Eric Lee / linux-smarc-t335x-v3.2

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Commit 89d6c0b5bdbb1927775584dcf532d98b3efe1477

Authored by Peter Zijlstra
Committed by Ingo Molnar
1 parent b79e8941fb
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

perf, arch: Add generic NODE cache events 

Add a NODE level to the generic cache events which is used to measure
local vs remote memory accesses. Like all other cache events, an
ACCESS is HIT+MISS, if there is no way to distinguish between reads
and writes do reads only etc..

The below needs filling out for !x86 (which I filled out with
unsupported events).

I'm fairly sure ARM can leave it like that since it doesn't strike me as
an architecture that even has NUMA support. SH might have something since
it does appear to have some NUMA bits.

Sparc64, PowerPC and MIPS certainly want a good look there since they
clearly are NUMA capable.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: David Miller <davem@davemloft.net>
Cc: Anton Blanchard <anton@samba.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 19 changed files with 298 additions and 2 deletions Side-by-side Diff

arch/arm/kernel/perf_event_v6.c
Diff comments   View file @ 89d6c0b
... ... @@ -173,6 +173,20 @@
173 173 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
174 174 },
175 175 },
  176 + [C(NODE)] = {
  177 + [C(OP_READ)] = {
  178 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  179 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  180 + },
  181 + [C(OP_WRITE)] = {
  182 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  183 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  184 + },
  185 + [C(OP_PREFETCH)] = {
  186 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  187 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  188 + },
  189 + },
176 190 };
177 191  
178 192 enum armv6mpcore_perf_types {
... ... @@ -297,6 +311,20 @@
297 311 },
298 312 },
299 313 [C(BPU)] = {
  314 + [C(OP_READ)] = {
  315 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  316 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  317 + },
  318 + [C(OP_WRITE)] = {
  319 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  320 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  321 + },
  322 + [C(OP_PREFETCH)] = {
  323 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  324 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  325 + },
  326 + },
  327 + [C(NODE)] = {
300 328 [C(OP_READ)] = {
301 329 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
302 330 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
arch/arm/kernel/perf_event_v7.c
Diff comments   View file @ 89d6c0b
... ... @@ -255,6 +255,20 @@
255 255 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
256 256 },
257 257 },
  258 + [C(NODE)] = {
  259 + [C(OP_READ)] = {
  260 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  261 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  262 + },
  263 + [C(OP_WRITE)] = {
  264 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  265 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  266 + },
  267 + [C(OP_PREFETCH)] = {
  268 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  269 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  270 + },
  271 + },
258 272 };
259 273  
260 274 /*
... ... @@ -365,6 +379,20 @@
365 379 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
366 380 [C(RESULT_MISS)]
367 381 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
  382 + },
  383 + [C(OP_PREFETCH)] = {
  384 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  385 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  386 + },
  387 + },
  388 + [C(NODE)] = {
  389 + [C(OP_READ)] = {
  390 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  391 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  392 + },
  393 + [C(OP_WRITE)] = {
  394 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  395 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
368 396 },
369 397 [C(OP_PREFETCH)] = {
370 398 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
arch/arm/kernel/perf_event_xscale.c
Diff comments   View file @ 89d6c0b
... ... @@ -144,6 +144,20 @@
144 144 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
145 145 },
146 146 },
  147 + [C(NODE)] = {
  148 + [C(OP_READ)] = {
  149 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  150 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  151 + },
  152 + [C(OP_WRITE)] = {
  153 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  154 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  155 + },
  156 + [C(OP_PREFETCH)] = {
  157 + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
  158 + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
  159 + },
  160 + },
147 161 };
148 162  
149 163 #define XSCALE_PMU_ENABLE 0x001
arch/mips/kernel/perf_event_mipsxx.c
Diff comments   View file @ 89d6c0b
... ... @@ -377,6 +377,20 @@
377 377 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
378 378 },
379 379 },
  380 +[C(NODE)] = {
  381 + [C(OP_READ)] = {
  382 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  383 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
  384 + },
  385 + [C(OP_WRITE)] = {
  386 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  387 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
  388 + },
  389 + [C(OP_PREFETCH)] = {
  390 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  391 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
  392 + },
  393 +},
380 394 };
381 395  
382 396 /* 74K core has completely different cache event map. */
... ... @@ -474,6 +488,20 @@
474 488 [C(OP_WRITE)] = {
475 489 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
476 490 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
  491 + },
  492 + [C(OP_PREFETCH)] = {
  493 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  494 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
  495 + },
  496 +},
  497 +[C(NODE)] = {
  498 + [C(OP_READ)] = {
  499 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  500 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
  501 + },
  502 + [C(OP_WRITE)] = {
  503 + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
  504 + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
477 505 },
478 506 [C(OP_PREFETCH)] = {
479 507 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
arch/powerpc/kernel/e500-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -75,6 +75,11 @@
75 75 [C(OP_WRITE)] = { -1, -1 },
76 76 [C(OP_PREFETCH)] = { -1, -1 },
77 77 },
  78 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  79 + [C(OP_READ)] = { -1, -1 },
  80 + [C(OP_WRITE)] = { -1, -1 },
  81 + [C(OP_PREFETCH)] = { -1, -1 },
  82 + },
78 83 };
79 84  
80 85 static int num_events = 128;
arch/powerpc/kernel/mpc7450-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -388,6 +388,11 @@
388 388 [C(OP_WRITE)] = { -1, -1 },
389 389 [C(OP_PREFETCH)] = { -1, -1 },
390 390 },
  391 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  392 + [C(OP_READ)] = { -1, -1 },
  393 + [C(OP_WRITE)] = { -1, -1 },
  394 + [C(OP_PREFETCH)] = { -1, -1 },
  395 + },
391 396 };
392 397  
393 398 struct power_pmu mpc7450_pmu = {
arch/powerpc/kernel/power4-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -587,6 +587,11 @@
587 587 [C(OP_WRITE)] = { -1, -1 },
588 588 [C(OP_PREFETCH)] = { -1, -1 },
589 589 },
  590 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  591 + [C(OP_READ)] = { -1, -1 },
  592 + [C(OP_WRITE)] = { -1, -1 },
  593 + [C(OP_PREFETCH)] = { -1, -1 },
  594 + },
590 595 };
591 596  
592 597 static struct power_pmu power4_pmu = {
arch/powerpc/kernel/power5+-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -653,6 +653,11 @@
653 653 [C(OP_WRITE)] = { -1, -1 },
654 654 [C(OP_PREFETCH)] = { -1, -1 },
655 655 },
  656 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  657 + [C(OP_READ)] = { -1, -1 },
  658 + [C(OP_WRITE)] = { -1, -1 },
  659 + [C(OP_PREFETCH)] = { -1, -1 },
  660 + },
656 661 };
657 662  
658 663 static struct power_pmu power5p_pmu = {
arch/powerpc/kernel/power5-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -595,6 +595,11 @@
595 595 [C(OP_WRITE)] = { -1, -1 },
596 596 [C(OP_PREFETCH)] = { -1, -1 },
597 597 },
  598 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  599 + [C(OP_READ)] = { -1, -1 },
  600 + [C(OP_WRITE)] = { -1, -1 },
  601 + [C(OP_PREFETCH)] = { -1, -1 },
  602 + },
598 603 };
599 604  
600 605 static struct power_pmu power5_pmu = {
arch/powerpc/kernel/power6-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -516,6 +516,11 @@
516 516 [C(OP_WRITE)] = { -1, -1 },
517 517 [C(OP_PREFETCH)] = { -1, -1 },
518 518 },
  519 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  520 + [C(OP_READ)] = { -1, -1 },
  521 + [C(OP_WRITE)] = { -1, -1 },
  522 + [C(OP_PREFETCH)] = { -1, -1 },
  523 + },
519 524 };
520 525  
521 526 static struct power_pmu power6_pmu = {
arch/powerpc/kernel/power7-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -342,6 +342,11 @@
342 342 [C(OP_WRITE)] = { -1, -1 },
343 343 [C(OP_PREFETCH)] = { -1, -1 },
344 344 },
  345 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  346 + [C(OP_READ)] = { -1, -1 },
  347 + [C(OP_WRITE)] = { -1, -1 },
  348 + [C(OP_PREFETCH)] = { -1, -1 },
  349 + },
345 350 };
346 351  
347 352 static struct power_pmu power7_pmu = {
arch/powerpc/kernel/ppc970-pmu.c
Diff comments   View file @ 89d6c0b
... ... @@ -467,6 +467,11 @@
467 467 [C(OP_WRITE)] = { -1, -1 },
468 468 [C(OP_PREFETCH)] = { -1, -1 },
469 469 },
  470 + [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
  471 + [C(OP_READ)] = { -1, -1 },
  472 + [C(OP_WRITE)] = { -1, -1 },
  473 + [C(OP_PREFETCH)] = { -1, -1 },
  474 + },
470 475 };
471 476  
472 477 static struct power_pmu ppc970_pmu = {
arch/sh/kernel/cpu/sh4/perf_event.c
Diff comments   View file @ 89d6c0b
... ... @@ -180,6 +180,21 @@
180 180 [ C(RESULT_MISS) ] = -1,
181 181 },
182 182 },
  183 +
  184 + [ C(NODE) ] = {
  185 + [ C(OP_READ) ] = {
  186 + [ C(RESULT_ACCESS) ] = -1,
  187 + [ C(RESULT_MISS) ] = -1,
  188 + },
  189 + [ C(OP_WRITE) ] = {
  190 + [ C(RESULT_ACCESS) ] = -1,
  191 + [ C(RESULT_MISS) ] = -1,
  192 + },
  193 + [ C(OP_PREFETCH) ] = {
  194 + [ C(RESULT_ACCESS) ] = -1,
  195 + [ C(RESULT_MISS) ] = -1,
  196 + },
  197 + },
183 198 };
184 199  
185 200 static int sh7750_event_map(int event)
arch/sh/kernel/cpu/sh4a/perf_event.c
Diff comments   View file @ 89d6c0b
... ... @@ -205,6 +205,21 @@
205 205 [ C(RESULT_MISS) ] = -1,
206 206 },
207 207 },
  208 +
  209 + [ C(NODE) ] = {
  210 + [ C(OP_READ) ] = {
  211 + [ C(RESULT_ACCESS) ] = -1,
  212 + [ C(RESULT_MISS) ] = -1,
  213 + },
  214 + [ C(OP_WRITE) ] = {
  215 + [ C(RESULT_ACCESS) ] = -1,
  216 + [ C(RESULT_MISS) ] = -1,
  217 + },
  218 + [ C(OP_PREFETCH) ] = {
  219 + [ C(RESULT_ACCESS) ] = -1,
  220 + [ C(RESULT_MISS) ] = -1,
  221 + },
  222 + },
208 223 };
209 224  
210 225 static int sh4a_event_map(int event)
arch/sparc/kernel/perf_event.c
Diff comments   View file @ 89d6c0b
... ... @@ -246,6 +246,20 @@
246 246 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
247 247 },
248 248 },
  249 +[C(NODE)] = {
  250 + [C(OP_READ)] = {
  251 + [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
  252 + [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  253 + },
  254 + [ C(OP_WRITE) ] = {
  255 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  256 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  257 + },
  258 + [ C(OP_PREFETCH) ] = {
  259 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  260 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  261 + },
  262 +},
249 263 };
250 264  
251 265 static const struct sparc_pmu ultra3_pmu = {
... ... @@ -361,6 +375,20 @@
361 375 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
362 376 },
363 377 },
  378 +[C(NODE)] = {
  379 + [C(OP_READ)] = {
  380 + [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
  381 + [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  382 + },
  383 + [ C(OP_WRITE) ] = {
  384 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  385 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  386 + },
  387 + [ C(OP_PREFETCH) ] = {
  388 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  389 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  390 + },
  391 +},
364 392 };
365 393  
366 394 static const struct sparc_pmu niagara1_pmu = {
... ... @@ -463,6 +491,20 @@
463 491 [C(OP_READ)] = {
464 492 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
465 493 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
  494 + },
  495 + [ C(OP_WRITE) ] = {
  496 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  497 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  498 + },
  499 + [ C(OP_PREFETCH) ] = {
  500 + [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
  501 + [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
  502 + },
  503 +},
  504 +[C(NODE)] = {
  505 + [C(OP_READ)] = {
  506 + [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
  507 + [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
466 508 },
467 509 [ C(OP_WRITE) ] = {
468 510 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
arch/x86/kernel/cpu/perf_event_amd.c
Diff comments   View file @ 89d6c0b
... ... @@ -89,6 +89,20 @@
89 89 [ C(RESULT_MISS) ] = -1,
90 90 },
91 91 },
  92 + [ C(NODE) ] = {
  93 + [ C(OP_READ) ] = {
  94 + [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
  95 + [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
  96 + },
  97 + [ C(OP_WRITE) ] = {
  98 + [ C(RESULT_ACCESS) ] = -1,
  99 + [ C(RESULT_MISS) ] = -1,
  100 + },
  101 + [ C(OP_PREFETCH) ] = {
  102 + [ C(RESULT_ACCESS) ] = -1,
  103 + [ C(RESULT_MISS) ] = -1,
  104 + },
  105 + },
92 106 };
93 107  
94 108 /*
arch/x86/kernel/cpu/perf_event_intel.c
Diff comments   View file @ 89d6c0b
... ... @@ -226,6 +226,21 @@
226 226 [ C(RESULT_MISS) ] = -1,
227 227 },
228 228 },
  229 + [ C(NODE) ] = {
  230 + [ C(OP_READ) ] = {
  231 + [ C(RESULT_ACCESS) ] = -1,
  232 + [ C(RESULT_MISS) ] = -1,
  233 + },
  234 + [ C(OP_WRITE) ] = {
  235 + [ C(RESULT_ACCESS) ] = -1,
  236 + [ C(RESULT_MISS) ] = -1,
  237 + },
  238 + [ C(OP_PREFETCH) ] = {
  239 + [ C(RESULT_ACCESS) ] = -1,
  240 + [ C(RESULT_MISS) ] = -1,
  241 + },
  242 + },
  243 +
229 244 };
230 245  
231 246 static __initconst const u64 westmere_hw_cache_event_ids
... ... @@ -327,6 +342,20 @@
327 342 [ C(RESULT_MISS) ] = -1,
328 343 },
329 344 },
  345 + [ C(NODE) ] = {
  346 + [ C(OP_READ) ] = {
  347 + [ C(RESULT_ACCESS) ] = 0x01b7,
  348 + [ C(RESULT_MISS) ] = 0x01b7,
  349 + },
  350 + [ C(OP_WRITE) ] = {
  351 + [ C(RESULT_ACCESS) ] = 0x01b7,
  352 + [ C(RESULT_MISS) ] = 0x01b7,
  353 + },
  354 + [ C(OP_PREFETCH) ] = {
  355 + [ C(RESULT_ACCESS) ] = 0x01b7,
  356 + [ C(RESULT_MISS) ] = 0x01b7,
  357 + },
  358 + },
330 359 };
331 360  
332 361 /*
... ... @@ -379,7 +408,21 @@
379 408 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
380 409 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
381 410 },
382   - }
  411 + },
  412 + [ C(NODE) ] = {
  413 + [ C(OP_READ) ] = {
  414 + [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
  415 + [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
  416 + },
  417 + [ C(OP_WRITE) ] = {
  418 + [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
  419 + [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
  420 + },
  421 + [ C(OP_PREFETCH) ] = {
  422 + [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
  423 + [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
  424 + },
  425 + },
383 426 };
384 427  
385 428 static __initconst const u64 nehalem_hw_cache_event_ids
... ... @@ -479,6 +522,20 @@
479 522 [ C(OP_PREFETCH) ] = {
480 523 [ C(RESULT_ACCESS) ] = -1,
481 524 [ C(RESULT_MISS) ] = -1,
  525 + },
  526 + },
  527 + [ C(NODE) ] = {
  528 + [ C(OP_READ) ] = {
  529 + [ C(RESULT_ACCESS) ] = 0x01b7,
  530 + [ C(RESULT_MISS) ] = 0x01b7,
  531 + },
  532 + [ C(OP_WRITE) ] = {
  533 + [ C(RESULT_ACCESS) ] = 0x01b7,
  534 + [ C(RESULT_MISS) ] = 0x01b7,
  535 + },
  536 + [ C(OP_PREFETCH) ] = {
  537 + [ C(RESULT_ACCESS) ] = 0x01b7,
  538 + [ C(RESULT_MISS) ] = 0x01b7,
482 539 },
483 540 },
484 541 };
arch/x86/kernel/cpu/perf_event_p4.c
Diff comments   View file @ 89d6c0b
... ... @@ -554,6 +554,20 @@
554 554 [ C(RESULT_MISS) ] = -1,
555 555 },
556 556 },
  557 + [ C(NODE) ] = {
  558 + [ C(OP_READ) ] = {
  559 + [ C(RESULT_ACCESS) ] = -1,
  560 + [ C(RESULT_MISS) ] = -1,
  561 + },
  562 + [ C(OP_WRITE) ] = {
  563 + [ C(RESULT_ACCESS) ] = -1,
  564 + [ C(RESULT_MISS) ] = -1,
  565 + },
  566 + [ C(OP_PREFETCH) ] = {
  567 + [ C(RESULT_ACCESS) ] = -1,
  568 + [ C(RESULT_MISS) ] = -1,
  569 + },
  570 + },
557 571 };
558 572  
559 573 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
include/linux/perf_event.h
Diff comments   View file @ 89d6c0b
... ... @@ -61,7 +61,7 @@
61 61 /*
62 62 * Generalized hardware cache events:
63 63 *
64   - * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x
  64 + * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
65 65 * { read, write, prefetch } x
66 66 * { accesses, misses }
67 67 */
... ... @@ -72,6 +72,7 @@
72 72 PERF_COUNT_HW_CACHE_DTLB = 3,
73 73 PERF_COUNT_HW_CACHE_ITLB = 4,
74 74 PERF_COUNT_HW_CACHE_BPU = 5,
  75 + PERF_COUNT_HW_CACHE_NODE = 6,
75 76  
76 77 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
77 78 };