Commit 8d3fdf31dd2066533861bb57ed7df1ae1b1f5fcc
1 parent
a8b7b34075
Exists in
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IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Showing 10 changed files with 169 additions and 234 deletions Side-by-side Diff
- arch/arm/mach-ixp4xx/avila-pci.c
- arch/arm/mach-ixp4xx/coyote-pci.c
- arch/arm/mach-ixp4xx/dsmg600-pci.c
- arch/arm/mach-ixp4xx/fsg-pci.c
- arch/arm/mach-ixp4xx/goramo_mlr.c
- arch/arm/mach-ixp4xx/gtwx5715-pci.c
- arch/arm/mach-ixp4xx/include/mach/irqs.h
- arch/arm/mach-ixp4xx/ixdp425-pci.c
- arch/arm/mach-ixp4xx/nas100d-pci.c
- arch/arm/mach-ixp4xx/nslu2-pci.c
arch/arm/mach-ixp4xx/avila-pci.c
... | ... | @@ -27,49 +27,40 @@ |
27 | 27 | #include <mach/hardware.h> |
28 | 28 | #include <asm/mach-types.h> |
29 | 29 | |
30 | -#define AVILA_PCI_MAX_DEV 4 | |
31 | -#define LOFT_PCI_MAX_DEV 6 | |
32 | -#define AVILA_PCI_IRQ_LINES 4 | |
30 | +#define AVILA_MAX_DEV 4 | |
31 | +#define LOFT_MAX_DEV 6 | |
32 | +#define IRQ_LINES 4 | |
33 | 33 | |
34 | 34 | /* PCI controller GPIO to IRQ pin mappings */ |
35 | -#define AVILA_PCI_INTA_PIN 11 | |
36 | -#define AVILA_PCI_INTB_PIN 10 | |
37 | -#define AVILA_PCI_INTC_PIN 9 | |
38 | -#define AVILA_PCI_INTD_PIN 8 | |
35 | +#define INTA 11 | |
36 | +#define INTB 10 | |
37 | +#define INTC 9 | |
38 | +#define INTD 8 | |
39 | 39 | |
40 | -#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 | |
41 | -#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 | |
42 | -#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 | |
43 | -#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 | |
44 | - | |
45 | 40 | void __init avila_pci_preinit(void) |
46 | 41 | { |
47 | - set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
48 | - set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
49 | - set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
50 | - set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | |
51 | - | |
42 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
43 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
44 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
45 | + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
52 | 46 | ixp4xx_pci_preinit(); |
53 | 47 | } |
54 | 48 | |
55 | 49 | static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
56 | 50 | { |
57 | - static int pci_irq_table[AVILA_PCI_IRQ_LINES] = { | |
58 | - IRQ_AVILA_PCI_INTA, | |
59 | - IRQ_AVILA_PCI_INTB, | |
60 | - IRQ_AVILA_PCI_INTC, | |
61 | - IRQ_AVILA_PCI_INTD | |
51 | + static int pci_irq_table[IRQ_LINES] = { | |
52 | + IXP4XX_GPIO_IRQ(INTA), | |
53 | + IXP4XX_GPIO_IRQ(INTB), | |
54 | + IXP4XX_GPIO_IRQ(INTC), | |
55 | + IXP4XX_GPIO_IRQ(INTD) | |
62 | 56 | }; |
63 | 57 | |
64 | - int irq = -1; | |
65 | - | |
66 | 58 | if (slot >= 1 && |
67 | - slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) && | |
68 | - pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) { | |
69 | - irq = pci_irq_table[(slot + pin - 2) % 4]; | |
70 | - } | |
59 | + slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && | |
60 | + pin >= 1 && pin <= IRQ_LINES) | |
61 | + return pci_irq_table[(slot + pin - 2) % 4]; | |
71 | 62 | |
72 | - return irq; | |
63 | + return -1; | |
73 | 64 | } |
74 | 65 | |
75 | 66 | struct hw_pci avila_pci __initdata = { |
arch/arm/mach-ixp4xx/coyote-pci.c
... | ... | @@ -23,30 +23,26 @@ |
23 | 23 | #include <asm/irq.h> |
24 | 24 | #include <asm/mach/pci.h> |
25 | 25 | |
26 | -#define COYOTE_PCI_SLOT0_DEVID 14 | |
27 | -#define COYOTE_PCI_SLOT1_DEVID 15 | |
26 | +#define SLOT0_DEVID 14 | |
27 | +#define SLOT1_DEVID 15 | |
28 | 28 | |
29 | 29 | /* PCI controller GPIO to IRQ pin mappings */ |
30 | -#define COYOTE_PCI_SLOT0_PIN 6 | |
31 | -#define COYOTE_PCI_SLOT1_PIN 11 | |
30 | +#define SLOT0_INTA 6 | |
31 | +#define SLOT1_INTA 11 | |
32 | 32 | |
33 | -#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 | |
34 | -#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 | |
35 | - | |
36 | 33 | void __init coyote_pci_preinit(void) |
37 | 34 | { |
38 | - set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); | |
39 | - set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); | |
40 | - | |
35 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); | |
36 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); | |
41 | 37 | ixp4xx_pci_preinit(); |
42 | 38 | } |
43 | 39 | |
44 | 40 | static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
45 | 41 | { |
46 | - if (slot == COYOTE_PCI_SLOT0_DEVID) | |
47 | - return IRQ_COYOTE_PCI_SLOT0; | |
48 | - else if (slot == COYOTE_PCI_SLOT1_DEVID) | |
49 | - return IRQ_COYOTE_PCI_SLOT1; | |
42 | + if (slot == SLOT0_DEVID) | |
43 | + return IXP4XX_GPIO_IRQ(SLOT0_INTA); | |
44 | + else if (slot == SLOT1_DEVID) | |
45 | + return IXP4XX_GPIO_IRQ(SLOT1_INTA); | |
50 | 46 | else return -1; |
51 | 47 | } |
52 | 48 |
arch/arm/mach-ixp4xx/dsmg600-pci.c
... | ... | @@ -22,53 +22,42 @@ |
22 | 22 | #include <asm/mach/pci.h> |
23 | 23 | #include <asm/mach-types.h> |
24 | 24 | |
25 | -#define DSMG600_PCI_MAX_DEV 4 | |
26 | -#define DSMG600_PCI_IRQ_LINES 3 | |
25 | +#define MAX_DEV 4 | |
26 | +#define IRQ_LINES 3 | |
27 | 27 | |
28 | 28 | /* PCI controller GPIO to IRQ pin mappings */ |
29 | -#define DSMG600_PCI_INTA_PIN 11 | |
30 | -#define DSMG600_PCI_INTB_PIN 10 | |
31 | -#define DSMG600_PCI_INTC_PIN 9 | |
32 | -#define DSMG600_PCI_INTD_PIN 8 | |
33 | -#define DSMG600_PCI_INTE_PIN 7 | |
34 | -#define DSMG600_PCI_INTF_PIN 6 | |
29 | +#define INTA 11 | |
30 | +#define INTB 10 | |
31 | +#define INTC 9 | |
32 | +#define INTD 8 | |
33 | +#define INTE 7 | |
34 | +#define INTF 6 | |
35 | 35 | |
36 | -#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 | |
37 | -#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 | |
38 | -#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 | |
39 | -#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 | |
40 | -#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 | |
41 | -#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 | |
42 | - | |
43 | 36 | void __init dsmg600_pci_preinit(void) |
44 | 37 | { |
45 | - set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
46 | - set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
47 | - set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
48 | - set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | |
49 | - set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | |
50 | - set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); | |
51 | - | |
38 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
39 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
40 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
41 | + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
42 | + set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | |
43 | + set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); | |
52 | 44 | ixp4xx_pci_preinit(); |
53 | 45 | } |
54 | 46 | |
55 | 47 | static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
56 | 48 | { |
57 | - static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = | |
58 | - { | |
59 | - { IRQ_DSMG600_PCI_INTE, -1, -1 }, | |
60 | - { IRQ_DSMG600_PCI_INTA, -1, -1 }, | |
61 | - { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, | |
62 | - { IRQ_DSMG600_PCI_INTF, -1, -1 }, | |
49 | + static int pci_irq_table[MAX_DEV][IRQ_LINES] = { | |
50 | + { IXP4XX_GPIO_IRQ(INTE), -1, -1 }, | |
51 | + { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, | |
52 | + { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), | |
53 | + IXP4XX_GPIO_IRQ(INTD) }, | |
54 | + { IXP4XX_GPIO_IRQ(INTF), -1, -1 }, | |
63 | 55 | }; |
64 | 56 | |
65 | - int irq = -1; | |
57 | + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) | |
58 | + return pci_irq_table[slot - 1][pin - 1]; | |
66 | 59 | |
67 | - if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV && | |
68 | - pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES) | |
69 | - irq = pci_irq_table[slot-1][pin-1]; | |
70 | - | |
71 | - return irq; | |
60 | + return -1; | |
72 | 61 | } |
73 | 62 | |
74 | 63 | struct hw_pci __initdata dsmg600_pci = { |
arch/arm/mach-ixp4xx/fsg-pci.c
... | ... | @@ -22,40 +22,35 @@ |
22 | 22 | #include <asm/mach/pci.h> |
23 | 23 | #include <asm/mach-types.h> |
24 | 24 | |
25 | -#define FSG_PCI_MAX_DEV 3 | |
26 | -#define FSG_PCI_IRQ_LINES 3 | |
25 | +#define MAX_DEV 3 | |
26 | +#define IRQ_LINES 3 | |
27 | 27 | |
28 | 28 | /* PCI controller GPIO to IRQ pin mappings */ |
29 | -#define FSG_PCI_INTA_PIN 6 | |
30 | -#define FSG_PCI_INTB_PIN 7 | |
31 | -#define FSG_PCI_INTC_PIN 5 | |
32 | -#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 | |
33 | -#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 | |
34 | -#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 | |
29 | +#define INTA 6 | |
30 | +#define INTB 7 | |
31 | +#define INTC 5 | |
35 | 32 | |
36 | 33 | void __init fsg_pci_preinit(void) |
37 | 34 | { |
38 | - set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
39 | - set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
40 | - set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
41 | - | |
35 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
36 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
37 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
42 | 38 | ixp4xx_pci_preinit(); |
43 | 39 | } |
44 | 40 | |
45 | 41 | static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
46 | 42 | { |
47 | - static int pci_irq_table[FSG_PCI_IRQ_LINES] = { | |
48 | - IRQ_FSG_PCI_INTC, | |
49 | - IRQ_FSG_PCI_INTB, | |
50 | - IRQ_FSG_PCI_INTA, | |
43 | + static int pci_irq_table[IRQ_LINES] = { | |
44 | + IXP4XX_GPIO_IRQ(INTC), | |
45 | + IXP4XX_GPIO_IRQ(INTB), | |
46 | + IXP4XX_GPIO_IRQ(INTA), | |
51 | 47 | }; |
52 | 48 | |
53 | 49 | int irq = -1; |
54 | - slot = slot - 11; | |
50 | + slot -= 11; | |
55 | 51 | |
56 | - if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && | |
57 | - pin >= 1 && pin <= FSG_PCI_IRQ_LINES) | |
58 | - irq = pci_irq_table[(slot - 1)]; | |
52 | + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) | |
53 | + irq = pci_irq_table[slot - 1]; | |
59 | 54 | printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", |
60 | 55 | __func__, slot, pin, irq); |
61 | 56 |
arch/arm/mach-ixp4xx/goramo_mlr.c
... | ... | @@ -17,29 +17,28 @@ |
17 | 17 | #include <asm/mach/flash.h> |
18 | 18 | #include <asm/mach/pci.h> |
19 | 19 | |
20 | -#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) | |
21 | -#define gpio_irq(n) xgpio_irq(n) | |
22 | - | |
23 | 20 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
24 | 21 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ |
25 | 22 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ |
26 | 23 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ |
27 | 24 | |
28 | -#define IRQ_ETHA IRQ_IXP4XX_GPIO4 | |
29 | -#define IRQ_ETHB IRQ_IXP4XX_GPIO5 | |
30 | -#define IRQ_NEC IRQ_IXP4XX_GPIO3 | |
31 | -#define IRQ_MPCI IRQ_IXP4XX_GPIO12 | |
32 | - | |
33 | 25 | /* GPIO lines */ |
34 | 26 | #define GPIO_SCL 0 |
35 | 27 | #define GPIO_SDA 1 |
36 | 28 | #define GPIO_STR 2 |
29 | +#define GPIO_IRQ_NEC 3 | |
30 | +#define GPIO_IRQ_ETHA 4 | |
31 | +#define GPIO_IRQ_ETHB 5 | |
37 | 32 | #define GPIO_HSS0_DCD_N 6 |
38 | 33 | #define GPIO_HSS1_DCD_N 7 |
34 | +#define GPIO_UART0_DCD 8 | |
35 | +#define GPIO_UART1_DCD 9 | |
39 | 36 | #define GPIO_HSS0_CTS_N 10 |
40 | 37 | #define GPIO_HSS1_CTS_N 11 |
38 | +#define GPIO_IRQ_MPCI 12 | |
41 | 39 | #define GPIO_HSS1_RTS_N 13 |
42 | 40 | #define GPIO_HSS0_RTS_N 14 |
41 | +/* GPIO15 is not connected */ | |
43 | 42 | |
44 | 43 | /* Control outputs from 74HC4094 */ |
45 | 44 | #define CONTROL_HSS0_CLK_INT 0 |
... | ... | @@ -152,7 +151,7 @@ |
152 | 151 | |
153 | 152 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) |
154 | 153 | { |
155 | - int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); | |
154 | + int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); | |
156 | 155 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
157 | 156 | set_carrier_cb_tab[port](pdev, !i); |
158 | 157 | return IRQ_HANDLED; |
159 | 158 | |
... | ... | @@ -165,9 +164,9 @@ |
165 | 164 | int i, irq; |
166 | 165 | |
167 | 166 | if (!port) |
168 | - irq = gpio_irq(GPIO_HSS0_DCD_N); | |
167 | + irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); | |
169 | 168 | else |
170 | - irq = gpio_irq(GPIO_HSS1_DCD_N); | |
169 | + irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); | |
171 | 170 | |
172 | 171 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
173 | 172 | set_carrier_cb(pdev, !i); |
... | ... | @@ -188,8 +187,8 @@ |
188 | 187 | |
189 | 188 | static void hss_close(int port, void *pdev) |
190 | 189 | { |
191 | - free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), | |
192 | - pdev); | |
190 | + free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : | |
191 | + IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); | |
193 | 192 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
194 | 193 | |
195 | 194 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); |
... | ... | @@ -421,8 +420,8 @@ |
421 | 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
422 | 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
423 | 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
424 | - set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | |
425 | - set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | |
423 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | |
424 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | |
426 | 425 | |
427 | 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
428 | 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
... | ... | @@ -442,10 +441,10 @@ |
442 | 441 | #ifdef CONFIG_PCI |
443 | 442 | static void __init gmlr_pci_preinit(void) |
444 | 443 | { |
445 | - set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); | |
446 | - set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); | |
447 | - set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); | |
448 | - set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); | |
444 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); | |
445 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); | |
446 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); | |
447 | + set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); | |
449 | 448 | ixp4xx_pci_preinit(); |
450 | 449 | } |
451 | 450 | |
... | ... | @@ -466,10 +465,10 @@ |
466 | 465 | static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
467 | 466 | { |
468 | 467 | switch(slot) { |
469 | - case SLOT_ETHA: return IRQ_ETHA; | |
470 | - case SLOT_ETHB: return IRQ_ETHB; | |
471 | - case SLOT_NEC: return IRQ_NEC; | |
472 | - default: return IRQ_MPCI; | |
468 | + case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); | |
469 | + case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); | |
470 | + case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); | |
471 | + default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); | |
473 | 472 | } |
474 | 473 | } |
475 | 474 |
arch/arm/mach-ixp4xx/gtwx5715-pci.c
... | ... | @@ -30,20 +30,16 @@ |
30 | 30 | #include <mach/hardware.h> |
31 | 31 | #include <asm/mach/pci.h> |
32 | 32 | |
33 | -#define GTWX5715_PCI_SLOT0_DEVID 0 | |
34 | -#define GTWX5715_PCI_SLOT0_INTA_GPIO 10 | |
35 | -#define GTWX5715_PCI_SLOT0_INTB_GPIO 11 | |
36 | -#define GTWX5715_PCI_SLOT0_INTA_IRQ IRQ_IXP4XX_GPIO10 | |
37 | -#define GTWX5715_PCI_SLOT0_INTB_IRQ IRQ_IXP4XX_GPIO11 | |
33 | +#define SLOT0_DEVID 0 | |
34 | +#define SLOT0_INTA 10 | |
35 | +#define SLOT0_INTB 11 | |
38 | 36 | |
39 | -#define GTWX5715_PCI_SLOT1_DEVID 1 | |
40 | -#define GTWX5715_PCI_SLOT1_INTA_GPIO 11 | |
41 | -#define GTWX5715_PCI_SLOT1_INTB_GPIO 10 | |
42 | -#define GTWX5715_PCI_SLOT1_INTA_IRQ IRQ_IXP4XX_GPIO11 | |
43 | -#define GTWX5715_PCI_SLOT1_INTB_IRQ IRQ_IXP4XX_GPIO10 | |
37 | +#define SLOT1_DEVID 1 | |
38 | +#define SLOT1_INTA 11 | |
39 | +#define SLOT1_INTB 10 | |
44 | 40 | |
45 | -#define GTWX5715_PCI_SLOT_COUNT 2 | |
46 | -#define GTWX5715_PCI_INT_PIN_COUNT 2 | |
41 | +#define SLOT_COUNT 2 | |
42 | +#define INT_PIN_COUNT 2 | |
47 | 43 | |
48 | 44 | /* |
49 | 45 | * Slot 0 isn't actually populated with a card connector but |
... | ... | @@ -53,11 +49,10 @@ |
53 | 49 | */ |
54 | 50 | void __init gtwx5715_pci_preinit(void) |
55 | 51 | { |
56 | - set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); | |
57 | - set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); | |
58 | - set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); | |
59 | - set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); | |
60 | - | |
52 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); | |
53 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTB), IRQ_TYPE_LEVEL_LOW); | |
54 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); | |
55 | + set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTB), IRQ_TYPE_LEVEL_LOW); | |
61 | 56 | ixp4xx_pci_preinit(); |
62 | 57 | } |
63 | 58 | |
64 | 59 | |
65 | 60 | |
66 | 61 | |
... | ... | @@ -65,20 +60,19 @@ |
65 | 60 | static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
66 | 61 | { |
67 | 62 | int rc; |
68 | - static int gtwx5715_irqmap | |
69 | - [GTWX5715_PCI_SLOT_COUNT] | |
70 | - [GTWX5715_PCI_INT_PIN_COUNT] = { | |
71 | - {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ}, | |
72 | - {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ}, | |
73 | -}; | |
63 | + static int gtwx5715_irqmap[SLOT_COUNT][INT_PIN_COUNT] = { | |
64 | + {IXP4XX_GPIO_IRQ(SLOT0_INTA), IXP4XX_GPIO_IRQ(SLOT0_INTB)}, | |
65 | + {IXP4XX_GPIO_IRQ(SLOT1_INTA), IXP4XX_GPIO_IRQ(SLOT1_INTB)}, | |
66 | + }; | |
74 | 67 | |
75 | - if (slot >= GTWX5715_PCI_SLOT_COUNT || | |
76 | - pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1; | |
68 | + if (slot >= SLOT_COUNT || pin >= INT_PIN_COUNT) | |
69 | + rc = -1; | |
77 | 70 | else |
78 | - rc = gtwx5715_irqmap[slot][pin-1]; | |
71 | + rc = gtwx5715_irqmap[slot][pin - 1]; | |
79 | 72 | |
80 | - printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); | |
81 | - return(rc); | |
73 | + printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", | |
74 | + __func__, slot, pin, rc); | |
75 | + return rc; | |
82 | 76 | } |
83 | 77 | |
84 | 78 | struct hw_pci gtwx5715_pci __initdata = { |
85 | 79 | |
... | ... | @@ -93,9 +87,7 @@ |
93 | 87 | int __init gtwx5715_pci_init(void) |
94 | 88 | { |
95 | 89 | if (machine_is_gtwx5715()) |
96 | - { | |
97 | 90 | pci_common_init(>wx5715_pci); |
98 | - } | |
99 | 91 | |
100 | 92 | return 0; |
101 | 93 | } |
arch/arm/mach-ixp4xx/include/mach/irqs.h
... | ... | @@ -15,7 +15,6 @@ |
15 | 15 | #ifndef _ARCH_IXP4XX_IRQS_H_ |
16 | 16 | #define _ARCH_IXP4XX_IRQS_H_ |
17 | 17 | |
18 | - | |
19 | 18 | #define IRQ_IXP4XX_NPEA 0 |
20 | 19 | #define IRQ_IXP4XX_NPEB 1 |
21 | 20 | #define IRQ_IXP4XX_NPEC 2 |
... | ... | @@ -58,6 +57,9 @@ |
58 | 57 | #define IRQ_IXP4XX_QM_PE 60 |
59 | 58 | #define IRQ_IXP4XX_MCU_ECC 61 |
60 | 59 | #define IRQ_IXP4XX_EXP_PE 62 |
60 | + | |
61 | +#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) | |
62 | +#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) | |
61 | 63 | |
62 | 64 | /* |
63 | 65 | * Only first 32 sources are valid if running on IXP42x systems |
arch/arm/mach-ixp4xx/ixdp425-pci.c
... | ... | @@ -24,47 +24,38 @@ |
24 | 24 | #include <mach/hardware.h> |
25 | 25 | #include <asm/mach-types.h> |
26 | 26 | |
27 | -#define IXDP425_PCI_MAX_DEV 4 | |
28 | -#define IXDP425_PCI_IRQ_LINES 4 | |
27 | +#define MAX_DEV 4 | |
28 | +#define IRQ_LINES 4 | |
29 | 29 | |
30 | 30 | /* PCI controller GPIO to IRQ pin mappings */ |
31 | -#define IXDP425_PCI_INTA_PIN 11 | |
32 | -#define IXDP425_PCI_INTB_PIN 10 | |
33 | -#define IXDP425_PCI_INTC_PIN 9 | |
34 | -#define IXDP425_PCI_INTD_PIN 8 | |
31 | +#define INTA 11 | |
32 | +#define INTB 10 | |
33 | +#define INTC 9 | |
34 | +#define INTD 8 | |
35 | 35 | |
36 | -#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 | |
37 | -#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 | |
38 | -#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 | |
39 | -#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 | |
40 | 36 | |
41 | 37 | void __init ixdp425_pci_preinit(void) |
42 | 38 | { |
43 | - set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
44 | - set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
45 | - set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
46 | - set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | |
47 | - | |
39 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
40 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
41 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
42 | + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
48 | 43 | ixp4xx_pci_preinit(); |
49 | 44 | } |
50 | 45 | |
51 | 46 | static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
52 | 47 | { |
53 | - static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = { | |
54 | - IRQ_IXDP425_PCI_INTA, | |
55 | - IRQ_IXDP425_PCI_INTB, | |
56 | - IRQ_IXDP425_PCI_INTC, | |
57 | - IRQ_IXDP425_PCI_INTD | |
48 | + static int pci_irq_table[IRQ_LINES] = { | |
49 | + IXP4XX_GPIO_IRQ(INTA), | |
50 | + IXP4XX_GPIO_IRQ(INTB), | |
51 | + IXP4XX_GPIO_IRQ(INTC), | |
52 | + IXP4XX_GPIO_IRQ(INTD) | |
58 | 53 | }; |
59 | 54 | |
60 | - int irq = -1; | |
55 | + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) | |
56 | + return pci_irq_table[(slot + pin - 2) % 4]; | |
61 | 57 | |
62 | - if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && | |
63 | - pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) { | |
64 | - irq = pci_irq_table[(slot + pin - 2) % 4]; | |
65 | - } | |
66 | - | |
67 | - return irq; | |
58 | + return -1; | |
68 | 59 | } |
69 | 60 | |
70 | 61 | struct hw_pci ixdp425_pci __initdata = { |
arch/arm/mach-ixp4xx/nas100d-pci.c
... | ... | @@ -21,49 +21,39 @@ |
21 | 21 | #include <asm/mach/pci.h> |
22 | 22 | #include <asm/mach-types.h> |
23 | 23 | |
24 | -#define NAS100D_PCI_MAX_DEV 3 | |
25 | -#define NAS100D_PCI_IRQ_LINES 3 | |
24 | +#define MAX_DEV 3 | |
25 | +#define IRQ_LINES 3 | |
26 | 26 | |
27 | 27 | /* PCI controller GPIO to IRQ pin mappings */ |
28 | -#define NAS100D_PCI_INTA_PIN 11 | |
29 | -#define NAS100D_PCI_INTB_PIN 10 | |
30 | -#define NAS100D_PCI_INTC_PIN 9 | |
31 | -#define NAS100D_PCI_INTD_PIN 8 | |
32 | -#define NAS100D_PCI_INTE_PIN 7 | |
28 | +#define INTA 11 | |
29 | +#define INTB 10 | |
30 | +#define INTC 9 | |
31 | +#define INTD 8 | |
32 | +#define INTE 7 | |
33 | 33 | |
34 | -#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 | |
35 | -#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 | |
36 | -#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 | |
37 | -#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 | |
38 | -#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 | |
39 | - | |
40 | 34 | void __init nas100d_pci_preinit(void) |
41 | 35 | { |
42 | - set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
43 | - set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
44 | - set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
45 | - set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | |
46 | - set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | |
47 | - | |
36 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
37 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
38 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
39 | + set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
40 | + set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | |
48 | 41 | ixp4xx_pci_preinit(); |
49 | 42 | } |
50 | 43 | |
51 | 44 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
52 | 45 | { |
53 | - static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = | |
54 | - { | |
55 | - { IRQ_NAS100D_PCI_INTA, -1, -1 }, | |
56 | - { IRQ_NAS100D_PCI_INTB, -1, -1 }, | |
57 | - { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, | |
46 | + static int pci_irq_table[MAX_DEV][IRQ_LINES] = { | |
47 | + { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, | |
48 | + { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, | |
49 | + { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), | |
50 | + IXP4XX_GPIO_IRQ(INTE) }, | |
58 | 51 | }; |
59 | 52 | |
60 | - int irq = -1; | |
53 | + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) | |
54 | + return pci_irq_table[slot - 1][pin - 1]; | |
61 | 55 | |
62 | - if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && | |
63 | - pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) | |
64 | - irq = pci_irq_table[slot-1][pin-1]; | |
65 | - | |
66 | - return irq; | |
56 | + return -1; | |
67 | 57 | } |
68 | 58 | |
69 | 59 | struct hw_pci __initdata nas100d_pci = { |
arch/arm/mach-ixp4xx/nslu2-pci.c
... | ... | @@ -21,43 +21,35 @@ |
21 | 21 | #include <asm/mach/pci.h> |
22 | 22 | #include <asm/mach-types.h> |
23 | 23 | |
24 | -#define NSLU2_PCI_MAX_DEV 3 | |
25 | -#define NSLU2_PCI_IRQ_LINES 3 | |
24 | +#define MAX_DEV 3 | |
25 | +#define IRQ_LINES 3 | |
26 | 26 | |
27 | 27 | /* PCI controller GPIO to IRQ pin mappings */ |
28 | -#define NSLU2_PCI_INTA_PIN 11 | |
29 | -#define NSLU2_PCI_INTB_PIN 10 | |
30 | -#define NSLU2_PCI_INTC_PIN 9 | |
31 | -#define NSLU2_PCI_INTD_PIN 8 | |
32 | -#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 | |
33 | -#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 | |
34 | -#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 | |
28 | +#define INTA 11 | |
29 | +#define INTB 10 | |
30 | +#define INTC 9 | |
31 | +#define INTD 8 | |
35 | 32 | |
36 | 33 | void __init nslu2_pci_preinit(void) |
37 | 34 | { |
38 | - set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | |
39 | - set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
40 | - set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
41 | - | |
35 | + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | |
36 | + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
37 | + set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
42 | 38 | ixp4xx_pci_preinit(); |
43 | 39 | } |
44 | 40 | |
45 | 41 | static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
46 | 42 | { |
47 | - static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = { | |
48 | - IRQ_NSLU2_PCI_INTA, | |
49 | - IRQ_NSLU2_PCI_INTB, | |
50 | - IRQ_NSLU2_PCI_INTC, | |
43 | + static int pci_irq_table[IRQ_LINES] = { | |
44 | + IXP4XX_GPIO_IRQ(INTA), | |
45 | + IXP4XX_GPIO_IRQ(INTB), | |
46 | + IXP4XX_GPIO_IRQ(INTC), | |
51 | 47 | }; |
52 | 48 | |
53 | - int irq = -1; | |
49 | + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) | |
50 | + return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; | |
54 | 51 | |
55 | - if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV && | |
56 | - pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) { | |
57 | - irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES]; | |
58 | - } | |
59 | - | |
60 | - return irq; | |
52 | + return -1; | |
61 | 53 | } |
62 | 54 | |
63 | 55 | struct hw_pci __initdata nslu2_pci = { |