Eric Lee / linux-smarc-t335x-v3.2

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Commit 98560bd83e73b5c0cf38e3d984892f46a405a172

Authored by Jesper Nilsson
1 parent 2d0503d1a6
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

CRIS: Add more delays in DDR setup 

Also, make DDR latency configurable.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>

Showing 3 changed files with 21 additions and 1 deletions Side-by-side Diff

arch/cris/arch-v32/mach-a3/Kconfig
Diff comments   View file @ 98560bd
... ... @@ -33,6 +33,10 @@
33 33 hex "DDR2 config"
34 34 default "0"
35 35  
  36 +config ETRAX_DDR2_LATENCY
  37 + hex "DDR2 latency"
  38 + default "0"
  39 +
36 40 config ETRAX_PIO_CE0_CFG
37 41 hex "PIO CE0 configuration"
38 42 default "0"
arch/cris/arch-v32/mach-a3/dram_init.S
Diff comments   View file @ 98560bd
... ... @@ -24,11 +24,21 @@
24 24  
25 25 ;; Refer to ddr2 MDS for initialization sequence
26 26  
  27 + ; 2. Wait 200us
  28 + move.d 10000, $r2
  29 +1: bne 1b
  30 + subq 1, $r2
  31 +
27 32 ; Start clock
28 33 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
29 34 move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
30 35 move.d $r1, [$r0]
31 36  
  37 + ; 2. Wait 200us
  38 + move.d 10000, $r2
  39 +1: bne 1b
  40 + subq 1, $r2
  41 +
32 42 ; Reset phy and start calibration
33 43 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
34 44 move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
... ... @@ -52,6 +62,10 @@
52 62 lslq 16, $r1
53 63 or.d $r3, $r1
54 64 move.d $r1, [$r0]
  65 + ; 2. Wait 200us
  66 + move.d 10000, $r4
  67 +1: bne 1b
  68 + subq 1, $r4
55 69 cmp.d sdram_commands_end, $r2
56 70 blo command_loop
57 71 nop
... ... @@ -63,7 +77,7 @@
63 77  
64 78 ; Set latency
65 79 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
66   - move.d 0x13, $r1
  80 + move.d CONFIG_ETRAX_DDR2_LATENCY, $r1
67 81 move.d $r1, [$r0]
68 82  
69 83 ; Set configuration
arch/cris/arch-v32/mach-a3/hw_settings.S
Diff comments   View file @ 98560bd
... ... @@ -31,6 +31,8 @@
31 31 ; Register values
32 32 .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
33 33 .dword CONFIG_ETRAX_DDR2_CONFIG
  34 + .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)
  35 + .dword CONFIG_ETRAX_DDR2_LATENCY
34 36 .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
35 37 .dword CONFIG_ETRAX_DDR2_TIMING
36 38 .dword CONFIG_ETRAX_DDR2_MRS