Eric Lee / linux-smarc-t335x-v3.2

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Commit ad68bb9f7a3cd47396635a5e3895215af57579da

Authored by Marek Vasut
Committed by Eric Miao
1 parent 851982c1b6
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

ARM: pxa: Access SMEMC via virtual addresses 

This is important because on PXA3xx, the physical mapping of SMEMC registers
differs from the one on PXA2xx. In order to get PCMCIA working on both PXA2xx
and PXA320, the PCMCIA driver was adjusted accordingly as well.

Also, various places in the kernel had to be patched to use
__raw_read/__raw_write.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

Showing 22 changed files with 176 additions and 136 deletions Side-by-side Diff

arch/arm/mach-pxa/cm-x2xx.c
Diff comments   View file @ ad68bb9
... ... @@ -24,6 +24,7 @@
24 24 #include <mach/pxa2xx-regs.h>
25 25 #include <mach/audio.h>
26 26 #include <mach/pxafb.h>
  27 +#include <mach/smemc.h>
27 28  
28 29 #include <asm/hardware/it8152.h>
29 30  
... ... @@ -392,9 +393,9 @@
392 393 cmx2xx_pci_suspend();
393 394  
394 395 /* save MSC registers */
395   - sleep_save_msc[0] = MSC0;
396   - sleep_save_msc[1] = MSC1;
397   - sleep_save_msc[2] = MSC2;
  396 + sleep_save_msc[0] = __raw_readl(MSC0);
  397 + sleep_save_msc[1] = __raw_readl(MSC1);
  398 + sleep_save_msc[2] = __raw_readl(MSC2);
398 399  
399 400 /* setup power saving mode registers */
400 401 PCFR = 0x0;
... ... @@ -416,9 +417,9 @@
416 417 cmx2xx_pci_resume();
417 418  
418 419 /* restore MSC registers */
419   - MSC0 = sleep_save_msc[0];
420   - MSC1 = sleep_save_msc[1];
421   - MSC2 = sleep_save_msc[2];
  420 + __raw_writel(sleep_save_msc[0], MSC0);
  421 + __raw_writel(sleep_save_msc[1], MSC1);
  422 + __raw_writel(sleep_save_msc[2], MSC2);
422 423  
423 424 return 0;
424 425 }
arch/arm/mach-pxa/cpufreq-pxa2xx.c
Diff comments   View file @ ad68bb9
... ... @@ -38,8 +38,10 @@
38 38 #include <linux/cpufreq.h>
39 39 #include <linux/err.h>
40 40 #include <linux/regulator/consumer.h>
  41 +#include <linux/io.h>
41 42  
42 43 #include <mach/pxa2xx-regs.h>
  44 +#include <mach/smemc.h>
43 45  
44 46 #ifdef DEBUG
45 47 static unsigned int freq_debug;
... ... @@ -242,7 +244,7 @@
242 244  
243 245 static void init_sdram_rows(void)
244 246 {
245   - uint32_t mdcnfg = MDCNFG;
  247 + uint32_t mdcnfg = __raw_readl(MDCNFG);
246 248 unsigned int drac2 = 0, drac0 = 0;
247 249  
248 250 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
... ... @@ -331,8 +333,8 @@
331 333 * we need to preset the smaller DRI before the change. If we're
332 334 * speeding up we need to set the larger DRI value after the change.
333 335 */
334   - preset_mdrefr = postset_mdrefr = MDREFR;
335   - if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
  336 + preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
  337 + if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
336 338 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
337 339 preset_mdrefr |= mdrefr_dri(new_freq_mem);
338 340 }
... ... @@ -370,7 +372,7 @@
370 372 3: nop \n\
371 373 "
372 374 : "=&r" (unused)
373   - : "r" (&MDREFR), "r" (cclkcfg),
  375 + : "r" (MDREFR), "r" (cclkcfg),
374 376 "r" (preset_mdrefr), "r" (postset_mdrefr)
375 377 : "r4", "r5");
376 378 local_irq_restore(flags);
arch/arm/mach-pxa/csb726.c
Diff comments   View file @ ad68bb9
... ... @@ -27,6 +27,7 @@
27 27 #include <mach/ohci.h>
28 28 #include <mach/pxa2xx-regs.h>
29 29 #include <mach/audio.h>
  30 +#include <mach/smemc.h>
30 31  
31 32 #include "generic.h"
32 33 #include "devices.h"
... ... @@ -255,9 +256,9 @@
255 256 static void __init csb726_init(void)
256 257 {
257 258 pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
258   -/* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */
259   -/* MSC2 = 0x06697ff4; *//* none/SM501 */
260   - MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
  259 +/* __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */
  260 +/* __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */
  261 + __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */
261 262  
262 263 pxa_set_ffuart_info(NULL);
263 264 pxa_set_btuart_info(NULL);
arch/arm/mach-pxa/generic.c
Diff comments   View file @ ad68bb9
... ... @@ -28,6 +28,7 @@
28 28  
29 29 #include <mach/reset.h>
30 30 #include <mach/gpio.h>
  31 +#include <mach/smemc.h>
31 32  
32 33 #include "generic.h"
33 34  
arch/arm/mach-pxa/h5000.c
Diff comments   View file @ ad68bb9
... ... @@ -32,6 +32,7 @@
32 32 #include <mach/pxa25x.h>
33 33 #include <mach/h5000.h>
34 34 #include <mach/udc.h>
  35 +#include <mach/smemc.h>
35 36  
36 37 #include "generic.h"
37 38  
38 39  
... ... @@ -172,11 +173,11 @@
172 173  
173 174 static void fix_msc(void)
174 175 {
175   - MSC0 = 0x129c24f2;
176   - MSC1 = 0x7ff424fa;
177   - MSC2 = 0x7ff47ff4;
  176 + __raw_writel(0x129c24f2, MSC0);
  177 + __raw_writel(0x7ff424fa, MSC1);
  178 + __raw_writel(0x7ff47ff4, MSC2);
178 179  
179   - MDREFR |= 0x02080000;
  180 + __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
180 181 }
181 182  
182 183 /*
arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
Diff comments   View file @ ad68bb9
... ... @@ -17,61 +17,6 @@
17 17 #include <mach/hardware.h>
18 18  
19 19 /*
20   - * Memory controller
21   - */
22   -
23   -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
24   -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
25   -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
26   -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
27   -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
28   -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
29   -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30   -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
31   -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
32   -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
33   -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
34   -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
35   -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
36   -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
37   -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
38   -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
39   -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
40   -
41   -/*
42   - * More handy macros for PCMCIA
43   - *
44   - * Arg is socket number
45   - */
46   -#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
47   -#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
48   -#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
49   -
50   -/* MECR register defines */
51   -#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
52   -#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
53   -
54   -#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
55   -#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
56   -#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
57   -#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58   -
59   -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
60   -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
61   -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
62   -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
63   -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
64   -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
65   -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
66   -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
67   -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
68   -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
69   -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
70   -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
71   -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
72   -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
73   -
74   -/*
75 20 * Power Manager
76 21 */
77 22  
arch/arm/mach-pxa/include/mach/smemc.h
Diff comments   View file @ ad68bb9
  1 +/*
  2 + * Static memory controller register definitions for PXA CPUs
  3 + *
  4 + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License version 2 as
  8 + * published by the Free Software Foundation.
  9 + */
  10 +
  11 +#ifndef __SMEMC_REGS_H
  12 +#define __SMEMC_REGS_H
  13 +
  14 +#define PXA2XX_SMEMC_BASE 0x48000000
  15 +#define PXA3XX_SMEMC_BASE 0x4a000000
  16 +#define SMEMC_VIRT 0xf6000000
  17 +
  18 +#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
  19 +#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
  20 +#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
  21 +#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
  22 +#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
  23 +#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
  24 +#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
  25 +#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */
  26 +#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */
  27 +#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
  28 +#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
  29 +#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */
  30 +#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */
  31 +#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
  32 +#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
  33 +#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
  34 +#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
  35 +#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */
  36 +#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */
  37 +#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */
  38 +#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */
  39 +#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */
  40 +
  41 +/*
  42 + * More handy macros for PCMCIA
  43 + *
  44 + * Arg is socket number
  45 + */
  46 +#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
  47 +#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */
  48 +#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */
  49 +
  50 +/* MECR register defines */
  51 +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
  52 +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
  53 +
  54 +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
  55 +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
  56 +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
  57 +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
  58 +
  59 +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
  60 +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
  61 +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
  62 +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
  63 +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
  64 +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
  65 +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
  66 +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
  67 +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
  68 +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
  69 +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
  70 +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
  71 +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
  72 +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
  73 +
  74 +#endif
arch/arm/mach-pxa/lpd270.c
Diff comments   View file @ ad68bb9
... ... @@ -46,6 +46,7 @@
46 46 #include <mach/mmc.h>
47 47 #include <mach/irda.h>
48 48 #include <mach/ohci.h>
  49 +#include <mach/smemc.h>
49 50  
50 51 #include "generic.h"
51 52 #include "devices.h"
... ... @@ -463,7 +464,7 @@
463 464 pxa_set_btuart_info(NULL);
464 465 pxa_set_stuart_info(NULL);
465 466  
466   - lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  467 + lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
467 468 lpd270_flash_data[1].width = 4;
468 469  
469 470 /*
arch/arm/mach-pxa/lubbock.c
Diff comments   View file @ ad68bb9
... ... @@ -50,6 +50,7 @@
50 50 #include <mach/pxafb.h>
51 51 #include <mach/mmc.h>
52 52 #include <mach/pm.h>
  53 +#include <mach/smemc.h>
53 54  
54 55 #include "generic.h"
55 56 #include "clock.h"
... ... @@ -525,7 +526,7 @@
525 526 pxa_set_ac97_info(NULL);
526 527  
527 528 lubbock_flash_data[0].width = lubbock_flash_data[1].width =
528   - (BOOT_DEF & 1) ? 2 : 4;
  529 + (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
529 530 /* Compensate for the nROMBT switch which swaps the flash banks */
530 531 printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
531 532 flashboot?"Flash":"ROM", flashboot);
arch/arm/mach-pxa/mainstone.c
Diff comments   View file @ ad68bb9
... ... @@ -51,6 +51,7 @@
51 51 #include <mach/irda.h>
52 52 #include <mach/ohci.h>
53 53 #include <plat/pxa27x_keypad.h>
  54 +#include <mach/smemc.h>
54 55  
55 56 #include "generic.h"
56 57 #include "devices.h"
... ... @@ -565,7 +566,7 @@
565 566 pxa_set_btuart_info(NULL);
566 567 pxa_set_stuart_info(NULL);
567 568  
568   - mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  569 + mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
569 570 mst_flash_data[1].width = 4;
570 571  
571 572 /* Compensate for SW7 which swaps the flash banks */
arch/arm/mach-pxa/pxa25x.c
Diff comments   View file @ ad68bb9
... ... @@ -31,6 +31,7 @@
31 31 #include <mach/reset.h>
32 32 #include <mach/pm.h>
33 33 #include <mach/dma.h>
  34 +#include <mach/smemc.h>
34 35  
35 36 #include "generic.h"
36 37 #include "devices.h"
... ... @@ -323,8 +324,8 @@
323 324  
324 325 static struct map_desc pxa25x_io_desc[] __initdata = {
325 326 { /* Mem Ctl */
326   - .virtual = 0xf6000000,
327   - .pfn = __phys_to_pfn(0x48000000),
  327 + .virtual = SMEMC_VIRT,
  328 + .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
328 329 .length = 0x00200000,
329 330 .type = MT_DEVICE
330 331 },
arch/arm/mach-pxa/pxa27x.c
Diff comments   View file @ ad68bb9
... ... @@ -17,6 +17,7 @@
17 17 #include <linux/suspend.h>
18 18 #include <linux/platform_device.h>
19 19 #include <linux/sysdev.h>
  20 +#include <linux/io.h>
20 21  
21 22 #include <asm/mach/map.h>
22 23 #include <mach/hardware.h>
... ... @@ -28,6 +29,8 @@
28 29 #include <mach/ohci.h>
29 30 #include <mach/pm.h>
30 31 #include <mach/dma.h>
  32 +#include <mach/smemc.h>
  33 +
31 34 #include <plat/i2c.h>
32 35  
33 36 #include "generic.h"
... ... @@ -255,7 +258,7 @@
255 258  
256 259 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
257 260 {
258   - SAVE(MDREFR);
  261 + sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
259 262 SAVE(PCFR);
260 263  
261 264 SAVE(CKEN);
... ... @@ -264,7 +267,7 @@
264 267  
265 268 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
266 269 {
267   - RESTORE(MDREFR);
  270 + __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
268 271 RESTORE(PCFR);
269 272  
270 273 PSSR = PSSR_RDH | PSSR_PH;
... ... @@ -373,8 +376,8 @@
373 376  
374 377 static struct map_desc pxa27x_io_desc[] __initdata = {
375 378 { /* Mem Ctl */
376   - .virtual = 0xf6000000,
377   - .pfn = __phys_to_pfn(0x48000000),
  379 + .virtual = SMEMC_VIRT,
  380 + .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
378 381 .length = 0x00200000,
379 382 .type = MT_DEVICE
380 383 }, { /* IMem ctl */
arch/arm/mach-pxa/pxa3xx.c
Diff comments   View file @ ad68bb9
... ... @@ -31,6 +31,7 @@
31 31 #include <mach/pm.h>
32 32 #include <mach/dma.h>
33 33 #include <mach/regs-intc.h>
  34 +#include <mach/smemc.h>
34 35 #include <plat/i2c.h>
35 36  
36 37 #include "generic.h"
... ... @@ -583,8 +584,8 @@
583 584  
584 585 static struct map_desc pxa3xx_io_desc[] __initdata = {
585 586 { /* Mem Ctl */
586   - .virtual = 0xf6000000,
587   - .pfn = __phys_to_pfn(0x4a000000),
  587 + .virtual = SMEMC_VIRT,
  588 + .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
588 589 .length = 0x00200000,
589 590 .type = MT_DEVICE
590 591 }
arch/arm/mach-pxa/sleep.S
Diff comments   View file @ ad68bb9
... ... @@ -14,7 +14,7 @@
14 14 #include <linux/linkage.h>
15 15 #include <asm/assembler.h>
16 16 #include <mach/hardware.h>
17   -
  17 +#include <mach/smemc.h>
18 18 #include <mach/pxa2xx-regs.h>
19 19  
20 20 #define MDREFR_KDIV 0x200a4000 // all banks
arch/arm/mach-pxa/smemc.c
Diff comments   View file @ ad68bb9
... ... @@ -9,50 +9,37 @@
9 9 #include <linux/sysdev.h>
10 10  
11 11 #include <mach/hardware.h>
  12 +#include <mach/smemc.h>
12 13  
13   -#define SMEMC_PHYS_BASE (0x4A000000)
14   -#define SMEMC_PHYS_SIZE (0x90)
15   -
16   -#define MSC0 (0x08) /* Static Memory Controller Register 0 */
17   -#define MSC1 (0x0C) /* Static Memory Controller Register 1 */
18   -#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */
19   -#define MEMCLKCFG (0x68) /* Clock Configuration */
20   -#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */
21   -#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */
22   -#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */
23   -#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */
24   -
25 14 #ifdef CONFIG_PM
26   -static void __iomem *smemc_mmio_base;
27   -
28 15 static unsigned long msc[2];
29 16 static unsigned long sxcnfg, memclkcfg;
30 17 static unsigned long csadrcfg[4];
31 18  
32 19 static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
33 20 {
34   - msc[0] = __raw_readl(smemc_mmio_base + MSC0);
35   - msc[1] = __raw_readl(smemc_mmio_base + MSC1);
36   - sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
37   - memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
38   - csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
39   - csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
40   - csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
41   - csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
  21 + msc[0] = __raw_readl(MSC0);
  22 + msc[1] = __raw_readl(MSC1);
  23 + sxcnfg = __raw_readl(SXCNFG);
  24 + memclkcfg = __raw_readl(MEMCLKCFG);
  25 + csadrcfg[0] = __raw_readl(CSADRCFG0);
  26 + csadrcfg[1] = __raw_readl(CSADRCFG1);
  27 + csadrcfg[2] = __raw_readl(CSADRCFG2);
  28 + csadrcfg[3] = __raw_readl(CSADRCFG3);
42 29  
43 30 return 0;
44 31 }
45 32  
46 33 static int pxa3xx_smemc_resume(struct sys_device *dev)
47 34 {
48   - __raw_writel(msc[0], smemc_mmio_base + MSC0);
49   - __raw_writel(msc[1], smemc_mmio_base + MSC1);
50   - __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
51   - __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
52   - __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
53   - __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
54   - __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
55   - __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
  35 + __raw_writel(msc[0], MSC0);
  36 + __raw_writel(msc[1], MSC1);
  37 + __raw_writel(sxcnfg, SXCNFG);
  38 + __raw_writel(memclkcfg, MEMCLKCFG);
  39 + __raw_writel(csadrcfg[0], CSADRCFG0);
  40 + __raw_writel(csadrcfg[1], CSADRCFG1);
  41 + __raw_writel(csadrcfg[2], CSADRCFG2);
  42 + __raw_writel(csadrcfg[3], CSADRCFG3);
56 43  
57 44 return 0;
58 45 }
... ... @@ -73,10 +60,6 @@
73 60 int ret = 0;
74 61  
75 62 if (cpu_is_pxa3xx()) {
76   - smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
77   - if (smemc_mmio_base == NULL)
78   - return -ENODEV;
79   -
80 63 ret = sysdev_class_register(&smemc_sysclass);
81 64 if (ret)
82 65 return ret;
arch/arm/mach-pxa/spitz.c
Diff comments   View file @ ad68bb9
... ... @@ -45,6 +45,7 @@
45 45 #include <mach/pxa2xx_spi.h>
46 46 #include <mach/spitz.h>
47 47 #include <mach/sharpsl_pm.h>
  48 +#include <mach/smemc.h>
48 49  
49 50 #include <plat/i2c.h>
50 51  
51 52  
... ... @@ -930,9 +931,10 @@
930 931  
931 932 static void spitz_restart(char mode, const char *cmd)
932 933 {
  934 + uint32_t msc0 = __raw_readl(MSC0);
933 935 /* Bootloader magic for a reboot */
934   - if ((MSC0 & 0xffff0000) == 0x7ff00000)
935   - MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
  936 + if ((msc0 & 0xffff0000) == 0x7ff00000)
  937 + __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
936 938  
937 939 spitz_poweroff();
938 940 }
arch/arm/mach-pxa/stargate2.c
Diff comments   View file @ ad68bb9
... ... @@ -48,6 +48,7 @@
48 48 #include <mach/udc.h>
49 49 #include <mach/pxa2xx_spi.h>
50 50 #include <mach/pxa27x-udc.h>
  51 +#include <mach/smemc.h>
51 52  
52 53 #include <linux/spi/spi.h>
53 54 #include <linux/mfd/da903x.h>
... ... @@ -976,7 +977,7 @@
976 977 {
977 978 /* This is probably a board specific hack as this must be set
978 979 prior to connecting the MFP stuff up. */
979   - MECR &= ~MECR_NOS;
  980 + __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR);
980 981  
981 982 pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
982 983  
arch/arm/mach-pxa/tosa.c
Diff comments   View file @ ad68bb9
... ... @@ -46,6 +46,7 @@
46 46 #include <mach/tosa_bt.h>
47 47 #include <mach/pxa2xx_spi.h>
48 48 #include <mach/audio.h>
  49 +#include <mach/smemc.h>
49 50  
50 51 #include <asm/mach/arch.h>
51 52 #include <mach/tosa.h>
52 53  
... ... @@ -893,9 +894,11 @@
893 894  
894 895 static void tosa_restart(char mode, const char *cmd)
895 896 {
  897 + uint32_t msc0 = __raw_readl(MSC0);
  898 +
896 899 /* Bootloader magic for a reboot */
897   - if((MSC0 & 0xffff0000) == 0x7ff00000)
898   - MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
  900 + if((msc0 & 0xffff0000) == 0x7ff00000)
  901 + __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
899 902  
900 903 tosa_poweroff();
901 904 }
arch/arm/mach-pxa/trizeps4.c
Diff comments   View file @ ad68bb9
... ... @@ -47,6 +47,7 @@
47 47 #include <mach/mmc.h>
48 48 #include <mach/irda.h>
49 49 #include <mach/ohci.h>
  50 +#include <mach/smemc.h>
50 51 #include <plat/i2c.h>
51 52  
52 53 #include "generic.h"
... ... @@ -542,7 +543,7 @@
542 543 pxa27x_map_io();
543 544 iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
544 545  
545   - if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) {
  546 + if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) {
546 547 /* if flash is 16 bit wide its a Trizeps4 WL */
547 548 __machine_arch_type = MACH_TYPE_TRIZEPS4WL;
548 549 trizeps4_flash_data[0].width = 2;
arch/arm/mach-pxa/xcep.c
Diff comments   View file @ ad68bb9
... ... @@ -31,6 +31,7 @@
31 31 #include <mach/hardware.h>
32 32 #include <mach/pxa2xx-regs.h>
33 33 #include <mach/mfp-pxa25x.h>
  34 +#include <mach/smemc.h>
34 35  
35 36 #include "generic.h"
36 37  
37 38  
... ... @@ -172,9 +173,9 @@
172 173  
173 174 /* See Intel XScale Developer's Guide for details */
174 175 /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
175   - MSC1 = (MSC1 & 0xffff) | 0xD5540000;
  176 + __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
176 177 /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
177   - MSC2 = (MSC2 & 0xffff) | 0x72A00000;
  178 + __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);
178 179  
179 180 platform_add_devices(ARRAY_AND_SIZE(devices));
180 181 pxa_set_i2c_info(&xcep_i2c_platform_data);
arch/arm/mach-pxa/zeus.c
Diff comments   View file @ ad68bb9
... ... @@ -47,6 +47,7 @@
47 47 #include <mach/audio.h>
48 48 #include <mach/arcom-pcmcia.h>
49 49 #include <mach/zeus.h>
  50 +#include <mach/smemc.h>
50 51  
51 52 #include "generic.h"
52 53  
53 54  
... ... @@ -823,13 +824,16 @@
823 824 static void __init zeus_init(void)
824 825 {
825 826 u16 dm9000_msc = DM9K_MSC_VALUE;
  827 + u32 msc0, msc1;
826 828  
827 829 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
828 830 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
829 831  
830 832 /* Fix timings for dm9000s (CS1/CS2)*/
831   - MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
832   - MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
  833 + msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16);
  834 + msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc;
  835 + __raw_writel(msc0, MSC0);
  836 + __raw_writel(msc1, MSC1);
833 837  
834 838 pm_power_off = zeus_power_off;
835 839 zeus_setup_apm();
drivers/pcmcia/pxa2xx_base.c
Diff comments   View file @ ad68bb9
... ... @@ -26,6 +26,7 @@
26 26 #include <linux/platform_device.h>
27 27  
28 28 #include <mach/hardware.h>
  29 +#include <mach/smemc.h>
29 30 #include <asm/io.h>
30 31 #include <asm/irq.h>
31 32 #include <asm/system.h>
32 33  
33 34  
34 35  
35 36  
36 37  
... ... @@ -116,37 +117,49 @@
116 117  
117 118 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
118 119 {
119   - MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
  120 + uint32_t val;
  121 +
  122 + val = ((pxa2xx_mcxx_setup(speed, clock)
120 123 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
121 124 | ((pxa2xx_mcxx_asst(speed, clock)
122 125 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
123 126 | ((pxa2xx_mcxx_hold(speed, clock)
124 127 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
125 128  
  129 + __raw_writel(val, MCMEM(sock));
  130 +
126 131 return 0;
127 132 }
128 133  
129 134 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
130 135 {
131   - MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
  136 + uint32_t val;
  137 +
  138 + val = ((pxa2xx_mcxx_setup(speed, clock)
132 139 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
133 140 | ((pxa2xx_mcxx_asst(speed, clock)
134 141 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
135 142 | ((pxa2xx_mcxx_hold(speed, clock)
136 143 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
137 144  
  145 + __raw_writel(val, MCIO(sock));
  146 +
138 147 return 0;
139 148 }
140 149  
141 150 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
142 151 {
143   - MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
  152 + uint32_t val;
  153 +
  154 + val = ((pxa2xx_mcxx_setup(speed, clock)
144 155 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
145 156 | ((pxa2xx_mcxx_asst(speed, clock)
146 157 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
147 158 | ((pxa2xx_mcxx_hold(speed, clock)
148 159 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
149 160  
  161 + __raw_writel(val, MCATT(sock));
  162 +
150 163 return 0;
151 164 }
152 165  
153 166  
154 167  
... ... @@ -205,19 +218,18 @@
205 218 static void pxa2xx_configure_sockets(struct device *dev)
206 219 {
207 220 struct pcmcia_low_level *ops = dev->platform_data;
208   -
209 221 /*
210 222 * We have at least one socket, so set MECR:CIT
211 223 * (Card Is There)
212 224 */
213   - MECR |= MECR_CIT;
  225 + uint32_t mecr = MECR_CIT;
214 226  
215 227 /* Set MECR:NOS (Number Of Sockets) */
216 228 if ((ops->first + ops->nr) > 1 ||
217 229 machine_is_viper() || machine_is_arcom_zeus())
218   - MECR |= MECR_NOS;
219   - else
220   - MECR &= ~MECR_NOS;
  230 + mecr |= MECR_NOS;
  231 +
  232 + __raw_writel(mecr, MECR);
221 233 }
222 234  
223 235 static const char *skt_names[] = {