Eric Lee / linux-smarc-t335x-v3.2

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Commit b2e68aa337f950e4a8c893a82b95b1755309bc56

Authored by Maciej W. Rozycki
Committed by Jeff Garzik
1 parent c3a9392e4f
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[PATCH] defxx: Big-endian hosts support 

The PDQ DMA engine requires a different byte-swapping mode for big-endian
hosts; also the MAC address which is read from a register through PIO has
to be byte-swapped.  These changes have been verified with DEFPA-DC (PCI)
boards and a Broadcom BCM91250A (MIPS CPU based) host.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

Showing 2 changed files with 31 additions and 23 deletions Inline Diff

1 /* 1 /*
2 * File Name: 2 * File Name:
3 * defxx.c 3 * defxx.c
4 * 4 *
5 * Copyright Information: 5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996. 6 * Copyright Digital Equipment Corporation 1996.
7 * 7 *
8 * This software may be used and distributed according to the terms of 8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference. 9 * the GNU General Public License, incorporated herein by reference.
10 * 10 *
11 * Abstract: 11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation 12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include: 13 * FDDI EISA and PCI controller families. Supported adapters include:
14 * 14 *
15 * DEC FDDIcontroller/EISA (DEFEA) 15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA) 16 * DEC FDDIcontroller/PCI (DEFPA)
17 * 17 *
18 * The original author: 18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
20 * 20 *
21 * Maintainers: 21 * Maintainers:
22 * macro Maciej W. Rozycki <macro@linux-mips.org> 22 * macro Maciej W. Rozycki <macro@linux-mips.org>
23 * 23 *
24 * Credits: 24 * Credits:
25 * I'd like to thank Patricia Cross for helping me get started with 25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring 26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver 27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and 28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS 29 * integration help on getting FDDI support into Linux. LVS
30 * 30 *
31 * Driver Architecture: 31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work 32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and 33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers 34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
36 * driver. 36 * driver.
37 * 37 *
38 * Adapter Probe - 38 * Adapter Probe -
39 * The driver scans for supported EISA adapters by reading the 39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match 40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value. 41 * against the expected value.
42 * 42 *
43 * Bus-Specific Initialization - 43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller 44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar 45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After 46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the 47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the 48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families. 49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured 50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers. 51 * to I/O map, rather than memory map, the adapter registers.
52 * 52 *
53 * Driver Open/Close - 53 * Driver Open/Close -
54 * In the driver open routine, the driver ISR (interrupt service 54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an 55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite 56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is 57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive 58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following 59 * commands to bring the adapter up and down as in the following
60 * example: 60 * example:
61 * ifconfig fddi0 up 61 * ifconfig fddi0 up
62 * ifconfig fddi0 down 62 * ifconfig fddi0 down
63 * ifconfig fddi0 up 63 * ifconfig fddi0 up
64 * 64 *
65 * Driver Shutdown - 65 * Driver Shutdown -
66 * Apparently, there is no shutdown or halt routine support under 66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or 67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe 68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user 69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However, 71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues 72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization. 73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where 74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented. 75 * Alan indicated that a shutdown handler may be implemented.
76 * 76 *
77 * Interrupt Service Routine - 77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for 78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's 79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt 80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards. 81 * processing to support shared interrupts and multiple boards.
82 * 82 *
83 * Interrupt enabling/disabling can occur at many levels. At the host 83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the 84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA 86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable. 87 * controller interrupt enable/disable.
88 * 88 *
89 * The driver currently enables and disables adapter interrupts at the 89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or 90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips. 91 * acknowledging any host-based interrupt chips.
92 * 92 *
93 * Control Functions - 93 * Control Functions -
94 * Control functions are those used to support functions such as adding 94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet 95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently, 96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and 97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible 98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include: 99 * enhancements include:
100 * 100 *
101 * - Custom ioctl interface for executing port interface commands 101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to 102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions). 103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades. 104 * - Custom ioctl interface for supporting firmware upgrades.
105 * 105 *
106 * Hardware (port interface) Support Routines - 106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent 107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They 108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter, 109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the 110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the 111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and 112 * port interface, these routines were written to be as generic and
113 * usable as possible. 113 * usable as possible.
114 * 114 *
115 * Receive Path - 115 * Receive Path -
116 * The adapter DMA engine supports a 256 entry receive descriptor block 116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The 117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in 118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the 119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data, 120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the 121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle 122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments 123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts 124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a 125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive 127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer. 128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at 129 * This is a performance enhancement that should be looked into at
130 * some point. 130 * some point.
131 * 131 *
132 * Transmit Path - 132 * Transmit Path -
133 * Like the receive path, the adapter DMA engine supports a 256 entry 133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at 134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255 135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one 136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request. 137 * fragment per transmit packet request.
138 * 138 *
139 * The fragment contains the entire packet from FC to end of data. 139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte 140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip 141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to 142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether 143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH 144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets, 145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines, 146 * the driver, rather than the common FDDI packet handler routines,
147 * sets these bytes. 147 * sets these bytes.
148 * 148 *
149 * To reduce the amount of descriptor fetches needed per transmit request, 149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three 150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit 151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set 152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH. 155 * bytes which we'll use to store the PRH.
156 * 156 *
157 * There's a subtle advantage to adding these pad bytes to the 157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for 158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying 160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should 161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c 162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased. 163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet, 164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at 165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size. 166 * least 24 bytes in size.
167 * 167 *
168 * Modification History: 168 * Modification History:
169 * Date Name Description 169 * Date Name Description
170 * 16-Aug-96 LVS Created. 170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information 171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are 172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy 173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is 174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer. 175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list 177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous 178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set. 179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb 180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address 181 * on Alan Cox recommendation. Added node address
182 * override support. 182 * override support.
183 * 12-Sep-96 LVS Reset current address to factory address during 183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a 184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data. 185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x 186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups 187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes 188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes 190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups. 191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API. 192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported. 193 * 14 Aug 2004 macro Fix device names reported.
194 * 14 Jun 2005 macro Use irqreturn_t. 194 * 14 Jun 2005 macro Use irqreturn_t.
195 * 23 Oct 2006 macro Big-endian host support.
195 */ 196 */
196 197
197 /* Include files */ 198 /* Include files */
198 199
199 #include <linux/module.h> 200 #include <linux/module.h>
200 #include <linux/kernel.h> 201 #include <linux/kernel.h>
201 #include <linux/string.h> 202 #include <linux/string.h>
202 #include <linux/errno.h> 203 #include <linux/errno.h>
203 #include <linux/ioport.h> 204 #include <linux/ioport.h>
204 #include <linux/slab.h> 205 #include <linux/slab.h>
205 #include <linux/interrupt.h> 206 #include <linux/interrupt.h>
206 #include <linux/pci.h> 207 #include <linux/pci.h>
207 #include <linux/delay.h> 208 #include <linux/delay.h>
208 #include <linux/init.h> 209 #include <linux/init.h>
209 #include <linux/netdevice.h> 210 #include <linux/netdevice.h>
210 #include <linux/fddidevice.h> 211 #include <linux/fddidevice.h>
211 #include <linux/skbuff.h> 212 #include <linux/skbuff.h>
212 #include <linux/bitops.h> 213 #include <linux/bitops.h>
213 214
214 #include <asm/byteorder.h> 215 #include <asm/byteorder.h>
215 #include <asm/io.h> 216 #include <asm/io.h>
216 217
217 #include "defxx.h" 218 #include "defxx.h"
218 219
219 /* Version information string should be updated prior to each new release! */ 220 /* Version information string should be updated prior to each new release! */
220 #define DRV_NAME "defxx" 221 #define DRV_NAME "defxx"
221 #define DRV_VERSION "v1.08" 222 #define DRV_VERSION "v1.09"
222 #define DRV_RELDATE "2005/06/14" 223 #define DRV_RELDATE "2006/10/23"
223 224
224 static char version[] __devinitdata = 225 static char version[] __devinitdata =
225 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 226 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
226 " Lawrence V. Stefani and others\n"; 227 " Lawrence V. Stefani and others\n";
227 228
228 #define DYNAMIC_BUFFERS 1 229 #define DYNAMIC_BUFFERS 1
229 230
230 #define SKBUFF_RX_COPYBREAK 200 231 #define SKBUFF_RX_COPYBREAK 200
231 /* 232 /*
232 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 233 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
233 * alignment for compatibility with old EISA boards. 234 * alignment for compatibility with old EISA boards.
234 */ 235 */
235 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 236 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
236 237
237 /* Define module-wide (static) routines */ 238 /* Define module-wide (static) routines */
238 239
239 static void dfx_bus_init(struct net_device *dev); 240 static void dfx_bus_init(struct net_device *dev);
240 static void dfx_bus_config_check(DFX_board_t *bp); 241 static void dfx_bus_config_check(DFX_board_t *bp);
241 242
242 static int dfx_driver_init(struct net_device *dev, const char *print_name); 243 static int dfx_driver_init(struct net_device *dev, const char *print_name);
243 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 244 static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
244 245
245 static int dfx_open(struct net_device *dev); 246 static int dfx_open(struct net_device *dev);
246 static int dfx_close(struct net_device *dev); 247 static int dfx_close(struct net_device *dev);
247 248
248 static void dfx_int_pr_halt_id(DFX_board_t *bp); 249 static void dfx_int_pr_halt_id(DFX_board_t *bp);
249 static void dfx_int_type_0_process(DFX_board_t *bp); 250 static void dfx_int_type_0_process(DFX_board_t *bp);
250 static void dfx_int_common(struct net_device *dev); 251 static void dfx_int_common(struct net_device *dev);
251 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 252 static irqreturn_t dfx_interrupt(int irq, void *dev_id);
252 253
253 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 254 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
254 static void dfx_ctl_set_multicast_list(struct net_device *dev); 255 static void dfx_ctl_set_multicast_list(struct net_device *dev);
255 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 256 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
256 static int dfx_ctl_update_cam(DFX_board_t *bp); 257 static int dfx_ctl_update_cam(DFX_board_t *bp);
257 static int dfx_ctl_update_filters(DFX_board_t *bp); 258 static int dfx_ctl_update_filters(DFX_board_t *bp);
258 259
259 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 260 static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
260 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 261 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
261 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 262 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
262 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 263 static int dfx_hw_adap_state_rd(DFX_board_t *bp);
263 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 264 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
264 265
265 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 266 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
266 static void dfx_rcv_queue_process(DFX_board_t *bp); 267 static void dfx_rcv_queue_process(DFX_board_t *bp);
267 static void dfx_rcv_flush(DFX_board_t *bp); 268 static void dfx_rcv_flush(DFX_board_t *bp);
268 269
269 static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev); 270 static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
270 static int dfx_xmt_done(DFX_board_t *bp); 271 static int dfx_xmt_done(DFX_board_t *bp);
271 static void dfx_xmt_flush(DFX_board_t *bp); 272 static void dfx_xmt_flush(DFX_board_t *bp);
272 273
273 /* Define module-wide (static) variables */ 274 /* Define module-wide (static) variables */
274 275
275 static struct net_device *root_dfx_eisa_dev; 276 static struct net_device *root_dfx_eisa_dev;
276 277
277 278
278 /* 279 /*
279 * ======================= 280 * =======================
280 * = dfx_port_write_byte = 281 * = dfx_port_write_byte =
281 * = dfx_port_read_byte = 282 * = dfx_port_read_byte =
282 * = dfx_port_write_long = 283 * = dfx_port_write_long =
283 * = dfx_port_read_long = 284 * = dfx_port_read_long =
284 * ======================= 285 * =======================
285 * 286 *
286 * Overview: 287 * Overview:
287 * Routines for reading and writing values from/to adapter 288 * Routines for reading and writing values from/to adapter
288 * 289 *
289 * Returns: 290 * Returns:
290 * None 291 * None
291 * 292 *
292 * Arguments: 293 * Arguments:
293 * bp - pointer to board information 294 * bp - pointer to board information
294 * offset - register offset from base I/O address 295 * offset - register offset from base I/O address
295 * data - for dfx_port_write_byte and dfx_port_write_long, this 296 * data - for dfx_port_write_byte and dfx_port_write_long, this
296 * is a value to write. 297 * is a value to write.
297 * for dfx_port_read_byte and dfx_port_read_byte, this 298 * for dfx_port_read_byte and dfx_port_read_byte, this
298 * is a pointer to store the read value. 299 * is a pointer to store the read value.
299 * 300 *
300 * Functional Description: 301 * Functional Description:
301 * These routines perform the correct operation to read or write 302 * These routines perform the correct operation to read or write
302 * the adapter register. 303 * the adapter register.
303 * 304 *
304 * EISA port block base addresses are based on the slot number in which the 305 * EISA port block base addresses are based on the slot number in which the
305 * controller is installed. For example, if the EISA controller is installed 306 * controller is installed. For example, if the EISA controller is installed
306 * in slot 4, the port block base address is 0x4000. If the controller is 307 * in slot 4, the port block base address is 0x4000. If the controller is
307 * installed in slot 2, the port block base address is 0x2000, and so on. 308 * installed in slot 2, the port block base address is 0x2000, and so on.
308 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 309 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
309 * registers using the register offsets defined in DEFXX.H. 310 * registers using the register offsets defined in DEFXX.H.
310 * 311 *
311 * PCI port block base addresses are assigned by the PCI BIOS or system 312 * PCI port block base addresses are assigned by the PCI BIOS or system
312 * firmware. There is one 128 byte port block which can be accessed. It 313 * firmware. There is one 128 byte port block which can be accessed. It
313 * allows for I/O mapping of both PDQ and PFI registers using the register 314 * allows for I/O mapping of both PDQ and PFI registers using the register
314 * offsets defined in DEFXX.H. 315 * offsets defined in DEFXX.H.
315 * 316 *
316 * Return Codes: 317 * Return Codes:
317 * None 318 * None
318 * 319 *
319 * Assumptions: 320 * Assumptions:
320 * bp->base_addr is a valid base I/O address for this adapter. 321 * bp->base_addr is a valid base I/O address for this adapter.
321 * offset is a valid register offset for this adapter. 322 * offset is a valid register offset for this adapter.
322 * 323 *
323 * Side Effects: 324 * Side Effects:
324 * Rather than produce macros for these functions, these routines 325 * Rather than produce macros for these functions, these routines
325 * are defined using "inline" to ensure that the compiler will 326 * are defined using "inline" to ensure that the compiler will
326 * generate inline code and not waste a procedure call and return. 327 * generate inline code and not waste a procedure call and return.
327 * This provides all the benefits of macros, but with the 328 * This provides all the benefits of macros, but with the
328 * advantage of strict data type checking. 329 * advantage of strict data type checking.
329 */ 330 */
330 331
331 static inline void dfx_port_write_byte( 332 static inline void dfx_port_write_byte(
332 DFX_board_t *bp, 333 DFX_board_t *bp,
333 int offset, 334 int offset,
334 u8 data 335 u8 data
335 ) 336 )
336 337
337 { 338 {
338 u16 port = bp->base_addr + offset; 339 u16 port = bp->base_addr + offset;
339 340
340 outb(data, port); 341 outb(data, port);
341 } 342 }
342 343
343 static inline void dfx_port_read_byte( 344 static inline void dfx_port_read_byte(
344 DFX_board_t *bp, 345 DFX_board_t *bp,
345 int offset, 346 int offset,
346 u8 *data 347 u8 *data
347 ) 348 )
348 349
349 { 350 {
350 u16 port = bp->base_addr + offset; 351 u16 port = bp->base_addr + offset;
351 352
352 *data = inb(port); 353 *data = inb(port);
353 } 354 }
354 355
355 static inline void dfx_port_write_long( 356 static inline void dfx_port_write_long(
356 DFX_board_t *bp, 357 DFX_board_t *bp,
357 int offset, 358 int offset,
358 u32 data 359 u32 data
359 ) 360 )
360 361
361 { 362 {
362 u16 port = bp->base_addr + offset; 363 u16 port = bp->base_addr + offset;
363 364
364 outl(data, port); 365 outl(data, port);
365 } 366 }
366 367
367 static inline void dfx_port_read_long( 368 static inline void dfx_port_read_long(
368 DFX_board_t *bp, 369 DFX_board_t *bp,
369 int offset, 370 int offset,
370 u32 *data 371 u32 *data
371 ) 372 )
372 373
373 { 374 {
374 u16 port = bp->base_addr + offset; 375 u16 port = bp->base_addr + offset;
375 376
376 *data = inl(port); 377 *data = inl(port);
377 } 378 }
378 379
379 380
380 /* 381 /*
381 * ============= 382 * =============
382 * = dfx_init_one_pci_or_eisa = 383 * = dfx_init_one_pci_or_eisa =
383 * ============= 384 * =============
384 * 385 *
385 * Overview: 386 * Overview:
386 * Initializes a supported FDDI EISA or PCI controller 387 * Initializes a supported FDDI EISA or PCI controller
387 * 388 *
388 * Returns: 389 * Returns:
389 * Condition code 390 * Condition code
390 * 391 *
391 * Arguments: 392 * Arguments:
392 * pdev - pointer to pci device information (NULL for EISA) 393 * pdev - pointer to pci device information (NULL for EISA)
393 * ioaddr - pointer to port (NULL for PCI) 394 * ioaddr - pointer to port (NULL for PCI)
394 * 395 *
395 * Functional Description: 396 * Functional Description:
396 * 397 *
397 * Return Codes: 398 * Return Codes:
398 * 0 - This device (fddi0, fddi1, etc) configured successfully 399 * 0 - This device (fddi0, fddi1, etc) configured successfully
399 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 400 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
400 * 401 *
401 * Assumptions: 402 * Assumptions:
402 * It compiles so it should work :-( (PCI cards do :-) 403 * It compiles so it should work :-( (PCI cards do :-)
403 * 404 *
404 * Side Effects: 405 * Side Effects:
405 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 406 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
406 * initialized and the board resources are read and stored in 407 * initialized and the board resources are read and stored in
407 * the device structure. 408 * the device structure.
408 */ 409 */
409 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr) 410 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr)
410 { 411 {
411 static int version_disp; 412 static int version_disp;
412 char *print_name = DRV_NAME; 413 char *print_name = DRV_NAME;
413 struct net_device *dev; 414 struct net_device *dev;
414 DFX_board_t *bp; /* board pointer */ 415 DFX_board_t *bp; /* board pointer */
415 int alloc_size; /* total buffer size used */ 416 int alloc_size; /* total buffer size used */
416 int err; 417 int err;
417 418
418 if (!version_disp) { /* display version info if adapter is found */ 419 if (!version_disp) { /* display version info if adapter is found */
419 version_disp = 1; /* set display flag to TRUE so that */ 420 version_disp = 1; /* set display flag to TRUE so that */
420 printk(version); /* we only display this string ONCE */ 421 printk(version); /* we only display this string ONCE */
421 } 422 }
422 423
423 if (pdev != NULL) 424 if (pdev != NULL)
424 print_name = pci_name(pdev); 425 print_name = pci_name(pdev);
425 426
426 dev = alloc_fddidev(sizeof(*bp)); 427 dev = alloc_fddidev(sizeof(*bp));
427 if (!dev) { 428 if (!dev) {
428 printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n", 429 printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n",
429 print_name); 430 print_name);
430 return -ENOMEM; 431 return -ENOMEM;
431 } 432 }
432 433
433 /* Enable PCI device. */ 434 /* Enable PCI device. */
434 if (pdev != NULL) { 435 if (pdev != NULL) {
435 err = pci_enable_device (pdev); 436 err = pci_enable_device (pdev);
436 if (err) goto err_out; 437 if (err) goto err_out;
437 ioaddr = pci_resource_start (pdev, 1); 438 ioaddr = pci_resource_start (pdev, 1);
438 } 439 }
439 440
440 SET_MODULE_OWNER(dev); 441 SET_MODULE_OWNER(dev);
441 if (pdev != NULL) 442 if (pdev != NULL)
442 SET_NETDEV_DEV(dev, &pdev->dev); 443 SET_NETDEV_DEV(dev, &pdev->dev);
443 444
444 bp = dev->priv; 445 bp = dev->priv;
445 446
446 if (!request_region(ioaddr, 447 if (!request_region(ioaddr,
447 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, 448 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN,
448 print_name)) { 449 print_name)) {
449 printk(KERN_ERR "%s: Cannot reserve I/O resource " 450 printk(KERN_ERR "%s: Cannot reserve I/O resource "
450 "0x%x @ 0x%lx, aborting\n", print_name, 451 "0x%x @ 0x%lx, aborting\n", print_name,
451 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, ioaddr); 452 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, ioaddr);
452 err = -EBUSY; 453 err = -EBUSY;
453 goto err_out; 454 goto err_out;
454 } 455 }
455 456
456 /* Initialize new device structure */ 457 /* Initialize new device structure */
457 458
458 dev->base_addr = ioaddr; /* save port (I/O) base address */ 459 dev->base_addr = ioaddr; /* save port (I/O) base address */
459 460
460 dev->get_stats = dfx_ctl_get_stats; 461 dev->get_stats = dfx_ctl_get_stats;
461 dev->open = dfx_open; 462 dev->open = dfx_open;
462 dev->stop = dfx_close; 463 dev->stop = dfx_close;
463 dev->hard_start_xmit = dfx_xmt_queue_pkt; 464 dev->hard_start_xmit = dfx_xmt_queue_pkt;
464 dev->set_multicast_list = dfx_ctl_set_multicast_list; 465 dev->set_multicast_list = dfx_ctl_set_multicast_list;
465 dev->set_mac_address = dfx_ctl_set_mac_address; 466 dev->set_mac_address = dfx_ctl_set_mac_address;
466 467
467 if (pdev == NULL) { 468 if (pdev == NULL) {
468 /* EISA board */ 469 /* EISA board */
469 bp->bus_type = DFX_BUS_TYPE_EISA; 470 bp->bus_type = DFX_BUS_TYPE_EISA;
470 bp->next = root_dfx_eisa_dev; 471 bp->next = root_dfx_eisa_dev;
471 root_dfx_eisa_dev = dev; 472 root_dfx_eisa_dev = dev;
472 } else { 473 } else {
473 /* PCI board */ 474 /* PCI board */
474 bp->bus_type = DFX_BUS_TYPE_PCI; 475 bp->bus_type = DFX_BUS_TYPE_PCI;
475 bp->pci_dev = pdev; 476 bp->pci_dev = pdev;
476 pci_set_drvdata (pdev, dev); 477 pci_set_drvdata (pdev, dev);
477 pci_set_master (pdev); 478 pci_set_master (pdev);
478 } 479 }
479 480
480 if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) { 481 if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) {
481 err = -ENODEV; 482 err = -ENODEV;
482 goto err_out_region; 483 goto err_out_region;
483 } 484 }
484 485
485 err = register_netdev(dev); 486 err = register_netdev(dev);
486 if (err) 487 if (err)
487 goto err_out_kfree; 488 goto err_out_kfree;
488 489
489 printk("%s: registered as %s\n", print_name, dev->name); 490 printk("%s: registered as %s\n", print_name, dev->name);
490 return 0; 491 return 0;
491 492
492 err_out_kfree: 493 err_out_kfree:
493 alloc_size = sizeof(PI_DESCR_BLOCK) + 494 alloc_size = sizeof(PI_DESCR_BLOCK) +
494 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 495 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
495 #ifndef DYNAMIC_BUFFERS 496 #ifndef DYNAMIC_BUFFERS
496 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 497 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
497 #endif 498 #endif
498 sizeof(PI_CONSUMER_BLOCK) + 499 sizeof(PI_CONSUMER_BLOCK) +
499 (PI_ALIGN_K_DESC_BLK - 1); 500 (PI_ALIGN_K_DESC_BLK - 1);
500 if (bp->kmalloced) 501 if (bp->kmalloced)
501 pci_free_consistent(pdev, alloc_size, 502 pci_free_consistent(pdev, alloc_size,
502 bp->kmalloced, bp->kmalloced_dma); 503 bp->kmalloced, bp->kmalloced_dma);
503 err_out_region: 504 err_out_region:
504 release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN); 505 release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN);
505 err_out: 506 err_out:
506 free_netdev(dev); 507 free_netdev(dev);
507 return err; 508 return err;
508 } 509 }
509 510
510 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 511 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
511 { 512 {
512 return dfx_init_one_pci_or_eisa(pdev, 0); 513 return dfx_init_one_pci_or_eisa(pdev, 0);
513 } 514 }
514 515
515 static int __init dfx_eisa_init(void) 516 static int __init dfx_eisa_init(void)
516 { 517 {
517 int rc = -ENODEV; 518 int rc = -ENODEV;
518 int i; /* used in for loops */ 519 int i; /* used in for loops */
519 u16 port; /* temporary I/O (port) address */ 520 u16 port; /* temporary I/O (port) address */
520 u32 slot_id; /* EISA hardware (slot) ID read from adapter */ 521 u32 slot_id; /* EISA hardware (slot) ID read from adapter */
521 522
522 DBG_printk("In dfx_eisa_init...\n"); 523 DBG_printk("In dfx_eisa_init...\n");
523 524
524 /* Scan for FDDI EISA controllers */ 525 /* Scan for FDDI EISA controllers */
525 526
526 for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */ 527 for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */
527 { 528 {
528 port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */ 529 port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */
529 slot_id = inl(port); /* read EISA HW (slot) ID */ 530 slot_id = inl(port); /* read EISA HW (slot) ID */
530 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID) 531 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID)
531 { 532 {
532 port = (i << 12); /* recalc base addr */ 533 port = (i << 12); /* recalc base addr */
533 534
534 if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0; 535 if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0;
535 } 536 }
536 } 537 }
537 return rc; 538 return rc;
538 } 539 }
539 540
540 /* 541 /*
541 * ================ 542 * ================
542 * = dfx_bus_init = 543 * = dfx_bus_init =
543 * ================ 544 * ================
544 * 545 *
545 * Overview: 546 * Overview:
546 * Initializes EISA and PCI controller bus-specific logic. 547 * Initializes EISA and PCI controller bus-specific logic.
547 * 548 *
548 * Returns: 549 * Returns:
549 * None 550 * None
550 * 551 *
551 * Arguments: 552 * Arguments:
552 * dev - pointer to device information 553 * dev - pointer to device information
553 * 554 *
554 * Functional Description: 555 * Functional Description:
555 * Determine and save adapter IRQ in device table, 556 * Determine and save adapter IRQ in device table,
556 * then perform bus-specific logic initialization. 557 * then perform bus-specific logic initialization.
557 * 558 *
558 * Return Codes: 559 * Return Codes:
559 * None 560 * None
560 * 561 *
561 * Assumptions: 562 * Assumptions:
562 * dev->base_addr has already been set with the proper 563 * dev->base_addr has already been set with the proper
563 * base I/O address for this device. 564 * base I/O address for this device.
564 * 565 *
565 * Side Effects: 566 * Side Effects:
566 * Interrupts are enabled at the adapter bus-specific logic. 567 * Interrupts are enabled at the adapter bus-specific logic.
567 * Note: Interrupts at the DMA engine (PDQ chip) are not 568 * Note: Interrupts at the DMA engine (PDQ chip) are not
568 * enabled yet. 569 * enabled yet.
569 */ 570 */
570 571
571 static void __devinit dfx_bus_init(struct net_device *dev) 572 static void __devinit dfx_bus_init(struct net_device *dev)
572 { 573 {
573 DFX_board_t *bp = dev->priv; 574 DFX_board_t *bp = dev->priv;
574 u8 val; /* used for I/O read/writes */ 575 u8 val; /* used for I/O read/writes */
575 576
576 DBG_printk("In dfx_bus_init...\n"); 577 DBG_printk("In dfx_bus_init...\n");
577 578
578 /* 579 /*
579 * Initialize base I/O address field in bp structure 580 * Initialize base I/O address field in bp structure
580 * 581 *
581 * Note: bp->base_addr is the same as dev->base_addr. 582 * Note: bp->base_addr is the same as dev->base_addr.
582 * It's useful because often we'll need to read 583 * It's useful because often we'll need to read
583 * or write registers where we already have the 584 * or write registers where we already have the
584 * bp pointer instead of the dev pointer. Having 585 * bp pointer instead of the dev pointer. Having
585 * the base address in the bp structure will 586 * the base address in the bp structure will
586 * save a pointer dereference. 587 * save a pointer dereference.
587 * 588 *
588 * IMPORTANT!! This field must be defined before 589 * IMPORTANT!! This field must be defined before
589 * any of the dfx_port_* inline functions are 590 * any of the dfx_port_* inline functions are
590 * called. 591 * called.
591 */ 592 */
592 593
593 bp->base_addr = dev->base_addr; 594 bp->base_addr = dev->base_addr;
594 595
595 /* And a pointer back to the net_device struct */ 596 /* And a pointer back to the net_device struct */
596 bp->dev = dev; 597 bp->dev = dev;
597 598
598 /* Initialize adapter based on bus type */ 599 /* Initialize adapter based on bus type */
599 600
600 if (bp->bus_type == DFX_BUS_TYPE_EISA) 601 if (bp->bus_type == DFX_BUS_TYPE_EISA)
601 { 602 {
602 /* Get the interrupt level from the ESIC chip */ 603 /* Get the interrupt level from the ESIC chip */
603 604
604 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val); 605 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
605 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ) 606 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ)
606 { 607 {
607 case PI_CONFIG_STAT_0_IRQ_K_9: 608 case PI_CONFIG_STAT_0_IRQ_K_9:
608 dev->irq = 9; 609 dev->irq = 9;
609 break; 610 break;
610 611
611 case PI_CONFIG_STAT_0_IRQ_K_10: 612 case PI_CONFIG_STAT_0_IRQ_K_10:
612 dev->irq = 10; 613 dev->irq = 10;
613 break; 614 break;
614 615
615 case PI_CONFIG_STAT_0_IRQ_K_11: 616 case PI_CONFIG_STAT_0_IRQ_K_11:
616 dev->irq = 11; 617 dev->irq = 11;
617 break; 618 break;
618 619
619 case PI_CONFIG_STAT_0_IRQ_K_15: 620 case PI_CONFIG_STAT_0_IRQ_K_15:
620 dev->irq = 15; 621 dev->irq = 15;
621 break; 622 break;
622 } 623 }
623 624
624 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */ 625 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
625 626
626 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB); 627 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB);
627 628
628 /* Set the I/O decode range of the board */ 629 /* Set the I/O decode range of the board */
629 630
630 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT); 631 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT);
631 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val); 632 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val);
632 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val); 633 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val);
633 634
634 /* Enable access to rest of module (including PDQ and packet memory) */ 635 /* Enable access to rest of module (including PDQ and packet memory) */
635 636
636 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB); 637 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB);
637 638
638 /* 639 /*
639 * Map PDQ registers into I/O space. This is done by clearing a bit 640 * Map PDQ registers into I/O space. This is done by clearing a bit
640 * in Burst Holdoff register. 641 * in Burst Holdoff register.
641 */ 642 */
642 643
643 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val); 644 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val);
644 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP)); 645 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP));
645 646
646 /* Enable interrupts at EISA bus interface chip (ESIC) */ 647 /* Enable interrupts at EISA bus interface chip (ESIC) */
647 648
648 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val); 649 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
649 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB)); 650 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB));
650 } 651 }
651 else 652 else
652 { 653 {
653 struct pci_dev *pdev = bp->pci_dev; 654 struct pci_dev *pdev = bp->pci_dev;
654 655
655 /* Get the interrupt level from the PCI Configuration Table */ 656 /* Get the interrupt level from the PCI Configuration Table */
656 657
657 dev->irq = pdev->irq; 658 dev->irq = pdev->irq;
658 659
659 /* Check Latency Timer and set if less than minimal */ 660 /* Check Latency Timer and set if less than minimal */
660 661
661 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 662 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
662 if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */ 663 if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */
663 { 664 {
664 val = PFI_K_LAT_TIMER_DEF; 665 val = PFI_K_LAT_TIMER_DEF;
665 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 666 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
666 } 667 }
667 668
668 /* Enable interrupts at PCI bus interface chip (PFI) */ 669 /* Enable interrupts at PCI bus interface chip (PFI) */
669 670
670 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB)); 671 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB));
671 } 672 }
672 } 673 }
673 674
674 675
675 /* 676 /*
676 * ======================== 677 * ========================
677 * = dfx_bus_config_check = 678 * = dfx_bus_config_check =
678 * ======================== 679 * ========================
679 * 680 *
680 * Overview: 681 * Overview:
681 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 682 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
682 * are illegal, then this routine will set new defaults. 683 * are illegal, then this routine will set new defaults.
683 * 684 *
684 * Returns: 685 * Returns:
685 * None 686 * None
686 * 687 *
687 * Arguments: 688 * Arguments:
688 * bp - pointer to board information 689 * bp - pointer to board information
689 * 690 *
690 * Functional Description: 691 * Functional Description:
691 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 692 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
692 * PDQ, and all FDDI PCI controllers, all values are legal. 693 * PDQ, and all FDDI PCI controllers, all values are legal.
693 * 694 *
694 * Return Codes: 695 * Return Codes:
695 * None 696 * None
696 * 697 *
697 * Assumptions: 698 * Assumptions:
698 * dfx_adap_init has NOT been called yet so burst size and other items have 699 * dfx_adap_init has NOT been called yet so burst size and other items have
699 * not been set. 700 * not been set.
700 * 701 *
701 * Side Effects: 702 * Side Effects:
702 * None 703 * None
703 */ 704 */
704 705
705 static void __devinit dfx_bus_config_check(DFX_board_t *bp) 706 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
706 { 707 {
707 int status; /* return code from adapter port control call */ 708 int status; /* return code from adapter port control call */
708 u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */ 709 u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */
709 u32 host_data; /* LW data returned from port control call */ 710 u32 host_data; /* LW data returned from port control call */
710 711
711 DBG_printk("In dfx_bus_config_check...\n"); 712 DBG_printk("In dfx_bus_config_check...\n");
712 713
713 /* Configuration check only valid for EISA adapter */ 714 /* Configuration check only valid for EISA adapter */
714 715
715 if (bp->bus_type == DFX_BUS_TYPE_EISA) 716 if (bp->bus_type == DFX_BUS_TYPE_EISA)
716 { 717 {
717 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id); 718 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id);
718 719
719 /* 720 /*
720 * First check if revision 2 EISA controller. Rev. 1 cards used 721 * First check if revision 2 EISA controller. Rev. 1 cards used
721 * PDQ revision B, so no workaround needed in this case. Rev. 3 722 * PDQ revision B, so no workaround needed in this case. Rev. 3
722 * cards used PDQ revision E, so no workaround needed in this 723 * cards used PDQ revision E, so no workaround needed in this
723 * case, either. Only Rev. 2 cards used either Rev. D or E 724 * case, either. Only Rev. 2 cards used either Rev. D or E
724 * chips, so we must verify the chip revision on Rev. 2 cards. 725 * chips, so we must verify the chip revision on Rev. 2 cards.
725 */ 726 */
726 727
727 if (slot_id == DEFEA_PROD_ID_2) 728 if (slot_id == DEFEA_PROD_ID_2)
728 { 729 {
729 /* 730 /*
730 * Revision 2 FDDI EISA controller found, so let's check PDQ 731 * Revision 2 FDDI EISA controller found, so let's check PDQ
731 * revision of adapter. 732 * revision of adapter.
732 */ 733 */
733 734
734 status = dfx_hw_port_ctrl_req(bp, 735 status = dfx_hw_port_ctrl_req(bp,
735 PI_PCTRL_M_SUB_CMD, 736 PI_PCTRL_M_SUB_CMD,
736 PI_SUB_CMD_K_PDQ_REV_GET, 737 PI_SUB_CMD_K_PDQ_REV_GET,
737 0, 738 0,
738 &host_data); 739 &host_data);
739 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 740 if ((status != DFX_K_SUCCESS) || (host_data == 2))
740 { 741 {
741 /* 742 /*
742 * Either we couldn't determine the PDQ revision, or 743 * Either we couldn't determine the PDQ revision, or
743 * we determined that it is at revision D. In either case, 744 * we determined that it is at revision D. In either case,
744 * we need to implement the workaround. 745 * we need to implement the workaround.
745 */ 746 */
746 747
747 /* Ensure that the burst size is set to 8 longwords or less */ 748 /* Ensure that the burst size is set to 8 longwords or less */
748 749
749 switch (bp->burst_size) 750 switch (bp->burst_size)
750 { 751 {
751 case PI_PDATA_B_DMA_BURST_SIZE_32: 752 case PI_PDATA_B_DMA_BURST_SIZE_32:
752 case PI_PDATA_B_DMA_BURST_SIZE_16: 753 case PI_PDATA_B_DMA_BURST_SIZE_16:
753 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 754 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
754 break; 755 break;
755 756
756 default: 757 default:
757 break; 758 break;
758 } 759 }
759 760
760 /* Ensure that full-duplex mode is not enabled */ 761 /* Ensure that full-duplex mode is not enabled */
761 762
762 bp->full_duplex_enb = PI_SNMP_K_FALSE; 763 bp->full_duplex_enb = PI_SNMP_K_FALSE;
763 } 764 }
764 } 765 }
765 } 766 }
766 } 767 }
767 768
768 769
769 /* 770 /*
770 * =================== 771 * ===================
771 * = dfx_driver_init = 772 * = dfx_driver_init =
772 * =================== 773 * ===================
773 * 774 *
774 * Overview: 775 * Overview:
775 * Initializes remaining adapter board structure information 776 * Initializes remaining adapter board structure information
776 * and makes sure adapter is in a safe state prior to dfx_open(). 777 * and makes sure adapter is in a safe state prior to dfx_open().
777 * 778 *
778 * Returns: 779 * Returns:
779 * Condition code 780 * Condition code
780 * 781 *
781 * Arguments: 782 * Arguments:
782 * dev - pointer to device information 783 * dev - pointer to device information
783 * print_name - printable device name 784 * print_name - printable device name
784 * 785 *
785 * Functional Description: 786 * Functional Description:
786 * This function allocates additional resources such as the host memory 787 * This function allocates additional resources such as the host memory
787 * blocks needed by the adapter (eg. descriptor and consumer blocks). 788 * blocks needed by the adapter (eg. descriptor and consumer blocks).
788 * Remaining bus initialization steps are also completed. The adapter 789 * Remaining bus initialization steps are also completed. The adapter
789 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 790 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
790 * must call dfx_open() to open the adapter and bring it on-line. 791 * must call dfx_open() to open the adapter and bring it on-line.
791 * 792 *
792 * Return Codes: 793 * Return Codes:
793 * DFX_K_SUCCESS - initialization succeeded 794 * DFX_K_SUCCESS - initialization succeeded
794 * DFX_K_FAILURE - initialization failed - could not allocate memory 795 * DFX_K_FAILURE - initialization failed - could not allocate memory
795 * or read adapter MAC address 796 * or read adapter MAC address
796 * 797 *
797 * Assumptions: 798 * Assumptions:
798 * Memory allocated from pci_alloc_consistent() call is physically 799 * Memory allocated from pci_alloc_consistent() call is physically
799 * contiguous, locked memory. 800 * contiguous, locked memory.
800 * 801 *
801 * Side Effects: 802 * Side Effects:
802 * Adapter is reset and should be in DMA_UNAVAILABLE state before 803 * Adapter is reset and should be in DMA_UNAVAILABLE state before
803 * returning from this routine. 804 * returning from this routine.
804 */ 805 */
805 806
806 static int __devinit dfx_driver_init(struct net_device *dev, 807 static int __devinit dfx_driver_init(struct net_device *dev,
807 const char *print_name) 808 const char *print_name)
808 { 809 {
809 DFX_board_t *bp = dev->priv; 810 DFX_board_t *bp = dev->priv;
810 int alloc_size; /* total buffer size needed */ 811 int alloc_size; /* total buffer size needed */
811 char *top_v, *curr_v; /* virtual addrs into memory block */ 812 char *top_v, *curr_v; /* virtual addrs into memory block */
812 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 813 dma_addr_t top_p, curr_p; /* physical addrs into memory block */
813 u32 data; /* host data register value */ 814 u32 data; /* host data register value */
814 815
815 DBG_printk("In dfx_driver_init...\n"); 816 DBG_printk("In dfx_driver_init...\n");
816 817
817 /* Initialize bus-specific hardware registers */ 818 /* Initialize bus-specific hardware registers */
818 819
819 dfx_bus_init(dev); 820 dfx_bus_init(dev);
820 821
821 /* 822 /*
822 * Initialize default values for configurable parameters 823 * Initialize default values for configurable parameters
823 * 824 *
824 * Note: All of these parameters are ones that a user may 825 * Note: All of these parameters are ones that a user may
825 * want to customize. It'd be nice to break these 826 * want to customize. It'd be nice to break these
826 * out into Space.c or someplace else that's more 827 * out into Space.c or someplace else that's more
827 * accessible/understandable than this file. 828 * accessible/understandable than this file.
828 */ 829 */
829 830
830 bp->full_duplex_enb = PI_SNMP_K_FALSE; 831 bp->full_duplex_enb = PI_SNMP_K_FALSE;
831 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 832 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
832 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 833 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
833 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 834 bp->rcv_bufs_to_post = RCV_BUFS_DEF;
834 835
835 /* 836 /*
836 * Ensure that HW configuration is OK 837 * Ensure that HW configuration is OK
837 * 838 *
838 * Note: Depending on the hardware revision, we may need to modify 839 * Note: Depending on the hardware revision, we may need to modify
839 * some of the configurable parameters to workaround hardware 840 * some of the configurable parameters to workaround hardware
840 * limitations. We'll perform this configuration check AFTER 841 * limitations. We'll perform this configuration check AFTER
841 * setting the parameters to their default values. 842 * setting the parameters to their default values.
842 */ 843 */
843 844
844 dfx_bus_config_check(bp); 845 dfx_bus_config_check(bp);
845 846
846 /* Disable PDQ interrupts first */ 847 /* Disable PDQ interrupts first */
847 848
848 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 849 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
849 850
850 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 851 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
851 852
852 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 853 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
853 854
854 /* Read the factory MAC address from the adapter then save it */ 855 /* Read the factory MAC address from the adapter then save it */
855 856
856 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 857 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
857 &data) != DFX_K_SUCCESS) { 858 &data) != DFX_K_SUCCESS) {
858 printk("%s: Could not read adapter factory MAC address!\n", 859 printk("%s: Could not read adapter factory MAC address!\n",
859 print_name); 860 print_name);
860 return(DFX_K_FAILURE); 861 return(DFX_K_FAILURE);
861 } 862 }
863 data = cpu_to_le32(data);
862 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); 864 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
863 865
864 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 866 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
865 &data) != DFX_K_SUCCESS) { 867 &data) != DFX_K_SUCCESS) {
866 printk("%s: Could not read adapter factory MAC address!\n", 868 printk("%s: Could not read adapter factory MAC address!\n",
867 print_name); 869 print_name);
868 return(DFX_K_FAILURE); 870 return(DFX_K_FAILURE);
869 } 871 }
872 data = cpu_to_le32(data);
870 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); 873 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
871 874
872 /* 875 /*
873 * Set current address to factory address 876 * Set current address to factory address
874 * 877 *
875 * Note: Node address override support is handled through 878 * Note: Node address override support is handled through
876 * dfx_ctl_set_mac_address. 879 * dfx_ctl_set_mac_address.
877 */ 880 */
878 881
879 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 882 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
880 if (bp->bus_type == DFX_BUS_TYPE_EISA) 883 if (bp->bus_type == DFX_BUS_TYPE_EISA)
881 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, " 884 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, "
882 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", 885 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
883 print_name, dev->base_addr, dev->irq, 886 print_name, dev->base_addr, dev->irq,
884 dev->dev_addr[0], dev->dev_addr[1], 887 dev->dev_addr[0], dev->dev_addr[1],
885 dev->dev_addr[2], dev->dev_addr[3], 888 dev->dev_addr[2], dev->dev_addr[3],
886 dev->dev_addr[4], dev->dev_addr[5]); 889 dev->dev_addr[4], dev->dev_addr[5]);
887 else 890 else
888 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, " 891 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, "
889 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", 892 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
890 print_name, dev->base_addr, dev->irq, 893 print_name, dev->base_addr, dev->irq,
891 dev->dev_addr[0], dev->dev_addr[1], 894 dev->dev_addr[0], dev->dev_addr[1],
892 dev->dev_addr[2], dev->dev_addr[3], 895 dev->dev_addr[2], dev->dev_addr[3],
893 dev->dev_addr[4], dev->dev_addr[5]); 896 dev->dev_addr[4], dev->dev_addr[5]);
894 897
895 /* 898 /*
896 * Get memory for descriptor block, consumer block, and other buffers 899 * Get memory for descriptor block, consumer block, and other buffers
897 * that need to be DMA read or written to by the adapter. 900 * that need to be DMA read or written to by the adapter.
898 */ 901 */
899 902
900 alloc_size = sizeof(PI_DESCR_BLOCK) + 903 alloc_size = sizeof(PI_DESCR_BLOCK) +
901 PI_CMD_REQ_K_SIZE_MAX + 904 PI_CMD_REQ_K_SIZE_MAX +
902 PI_CMD_RSP_K_SIZE_MAX + 905 PI_CMD_RSP_K_SIZE_MAX +
903 #ifndef DYNAMIC_BUFFERS 906 #ifndef DYNAMIC_BUFFERS
904 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 907 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
905 #endif 908 #endif
906 sizeof(PI_CONSUMER_BLOCK) + 909 sizeof(PI_CONSUMER_BLOCK) +
907 (PI_ALIGN_K_DESC_BLK - 1); 910 (PI_ALIGN_K_DESC_BLK - 1);
908 bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size, 911 bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size,
909 &bp->kmalloced_dma); 912 &bp->kmalloced_dma);
910 if (top_v == NULL) { 913 if (top_v == NULL) {
911 printk("%s: Could not allocate memory for host buffers " 914 printk("%s: Could not allocate memory for host buffers "
912 "and structures!\n", print_name); 915 "and structures!\n", print_name);
913 return(DFX_K_FAILURE); 916 return(DFX_K_FAILURE);
914 } 917 }
915 memset(top_v, 0, alloc_size); /* zero out memory before continuing */ 918 memset(top_v, 0, alloc_size); /* zero out memory before continuing */
916 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 919 top_p = bp->kmalloced_dma; /* get physical address of buffer */
917 920
918 /* 921 /*
919 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 922 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
920 * plus the amount of memory needed was allocated. The physical address 923 * plus the amount of memory needed was allocated. The physical address
921 * is now 8K aligned. By carving up the memory in a specific order, 924 * is now 8K aligned. By carving up the memory in a specific order,
922 * we'll guarantee the alignment requirements for all other structures. 925 * we'll guarantee the alignment requirements for all other structures.
923 * 926 *
924 * Note: If the assumptions change regarding the non-paged, non-cached, 927 * Note: If the assumptions change regarding the non-paged, non-cached,
925 * physically contiguous nature of the memory block or the address 928 * physically contiguous nature of the memory block or the address
926 * alignments, then we'll need to implement a different algorithm 929 * alignments, then we'll need to implement a different algorithm
927 * for allocating the needed memory. 930 * for allocating the needed memory.
928 */ 931 */
929 932
930 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 933 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
931 curr_v = top_v + (curr_p - top_p); 934 curr_v = top_v + (curr_p - top_p);
932 935
933 /* Reserve space for descriptor block */ 936 /* Reserve space for descriptor block */
934 937
935 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 938 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
936 bp->descr_block_phys = curr_p; 939 bp->descr_block_phys = curr_p;
937 curr_v += sizeof(PI_DESCR_BLOCK); 940 curr_v += sizeof(PI_DESCR_BLOCK);
938 curr_p += sizeof(PI_DESCR_BLOCK); 941 curr_p += sizeof(PI_DESCR_BLOCK);
939 942
940 /* Reserve space for command request buffer */ 943 /* Reserve space for command request buffer */
941 944
942 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 945 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
943 bp->cmd_req_phys = curr_p; 946 bp->cmd_req_phys = curr_p;
944 curr_v += PI_CMD_REQ_K_SIZE_MAX; 947 curr_v += PI_CMD_REQ_K_SIZE_MAX;
945 curr_p += PI_CMD_REQ_K_SIZE_MAX; 948 curr_p += PI_CMD_REQ_K_SIZE_MAX;
946 949
947 /* Reserve space for command response buffer */ 950 /* Reserve space for command response buffer */
948 951
949 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 952 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
950 bp->cmd_rsp_phys = curr_p; 953 bp->cmd_rsp_phys = curr_p;
951 curr_v += PI_CMD_RSP_K_SIZE_MAX; 954 curr_v += PI_CMD_RSP_K_SIZE_MAX;
952 curr_p += PI_CMD_RSP_K_SIZE_MAX; 955 curr_p += PI_CMD_RSP_K_SIZE_MAX;
953 956
954 /* Reserve space for the LLC host receive queue buffers */ 957 /* Reserve space for the LLC host receive queue buffers */
955 958
956 bp->rcv_block_virt = curr_v; 959 bp->rcv_block_virt = curr_v;
957 bp->rcv_block_phys = curr_p; 960 bp->rcv_block_phys = curr_p;
958 961
959 #ifndef DYNAMIC_BUFFERS 962 #ifndef DYNAMIC_BUFFERS
960 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 963 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
961 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 964 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
962 #endif 965 #endif
963 966
964 /* Reserve space for the consumer block */ 967 /* Reserve space for the consumer block */
965 968
966 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 969 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
967 bp->cons_block_phys = curr_p; 970 bp->cons_block_phys = curr_p;
968 971
969 /* Display virtual and physical addresses if debug driver */ 972 /* Display virtual and physical addresses if debug driver */
970 973
971 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 974 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
972 print_name, 975 print_name,
973 (long)bp->descr_block_virt, bp->descr_block_phys); 976 (long)bp->descr_block_virt, bp->descr_block_phys);
974 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 977 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
975 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 978 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
976 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 979 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
977 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 980 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
978 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 981 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
979 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 982 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
980 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 983 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
981 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 984 print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
982 985
983 return(DFX_K_SUCCESS); 986 return(DFX_K_SUCCESS);
984 } 987 }
985 988
986 989
987 /* 990 /*
988 * ================= 991 * =================
989 * = dfx_adap_init = 992 * = dfx_adap_init =
990 * ================= 993 * =================
991 * 994 *
992 * Overview: 995 * Overview:
993 * Brings the adapter to the link avail/link unavailable state. 996 * Brings the adapter to the link avail/link unavailable state.
994 * 997 *
995 * Returns: 998 * Returns:
996 * Condition code 999 * Condition code
997 * 1000 *
998 * Arguments: 1001 * Arguments:
999 * bp - pointer to board information 1002 * bp - pointer to board information
1000 * get_buffers - non-zero if buffers to be allocated 1003 * get_buffers - non-zero if buffers to be allocated
1001 * 1004 *
1002 * Functional Description: 1005 * Functional Description:
1003 * Issues the low-level firmware/hardware calls necessary to bring 1006 * Issues the low-level firmware/hardware calls necessary to bring
1004 * the adapter up, or to properly reset and restore adapter during 1007 * the adapter up, or to properly reset and restore adapter during
1005 * run-time. 1008 * run-time.
1006 * 1009 *
1007 * Return Codes: 1010 * Return Codes:
1008 * DFX_K_SUCCESS - Adapter brought up successfully 1011 * DFX_K_SUCCESS - Adapter brought up successfully
1009 * DFX_K_FAILURE - Adapter initialization failed 1012 * DFX_K_FAILURE - Adapter initialization failed
1010 * 1013 *
1011 * Assumptions: 1014 * Assumptions:
1012 * bp->reset_type should be set to a valid reset type value before 1015 * bp->reset_type should be set to a valid reset type value before
1013 * calling this routine. 1016 * calling this routine.
1014 * 1017 *
1015 * Side Effects: 1018 * Side Effects:
1016 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1019 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1017 * upon a successful return of this routine. 1020 * upon a successful return of this routine.
1018 */ 1021 */
1019 1022
1020 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1023 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1021 { 1024 {
1022 DBG_printk("In dfx_adap_init...\n"); 1025 DBG_printk("In dfx_adap_init...\n");
1023 1026
1024 /* Disable PDQ interrupts first */ 1027 /* Disable PDQ interrupts first */
1025 1028
1026 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1029 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1027 1030
1028 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1031 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1029 1032
1030 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1033 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1031 { 1034 {
1032 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1035 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1033 return(DFX_K_FAILURE); 1036 return(DFX_K_FAILURE);
1034 } 1037 }
1035 1038
1036 /* 1039 /*
1037 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1040 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1038 * so we'll acknowledge all Type 0 interrupts now before continuing. 1041 * so we'll acknowledge all Type 0 interrupts now before continuing.
1039 */ 1042 */
1040 1043
1041 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1044 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1042 1045
1043 /* 1046 /*
1044 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1047 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1045 * 1048 *
1046 * Note: We only need to clear host copies of these registers. The PDQ reset 1049 * Note: We only need to clear host copies of these registers. The PDQ reset
1047 * takes care of the on-board register values. 1050 * takes care of the on-board register values.
1048 */ 1051 */
1049 1052
1050 bp->cmd_req_reg.lword = 0; 1053 bp->cmd_req_reg.lword = 0;
1051 bp->cmd_rsp_reg.lword = 0; 1054 bp->cmd_rsp_reg.lword = 0;
1052 bp->rcv_xmt_reg.lword = 0; 1055 bp->rcv_xmt_reg.lword = 0;
1053 1056
1054 /* Clear consumer block before going to DMA_AVAILABLE state */ 1057 /* Clear consumer block before going to DMA_AVAILABLE state */
1055 1058
1056 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1059 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1057 1060
1058 /* Initialize the DMA Burst Size */ 1061 /* Initialize the DMA Burst Size */
1059 1062
1060 if (dfx_hw_port_ctrl_req(bp, 1063 if (dfx_hw_port_ctrl_req(bp,
1061 PI_PCTRL_M_SUB_CMD, 1064 PI_PCTRL_M_SUB_CMD,
1062 PI_SUB_CMD_K_BURST_SIZE_SET, 1065 PI_SUB_CMD_K_BURST_SIZE_SET,
1063 bp->burst_size, 1066 bp->burst_size,
1064 NULL) != DFX_K_SUCCESS) 1067 NULL) != DFX_K_SUCCESS)
1065 { 1068 {
1066 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1069 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1067 return(DFX_K_FAILURE); 1070 return(DFX_K_FAILURE);
1068 } 1071 }
1069 1072
1070 /* 1073 /*
1071 * Set base address of Consumer Block 1074 * Set base address of Consumer Block
1072 * 1075 *
1073 * Assumption: 32-bit physical address of consumer block is 64 byte 1076 * Assumption: 32-bit physical address of consumer block is 64 byte
1074 * aligned. That is, bits 0-5 of the address must be zero. 1077 * aligned. That is, bits 0-5 of the address must be zero.
1075 */ 1078 */
1076 1079
1077 if (dfx_hw_port_ctrl_req(bp, 1080 if (dfx_hw_port_ctrl_req(bp,
1078 PI_PCTRL_M_CONS_BLOCK, 1081 PI_PCTRL_M_CONS_BLOCK,
1079 bp->cons_block_phys, 1082 bp->cons_block_phys,
1080 0, 1083 0,
1081 NULL) != DFX_K_SUCCESS) 1084 NULL) != DFX_K_SUCCESS)
1082 { 1085 {
1083 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1086 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1084 return(DFX_K_FAILURE); 1087 return(DFX_K_FAILURE);
1085 } 1088 }
1086 1089
1087 /* 1090 /*
1088 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state 1091 * Set the base address of Descriptor Block and bring adapter
1092 * to DMA_AVAILABLE state.
1089 * 1093 *
1090 * Note: We also set the literal and data swapping requirements in this 1094 * Note: We also set the literal and data swapping requirements
1091 * command. Since this driver presently runs on Intel platforms 1095 * in this command.
1092 * which are Little Endian, we'll tell the adapter to byte swap
1093 * data only. This code will need to change when we support
1094 * Big Endian systems (eg. PowerPC).
1095 * 1096 *
1096 * Assumption: 32-bit physical address of descriptor block is 8Kbyte 1097 * Assumption: 32-bit physical address of descriptor block
1097 * aligned. That is, bits 0-12 of the address must be zero. 1098 * is 8Kbyte aligned.
1098 */ 1099 */
1099 1100 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
1100 if (dfx_hw_port_ctrl_req(bp, 1101 (u32)(bp->descr_block_phys |
1101 PI_PCTRL_M_INIT, 1102 PI_PDATA_A_INIT_M_BSWAP_INIT),
1102 (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA), 1103 0, NULL) != DFX_K_SUCCESS) {
1103 0, 1104 printk("%s: Could not set descriptor block address!\n",
1104 NULL) != DFX_K_SUCCESS) 1105 bp->dev->name);
1105 { 1106 return DFX_K_FAILURE;
1106 printk("%s: Could not set descriptor block address!\n", bp->dev->name); 1107 }
1107 return(DFX_K_FAILURE);
1108 }
1109 1108
1110 /* Set transmit flush timeout value */ 1109 /* Set transmit flush timeout value */
1111 1110
1112 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1111 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1113 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1112 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
1114 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1113 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
1115 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1114 bp->cmd_req_virt->char_set.item[0].item_index = 0;
1116 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1115 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
1117 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1116 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1118 { 1117 {
1119 printk("%s: DMA command request failed!\n", bp->dev->name); 1118 printk("%s: DMA command request failed!\n", bp->dev->name);
1120 return(DFX_K_FAILURE); 1119 return(DFX_K_FAILURE);
1121 } 1120 }
1122 1121
1123 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1122 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1124 1123
1125 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1124 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1126 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1125 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
1127 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1126 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
1128 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1127 bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
1129 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1128 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
1130 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1129 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
1131 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1130 bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
1132 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1131 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
1133 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1132 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1134 { 1133 {
1135 printk("%s: DMA command request failed!\n", bp->dev->name); 1134 printk("%s: DMA command request failed!\n", bp->dev->name);
1136 return(DFX_K_FAILURE); 1135 return(DFX_K_FAILURE);
1137 } 1136 }
1138 1137
1139 /* Initialize adapter CAM */ 1138 /* Initialize adapter CAM */
1140 1139
1141 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1140 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1142 { 1141 {
1143 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1142 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1144 return(DFX_K_FAILURE); 1143 return(DFX_K_FAILURE);
1145 } 1144 }
1146 1145
1147 /* Initialize adapter filters */ 1146 /* Initialize adapter filters */
1148 1147
1149 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1148 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1150 { 1149 {
1151 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1150 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1152 return(DFX_K_FAILURE); 1151 return(DFX_K_FAILURE);
1153 } 1152 }
1154 1153
1155 /* 1154 /*
1156 * Remove any existing dynamic buffers (i.e. if the adapter is being 1155 * Remove any existing dynamic buffers (i.e. if the adapter is being
1157 * reinitialized) 1156 * reinitialized)
1158 */ 1157 */
1159 1158
1160 if (get_buffers) 1159 if (get_buffers)
1161 dfx_rcv_flush(bp); 1160 dfx_rcv_flush(bp);
1162 1161
1163 /* Initialize receive descriptor block and produce buffers */ 1162 /* Initialize receive descriptor block and produce buffers */
1164 1163
1165 if (dfx_rcv_init(bp, get_buffers)) 1164 if (dfx_rcv_init(bp, get_buffers))
1166 { 1165 {
1167 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1166 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1168 if (get_buffers) 1167 if (get_buffers)
1169 dfx_rcv_flush(bp); 1168 dfx_rcv_flush(bp);
1170 return(DFX_K_FAILURE); 1169 return(DFX_K_FAILURE);
1171 } 1170 }
1172 1171
1173 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1172 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1174 1173
1175 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1174 bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1176 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1175 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1177 { 1176 {
1178 printk("%s: Start command failed\n", bp->dev->name); 1177 printk("%s: Start command failed\n", bp->dev->name);
1179 if (get_buffers) 1178 if (get_buffers)
1180 dfx_rcv_flush(bp); 1179 dfx_rcv_flush(bp);
1181 return(DFX_K_FAILURE); 1180 return(DFX_K_FAILURE);
1182 } 1181 }
1183 1182
1184 /* Initialization succeeded, reenable PDQ interrupts */ 1183 /* Initialization succeeded, reenable PDQ interrupts */
1185 1184
1186 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1185 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1187 return(DFX_K_SUCCESS); 1186 return(DFX_K_SUCCESS);
1188 } 1187 }
1189 1188
1190 1189
1191 /* 1190 /*
1192 * ============ 1191 * ============
1193 * = dfx_open = 1192 * = dfx_open =
1194 * ============ 1193 * ============
1195 * 1194 *
1196 * Overview: 1195 * Overview:
1197 * Opens the adapter 1196 * Opens the adapter
1198 * 1197 *
1199 * Returns: 1198 * Returns:
1200 * Condition code 1199 * Condition code
1201 * 1200 *
1202 * Arguments: 1201 * Arguments:
1203 * dev - pointer to device information 1202 * dev - pointer to device information
1204 * 1203 *
1205 * Functional Description: 1204 * Functional Description:
1206 * This function brings the adapter to an operational state. 1205 * This function brings the adapter to an operational state.
1207 * 1206 *
1208 * Return Codes: 1207 * Return Codes:
1209 * 0 - Adapter was successfully opened 1208 * 0 - Adapter was successfully opened
1210 * -EAGAIN - Could not register IRQ or adapter initialization failed 1209 * -EAGAIN - Could not register IRQ or adapter initialization failed
1211 * 1210 *
1212 * Assumptions: 1211 * Assumptions:
1213 * This routine should only be called for a device that was 1212 * This routine should only be called for a device that was
1214 * initialized successfully. 1213 * initialized successfully.
1215 * 1214 *
1216 * Side Effects: 1215 * Side Effects:
1217 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1216 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1218 * if the open is successful. 1217 * if the open is successful.
1219 */ 1218 */
1220 1219
1221 static int dfx_open(struct net_device *dev) 1220 static int dfx_open(struct net_device *dev)
1222 { 1221 {
1223 int ret; 1222 int ret;
1224 DFX_board_t *bp = dev->priv; 1223 DFX_board_t *bp = dev->priv;
1225 1224
1226 DBG_printk("In dfx_open...\n"); 1225 DBG_printk("In dfx_open...\n");
1227 1226
1228 /* Register IRQ - support shared interrupts by passing device ptr */ 1227 /* Register IRQ - support shared interrupts by passing device ptr */
1229 1228
1230 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, dev); 1229 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, dev);
1231 if (ret) { 1230 if (ret) {
1232 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1231 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1233 return ret; 1232 return ret;
1234 } 1233 }
1235 1234
1236 /* 1235 /*
1237 * Set current address to factory MAC address 1236 * Set current address to factory MAC address
1238 * 1237 *
1239 * Note: We've already done this step in dfx_driver_init. 1238 * Note: We've already done this step in dfx_driver_init.
1240 * However, it's possible that a user has set a node 1239 * However, it's possible that a user has set a node
1241 * address override, then closed and reopened the 1240 * address override, then closed and reopened the
1242 * adapter. Unless we reset the device address field 1241 * adapter. Unless we reset the device address field
1243 * now, we'll continue to use the existing modified 1242 * now, we'll continue to use the existing modified
1244 * address. 1243 * address.
1245 */ 1244 */
1246 1245
1247 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1246 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1248 1247
1249 /* Clear local unicast/multicast address tables and counts */ 1248 /* Clear local unicast/multicast address tables and counts */
1250 1249
1251 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1250 memset(bp->uc_table, 0, sizeof(bp->uc_table));
1252 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1251 memset(bp->mc_table, 0, sizeof(bp->mc_table));
1253 bp->uc_count = 0; 1252 bp->uc_count = 0;
1254 bp->mc_count = 0; 1253 bp->mc_count = 0;
1255 1254
1256 /* Disable promiscuous filter settings */ 1255 /* Disable promiscuous filter settings */
1257 1256
1258 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1257 bp->ind_group_prom = PI_FSTATE_K_BLOCK;
1259 bp->group_prom = PI_FSTATE_K_BLOCK; 1258 bp->group_prom = PI_FSTATE_K_BLOCK;
1260 1259
1261 spin_lock_init(&bp->lock); 1260 spin_lock_init(&bp->lock);
1262 1261
1263 /* Reset and initialize adapter */ 1262 /* Reset and initialize adapter */
1264 1263
1265 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1264 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
1266 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1265 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1267 { 1266 {
1268 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1267 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1269 free_irq(dev->irq, dev); 1268 free_irq(dev->irq, dev);
1270 return -EAGAIN; 1269 return -EAGAIN;
1271 } 1270 }
1272 1271
1273 /* Set device structure info */ 1272 /* Set device structure info */
1274 netif_start_queue(dev); 1273 netif_start_queue(dev);
1275 return(0); 1274 return(0);
1276 } 1275 }
1277 1276
1278 1277
1279 /* 1278 /*
1280 * ============= 1279 * =============
1281 * = dfx_close = 1280 * = dfx_close =
1282 * ============= 1281 * =============
1283 * 1282 *
1284 * Overview: 1283 * Overview:
1285 * Closes the device/module. 1284 * Closes the device/module.
1286 * 1285 *
1287 * Returns: 1286 * Returns:
1288 * Condition code 1287 * Condition code
1289 * 1288 *
1290 * Arguments: 1289 * Arguments:
1291 * dev - pointer to device information 1290 * dev - pointer to device information
1292 * 1291 *
1293 * Functional Description: 1292 * Functional Description:
1294 * This routine closes the adapter and brings it to a safe state. 1293 * This routine closes the adapter and brings it to a safe state.
1295 * The interrupt service routine is deregistered with the OS. 1294 * The interrupt service routine is deregistered with the OS.
1296 * The adapter can be opened again with another call to dfx_open(). 1295 * The adapter can be opened again with another call to dfx_open().
1297 * 1296 *
1298 * Return Codes: 1297 * Return Codes:
1299 * Always return 0. 1298 * Always return 0.
1300 * 1299 *
1301 * Assumptions: 1300 * Assumptions:
1302 * No further requests for this adapter are made after this routine is 1301 * No further requests for this adapter are made after this routine is
1303 * called. dfx_open() can be called to reset and reinitialize the 1302 * called. dfx_open() can be called to reset and reinitialize the
1304 * adapter. 1303 * adapter.
1305 * 1304 *
1306 * Side Effects: 1305 * Side Effects:
1307 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1306 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1308 * routine. 1307 * routine.
1309 */ 1308 */
1310 1309
1311 static int dfx_close(struct net_device *dev) 1310 static int dfx_close(struct net_device *dev)
1312 { 1311 {
1313 DFX_board_t *bp = dev->priv; 1312 DFX_board_t *bp = dev->priv;
1314 1313
1315 DBG_printk("In dfx_close...\n"); 1314 DBG_printk("In dfx_close...\n");
1316 1315
1317 /* Disable PDQ interrupts first */ 1316 /* Disable PDQ interrupts first */
1318 1317
1319 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1318 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1320 1319
1321 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1320 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1322 1321
1323 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1322 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1324 1323
1325 /* 1324 /*
1326 * Flush any pending transmit buffers 1325 * Flush any pending transmit buffers
1327 * 1326 *
1328 * Note: It's important that we flush the transmit buffers 1327 * Note: It's important that we flush the transmit buffers
1329 * BEFORE we clear our copy of the Type 2 register. 1328 * BEFORE we clear our copy of the Type 2 register.
1330 * Otherwise, we'll have no idea how many buffers 1329 * Otherwise, we'll have no idea how many buffers
1331 * we need to free. 1330 * we need to free.
1332 */ 1331 */
1333 1332
1334 dfx_xmt_flush(bp); 1333 dfx_xmt_flush(bp);
1335 1334
1336 /* 1335 /*
1337 * Clear Type 1 and Type 2 registers after adapter reset 1336 * Clear Type 1 and Type 2 registers after adapter reset
1338 * 1337 *
1339 * Note: Even though we're closing the adapter, it's 1338 * Note: Even though we're closing the adapter, it's
1340 * possible that an interrupt will occur after 1339 * possible that an interrupt will occur after
1341 * dfx_close is called. Without some assurance to 1340 * dfx_close is called. Without some assurance to
1342 * the contrary we want to make sure that we don't 1341 * the contrary we want to make sure that we don't
1343 * process receive and transmit LLC frames and update 1342 * process receive and transmit LLC frames and update
1344 * the Type 2 register with bad information. 1343 * the Type 2 register with bad information.
1345 */ 1344 */
1346 1345
1347 bp->cmd_req_reg.lword = 0; 1346 bp->cmd_req_reg.lword = 0;
1348 bp->cmd_rsp_reg.lword = 0; 1347 bp->cmd_rsp_reg.lword = 0;
1349 bp->rcv_xmt_reg.lword = 0; 1348 bp->rcv_xmt_reg.lword = 0;
1350 1349
1351 /* Clear consumer block for the same reason given above */ 1350 /* Clear consumer block for the same reason given above */
1352 1351
1353 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1352 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1354 1353
1355 /* Release all dynamically allocate skb in the receive ring. */ 1354 /* Release all dynamically allocate skb in the receive ring. */
1356 1355
1357 dfx_rcv_flush(bp); 1356 dfx_rcv_flush(bp);
1358 1357
1359 /* Clear device structure flags */ 1358 /* Clear device structure flags */
1360 1359
1361 netif_stop_queue(dev); 1360 netif_stop_queue(dev);
1362 1361
1363 /* Deregister (free) IRQ */ 1362 /* Deregister (free) IRQ */
1364 1363
1365 free_irq(dev->irq, dev); 1364 free_irq(dev->irq, dev);
1366 1365
1367 return(0); 1366 return(0);
1368 } 1367 }
1369 1368
1370 1369
1371 /* 1370 /*
1372 * ====================== 1371 * ======================
1373 * = dfx_int_pr_halt_id = 1372 * = dfx_int_pr_halt_id =
1374 * ====================== 1373 * ======================
1375 * 1374 *
1376 * Overview: 1375 * Overview:
1377 * Displays halt id's in string form. 1376 * Displays halt id's in string form.
1378 * 1377 *
1379 * Returns: 1378 * Returns:
1380 * None 1379 * None
1381 * 1380 *
1382 * Arguments: 1381 * Arguments:
1383 * bp - pointer to board information 1382 * bp - pointer to board information
1384 * 1383 *
1385 * Functional Description: 1384 * Functional Description:
1386 * Determine current halt id and display appropriate string. 1385 * Determine current halt id and display appropriate string.
1387 * 1386 *
1388 * Return Codes: 1387 * Return Codes:
1389 * None 1388 * None
1390 * 1389 *
1391 * Assumptions: 1390 * Assumptions:
1392 * None 1391 * None
1393 * 1392 *
1394 * Side Effects: 1393 * Side Effects:
1395 * None 1394 * None
1396 */ 1395 */
1397 1396
1398 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1397 static void dfx_int_pr_halt_id(DFX_board_t *bp)
1399 { 1398 {
1400 PI_UINT32 port_status; /* PDQ port status register value */ 1399 PI_UINT32 port_status; /* PDQ port status register value */
1401 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1400 PI_UINT32 halt_id; /* PDQ port status halt ID */
1402 1401
1403 /* Read the latest port status */ 1402 /* Read the latest port status */
1404 1403
1405 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1404 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1406 1405
1407 /* Display halt state transition information */ 1406 /* Display halt state transition information */
1408 1407
1409 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1408 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1410 switch (halt_id) 1409 switch (halt_id)
1411 { 1410 {
1412 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1411 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1413 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1412 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1414 break; 1413 break;
1415 1414
1416 case PI_HALT_ID_K_PARITY_ERROR: 1415 case PI_HALT_ID_K_PARITY_ERROR:
1417 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1416 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1418 break; 1417 break;
1419 1418
1420 case PI_HALT_ID_K_HOST_DIR_HALT: 1419 case PI_HALT_ID_K_HOST_DIR_HALT:
1421 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1420 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1422 break; 1421 break;
1423 1422
1424 case PI_HALT_ID_K_SW_FAULT: 1423 case PI_HALT_ID_K_SW_FAULT:
1425 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1424 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1426 break; 1425 break;
1427 1426
1428 case PI_HALT_ID_K_HW_FAULT: 1427 case PI_HALT_ID_K_HW_FAULT:
1429 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1428 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1430 break; 1429 break;
1431 1430
1432 case PI_HALT_ID_K_PC_TRACE: 1431 case PI_HALT_ID_K_PC_TRACE:
1433 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1432 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1434 break; 1433 break;
1435 1434
1436 case PI_HALT_ID_K_DMA_ERROR: 1435 case PI_HALT_ID_K_DMA_ERROR:
1437 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1436 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1438 break; 1437 break;
1439 1438
1440 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1439 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1441 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1440 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1442 break; 1441 break;
1443 1442
1444 case PI_HALT_ID_K_BUS_EXCEPTION: 1443 case PI_HALT_ID_K_BUS_EXCEPTION:
1445 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1444 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1446 break; 1445 break;
1447 1446
1448 default: 1447 default:
1449 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1448 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1450 break; 1449 break;
1451 } 1450 }
1452 } 1451 }
1453 1452
1454 1453
1455 /* 1454 /*
1456 * ========================== 1455 * ==========================
1457 * = dfx_int_type_0_process = 1456 * = dfx_int_type_0_process =
1458 * ========================== 1457 * ==========================
1459 * 1458 *
1460 * Overview: 1459 * Overview:
1461 * Processes Type 0 interrupts. 1460 * Processes Type 0 interrupts.
1462 * 1461 *
1463 * Returns: 1462 * Returns:
1464 * None 1463 * None
1465 * 1464 *
1466 * Arguments: 1465 * Arguments:
1467 * bp - pointer to board information 1466 * bp - pointer to board information
1468 * 1467 *
1469 * Functional Description: 1468 * Functional Description:
1470 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1469 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1471 * is a serious fault on the adapter, then an error message is displayed 1470 * is a serious fault on the adapter, then an error message is displayed
1472 * and the adapter is reset. 1471 * and the adapter is reset.
1473 * 1472 *
1474 * One tricky potential timing window is the rapid succession of "link avail" 1473 * One tricky potential timing window is the rapid succession of "link avail"
1475 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1474 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1476 * interrupt must be done before reading the state from the Port Status 1475 * interrupt must be done before reading the state from the Port Status
1477 * register. This is true because a state change could occur after reading 1476 * register. This is true because a state change could occur after reading
1478 * the data, but before acknowledging the interrupt. If this state change 1477 * the data, but before acknowledging the interrupt. If this state change
1479 * does happen, it would be lost because the driver is using the old state, 1478 * does happen, it would be lost because the driver is using the old state,
1480 * and it will never know about the new state because it subsequently 1479 * and it will never know about the new state because it subsequently
1481 * acknowledges the state change interrupt. 1480 * acknowledges the state change interrupt.
1482 * 1481 *
1483 * INCORRECT CORRECT 1482 * INCORRECT CORRECT
1484 * read type 0 int reasons read type 0 int reasons 1483 * read type 0 int reasons read type 0 int reasons
1485 * read adapter state ack type 0 interrupts 1484 * read adapter state ack type 0 interrupts
1486 * ack type 0 interrupts read adapter state 1485 * ack type 0 interrupts read adapter state
1487 * ... process interrupt ... ... process interrupt ... 1486 * ... process interrupt ... ... process interrupt ...
1488 * 1487 *
1489 * Return Codes: 1488 * Return Codes:
1490 * None 1489 * None
1491 * 1490 *
1492 * Assumptions: 1491 * Assumptions:
1493 * None 1492 * None
1494 * 1493 *
1495 * Side Effects: 1494 * Side Effects:
1496 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1495 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1497 * or if the port status indicates that the adapter is halted. The driver 1496 * or if the port status indicates that the adapter is halted. The driver
1498 * is responsible for reinitializing the adapter with the current CAM 1497 * is responsible for reinitializing the adapter with the current CAM
1499 * contents and adapter filter settings. 1498 * contents and adapter filter settings.
1500 */ 1499 */
1501 1500
1502 static void dfx_int_type_0_process(DFX_board_t *bp) 1501 static void dfx_int_type_0_process(DFX_board_t *bp)
1503 1502
1504 { 1503 {
1505 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1504 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
1506 PI_UINT32 state; /* current adap state (from port status) */ 1505 PI_UINT32 state; /* current adap state (from port status) */
1507 1506
1508 /* 1507 /*
1509 * Read host interrupt Type 0 register to determine which Type 0 1508 * Read host interrupt Type 0 register to determine which Type 0
1510 * interrupts are pending. Immediately write it back out to clear 1509 * interrupts are pending. Immediately write it back out to clear
1511 * those interrupts. 1510 * those interrupts.
1512 */ 1511 */
1513 1512
1514 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1513 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1515 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1514 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1516 1515
1517 /* Check for Type 0 error interrupts */ 1516 /* Check for Type 0 error interrupts */
1518 1517
1519 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1518 if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1520 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1519 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1521 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1520 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1522 { 1521 {
1523 /* Check for Non-Existent Memory error */ 1522 /* Check for Non-Existent Memory error */
1524 1523
1525 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1524 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1526 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1525 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1527 1526
1528 /* Check for Packet Memory Parity error */ 1527 /* Check for Packet Memory Parity error */
1529 1528
1530 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1529 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1531 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1530 printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1532 1531
1533 /* Check for Host Bus Parity error */ 1532 /* Check for Host Bus Parity error */
1534 1533
1535 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1534 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1536 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1535 printk("%s: Host Bus Parity Error\n", bp->dev->name);
1537 1536
1538 /* Reset adapter and bring it back on-line */ 1537 /* Reset adapter and bring it back on-line */
1539 1538
1540 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1539 bp->link_available = PI_K_FALSE; /* link is no longer available */
1541 bp->reset_type = 0; /* rerun on-board diagnostics */ 1540 bp->reset_type = 0; /* rerun on-board diagnostics */
1542 printk("%s: Resetting adapter...\n", bp->dev->name); 1541 printk("%s: Resetting adapter...\n", bp->dev->name);
1543 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1542 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1544 { 1543 {
1545 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1544 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1546 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1545 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1547 return; 1546 return;
1548 } 1547 }
1549 printk("%s: Adapter reset successful!\n", bp->dev->name); 1548 printk("%s: Adapter reset successful!\n", bp->dev->name);
1550 return; 1549 return;
1551 } 1550 }
1552 1551
1553 /* Check for transmit flush interrupt */ 1552 /* Check for transmit flush interrupt */
1554 1553
1555 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1554 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1556 { 1555 {
1557 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1556 /* Flush any pending xmt's and acknowledge the flush interrupt */
1558 1557
1559 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1558 bp->link_available = PI_K_FALSE; /* link is no longer available */
1560 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1559 dfx_xmt_flush(bp); /* flush any outstanding packets */
1561 (void) dfx_hw_port_ctrl_req(bp, 1560 (void) dfx_hw_port_ctrl_req(bp,
1562 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1561 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1563 0, 1562 0,
1564 0, 1563 0,
1565 NULL); 1564 NULL);
1566 } 1565 }
1567 1566
1568 /* Check for adapter state change */ 1567 /* Check for adapter state change */
1569 1568
1570 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1569 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1571 { 1570 {
1572 /* Get latest adapter state */ 1571 /* Get latest adapter state */
1573 1572
1574 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1573 state = dfx_hw_adap_state_rd(bp); /* get adapter state */
1575 if (state == PI_STATE_K_HALTED) 1574 if (state == PI_STATE_K_HALTED)
1576 { 1575 {
1577 /* 1576 /*
1578 * Adapter has transitioned to HALTED state, try to reset 1577 * Adapter has transitioned to HALTED state, try to reset
1579 * adapter to bring it back on-line. If reset fails, 1578 * adapter to bring it back on-line. If reset fails,
1580 * leave the adapter in the broken state. 1579 * leave the adapter in the broken state.
1581 */ 1580 */
1582 1581
1583 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1582 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1584 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1583 dfx_int_pr_halt_id(bp); /* display halt id as string */
1585 1584
1586 /* Reset adapter and bring it back on-line */ 1585 /* Reset adapter and bring it back on-line */
1587 1586
1588 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1587 bp->link_available = PI_K_FALSE; /* link is no longer available */
1589 bp->reset_type = 0; /* rerun on-board diagnostics */ 1588 bp->reset_type = 0; /* rerun on-board diagnostics */
1590 printk("%s: Resetting adapter...\n", bp->dev->name); 1589 printk("%s: Resetting adapter...\n", bp->dev->name);
1591 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1590 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1592 { 1591 {
1593 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1592 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1594 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1593 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1595 return; 1594 return;
1596 } 1595 }
1597 printk("%s: Adapter reset successful!\n", bp->dev->name); 1596 printk("%s: Adapter reset successful!\n", bp->dev->name);
1598 } 1597 }
1599 else if (state == PI_STATE_K_LINK_AVAIL) 1598 else if (state == PI_STATE_K_LINK_AVAIL)
1600 { 1599 {
1601 bp->link_available = PI_K_TRUE; /* set link available flag */ 1600 bp->link_available = PI_K_TRUE; /* set link available flag */
1602 } 1601 }
1603 } 1602 }
1604 } 1603 }
1605 1604
1606 1605
1607 /* 1606 /*
1608 * ================== 1607 * ==================
1609 * = dfx_int_common = 1608 * = dfx_int_common =
1610 * ================== 1609 * ==================
1611 * 1610 *
1612 * Overview: 1611 * Overview:
1613 * Interrupt service routine (ISR) 1612 * Interrupt service routine (ISR)
1614 * 1613 *
1615 * Returns: 1614 * Returns:
1616 * None 1615 * None
1617 * 1616 *
1618 * Arguments: 1617 * Arguments:
1619 * bp - pointer to board information 1618 * bp - pointer to board information
1620 * 1619 *
1621 * Functional Description: 1620 * Functional Description:
1622 * This is the ISR which processes incoming adapter interrupts. 1621 * This is the ISR which processes incoming adapter interrupts.
1623 * 1622 *
1624 * Return Codes: 1623 * Return Codes:
1625 * None 1624 * None
1626 * 1625 *
1627 * Assumptions: 1626 * Assumptions:
1628 * This routine assumes PDQ interrupts have not been disabled. 1627 * This routine assumes PDQ interrupts have not been disabled.
1629 * When interrupts are disabled at the PDQ, the Port Status register 1628 * When interrupts are disabled at the PDQ, the Port Status register
1630 * is automatically cleared. This routine uses the Port Status 1629 * is automatically cleared. This routine uses the Port Status
1631 * register value to determine whether a Type 0 interrupt occurred, 1630 * register value to determine whether a Type 0 interrupt occurred,
1632 * so it's important that adapter interrupts are not normally 1631 * so it's important that adapter interrupts are not normally
1633 * enabled/disabled at the PDQ. 1632 * enabled/disabled at the PDQ.
1634 * 1633 *
1635 * It's vital that this routine is NOT reentered for the 1634 * It's vital that this routine is NOT reentered for the
1636 * same board and that the OS is not in another section of 1635 * same board and that the OS is not in another section of
1637 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1636 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1638 * different thread. 1637 * different thread.
1639 * 1638 *
1640 * Side Effects: 1639 * Side Effects:
1641 * Pending interrupts are serviced. Depending on the type of 1640 * Pending interrupts are serviced. Depending on the type of
1642 * interrupt, acknowledging and clearing the interrupt at the 1641 * interrupt, acknowledging and clearing the interrupt at the
1643 * PDQ involves writing a register to clear the interrupt bit 1642 * PDQ involves writing a register to clear the interrupt bit
1644 * or updating completion indices. 1643 * or updating completion indices.
1645 */ 1644 */
1646 1645
1647 static void dfx_int_common(struct net_device *dev) 1646 static void dfx_int_common(struct net_device *dev)
1648 { 1647 {
1649 DFX_board_t *bp = dev->priv; 1648 DFX_board_t *bp = dev->priv;
1650 PI_UINT32 port_status; /* Port Status register */ 1649 PI_UINT32 port_status; /* Port Status register */
1651 1650
1652 /* Process xmt interrupts - frequent case, so always call this routine */ 1651 /* Process xmt interrupts - frequent case, so always call this routine */
1653 1652
1654 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1653 if(dfx_xmt_done(bp)) /* free consumed xmt packets */
1655 netif_wake_queue(dev); 1654 netif_wake_queue(dev);
1656 1655
1657 /* Process rcv interrupts - frequent case, so always call this routine */ 1656 /* Process rcv interrupts - frequent case, so always call this routine */
1658 1657
1659 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1658 dfx_rcv_queue_process(bp); /* service received LLC frames */
1660 1659
1661 /* 1660 /*
1662 * Transmit and receive producer and completion indices are updated on the 1661 * Transmit and receive producer and completion indices are updated on the
1663 * adapter by writing to the Type 2 Producer register. Since the frequent 1662 * adapter by writing to the Type 2 Producer register. Since the frequent
1664 * case is that we'll be processing either LLC transmit or receive buffers, 1663 * case is that we'll be processing either LLC transmit or receive buffers,
1665 * we'll optimize I/O writes by doing a single register write here. 1664 * we'll optimize I/O writes by doing a single register write here.
1666 */ 1665 */
1667 1666
1668 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1667 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1669 1668
1670 /* Read PDQ Port Status register to find out which interrupts need processing */ 1669 /* Read PDQ Port Status register to find out which interrupts need processing */
1671 1670
1672 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1671 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1673 1672
1674 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1673 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1675 1674
1676 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1675 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1677 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1676 dfx_int_type_0_process(bp); /* process Type 0 interrupts */
1678 } 1677 }
1679 1678
1680 1679
1681 /* 1680 /*
1682 * ================= 1681 * =================
1683 * = dfx_interrupt = 1682 * = dfx_interrupt =
1684 * ================= 1683 * =================
1685 * 1684 *
1686 * Overview: 1685 * Overview:
1687 * Interrupt processing routine 1686 * Interrupt processing routine
1688 * 1687 *
1689 * Returns: 1688 * Returns:
1690 * Whether a valid interrupt was seen. 1689 * Whether a valid interrupt was seen.
1691 * 1690 *
1692 * Arguments: 1691 * Arguments:
1693 * irq - interrupt vector 1692 * irq - interrupt vector
1694 * dev_id - pointer to device information 1693 * dev_id - pointer to device information
1695 * 1694 *
1696 * Functional Description: 1695 * Functional Description:
1697 * This routine calls the interrupt processing routine for this adapter. It 1696 * This routine calls the interrupt processing routine for this adapter. It
1698 * disables and reenables adapter interrupts, as appropriate. We can support 1697 * disables and reenables adapter interrupts, as appropriate. We can support
1699 * shared interrupts since the incoming dev_id pointer provides our device 1698 * shared interrupts since the incoming dev_id pointer provides our device
1700 * structure context. 1699 * structure context.
1701 * 1700 *
1702 * Return Codes: 1701 * Return Codes:
1703 * IRQ_HANDLED - an IRQ was handled. 1702 * IRQ_HANDLED - an IRQ was handled.
1704 * IRQ_NONE - no IRQ was handled. 1703 * IRQ_NONE - no IRQ was handled.
1705 * 1704 *
1706 * Assumptions: 1705 * Assumptions:
1707 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1706 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1708 * on Intel-based systems) is done by the operating system outside this 1707 * on Intel-based systems) is done by the operating system outside this
1709 * routine. 1708 * routine.
1710 * 1709 *
1711 * System interrupts are enabled through this call. 1710 * System interrupts are enabled through this call.
1712 * 1711 *
1713 * Side Effects: 1712 * Side Effects:
1714 * Interrupts are disabled, then reenabled at the adapter. 1713 * Interrupts are disabled, then reenabled at the adapter.
1715 */ 1714 */
1716 1715
1717 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1716 static irqreturn_t dfx_interrupt(int irq, void *dev_id)
1718 { 1717 {
1719 struct net_device *dev = dev_id; 1718 struct net_device *dev = dev_id;
1720 DFX_board_t *bp; /* private board structure pointer */ 1719 DFX_board_t *bp; /* private board structure pointer */
1721 1720
1722 /* Get board pointer only if device structure is valid */ 1721 /* Get board pointer only if device structure is valid */
1723 1722
1724 bp = dev->priv; 1723 bp = dev->priv;
1725 1724
1726 /* See if we're already servicing an interrupt */ 1725 /* See if we're already servicing an interrupt */
1727 1726
1728 /* Service adapter interrupts */ 1727 /* Service adapter interrupts */
1729 1728
1730 if (bp->bus_type == DFX_BUS_TYPE_PCI) { 1729 if (bp->bus_type == DFX_BUS_TYPE_PCI) {
1731 u32 status; 1730 u32 status;
1732 1731
1733 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1732 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
1734 if (!(status & PFI_STATUS_M_PDQ_INT)) 1733 if (!(status & PFI_STATUS_M_PDQ_INT))
1735 return IRQ_NONE; 1734 return IRQ_NONE;
1736 1735
1737 spin_lock(&bp->lock); 1736 spin_lock(&bp->lock);
1738 1737
1739 /* Disable PDQ-PFI interrupts at PFI */ 1738 /* Disable PDQ-PFI interrupts at PFI */
1740 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1739 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1741 PFI_MODE_M_DMA_ENB); 1740 PFI_MODE_M_DMA_ENB);
1742 1741
1743 /* Call interrupt service routine for this adapter */ 1742 /* Call interrupt service routine for this adapter */
1744 dfx_int_common(dev); 1743 dfx_int_common(dev);
1745 1744
1746 /* Clear PDQ interrupt status bit and reenable interrupts */ 1745 /* Clear PDQ interrupt status bit and reenable interrupts */
1747 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1746 dfx_port_write_long(bp, PFI_K_REG_STATUS,
1748 PFI_STATUS_M_PDQ_INT); 1747 PFI_STATUS_M_PDQ_INT);
1749 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1748 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1750 (PFI_MODE_M_PDQ_INT_ENB | 1749 (PFI_MODE_M_PDQ_INT_ENB |
1751 PFI_MODE_M_DMA_ENB)); 1750 PFI_MODE_M_DMA_ENB));
1752 1751
1753 spin_unlock(&bp->lock); 1752 spin_unlock(&bp->lock);
1754 } else { 1753 } else {
1755 u8 status; 1754 u8 status;
1756 1755
1757 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status); 1756 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1758 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1757 if (!(status & PI_CONFIG_STAT_0_M_PEND))
1759 return IRQ_NONE; 1758 return IRQ_NONE;
1760 1759
1761 spin_lock(&bp->lock); 1760 spin_lock(&bp->lock);
1762 1761
1763 /* Disable interrupts at the ESIC */ 1762 /* Disable interrupts at the ESIC */
1764 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1763 status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1765 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status); 1764 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1766 1765
1767 /* Call interrupt service routine for this adapter */ 1766 /* Call interrupt service routine for this adapter */
1768 dfx_int_common(dev); 1767 dfx_int_common(dev);
1769 1768
1770 /* Reenable interrupts at the ESIC */ 1769 /* Reenable interrupts at the ESIC */
1771 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status); 1770 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1772 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1771 status |= PI_CONFIG_STAT_0_M_INT_ENB;
1773 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status); 1772 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1774 1773
1775 spin_unlock(&bp->lock); 1774 spin_unlock(&bp->lock);
1776 } 1775 }
1777 1776
1778 return IRQ_HANDLED; 1777 return IRQ_HANDLED;
1779 } 1778 }
1780 1779
1781 1780
1782 /* 1781 /*
1783 * ===================== 1782 * =====================
1784 * = dfx_ctl_get_stats = 1783 * = dfx_ctl_get_stats =
1785 * ===================== 1784 * =====================
1786 * 1785 *
1787 * Overview: 1786 * Overview:
1788 * Get statistics for FDDI adapter 1787 * Get statistics for FDDI adapter
1789 * 1788 *
1790 * Returns: 1789 * Returns:
1791 * Pointer to FDDI statistics structure 1790 * Pointer to FDDI statistics structure
1792 * 1791 *
1793 * Arguments: 1792 * Arguments:
1794 * dev - pointer to device information 1793 * dev - pointer to device information
1795 * 1794 *
1796 * Functional Description: 1795 * Functional Description:
1797 * Gets current MIB objects from adapter, then 1796 * Gets current MIB objects from adapter, then
1798 * returns FDDI statistics structure as defined 1797 * returns FDDI statistics structure as defined
1799 * in if_fddi.h. 1798 * in if_fddi.h.
1800 * 1799 *
1801 * Note: Since the FDDI statistics structure is 1800 * Note: Since the FDDI statistics structure is
1802 * still new and the device structure doesn't 1801 * still new and the device structure doesn't
1803 * have an FDDI-specific get statistics handler, 1802 * have an FDDI-specific get statistics handler,
1804 * we'll return the FDDI statistics structure as 1803 * we'll return the FDDI statistics structure as
1805 * a pointer to an Ethernet statistics structure. 1804 * a pointer to an Ethernet statistics structure.
1806 * That way, at least the first part of the statistics 1805 * That way, at least the first part of the statistics
1807 * structure can be decoded properly, and it allows 1806 * structure can be decoded properly, and it allows
1808 * "smart" applications to perform a second cast to 1807 * "smart" applications to perform a second cast to
1809 * decode the FDDI-specific statistics. 1808 * decode the FDDI-specific statistics.
1810 * 1809 *
1811 * We'll have to pay attention to this routine as the 1810 * We'll have to pay attention to this routine as the
1812 * device structure becomes more mature and LAN media 1811 * device structure becomes more mature and LAN media
1813 * independent. 1812 * independent.
1814 * 1813 *
1815 * Return Codes: 1814 * Return Codes:
1816 * None 1815 * None
1817 * 1816 *
1818 * Assumptions: 1817 * Assumptions:
1819 * None 1818 * None
1820 * 1819 *
1821 * Side Effects: 1820 * Side Effects:
1822 * None 1821 * None
1823 */ 1822 */
1824 1823
1825 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 1824 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
1826 { 1825 {
1827 DFX_board_t *bp = dev->priv; 1826 DFX_board_t *bp = dev->priv;
1828 1827
1829 /* Fill the bp->stats structure with driver-maintained counters */ 1828 /* Fill the bp->stats structure with driver-maintained counters */
1830 1829
1831 bp->stats.gen.rx_packets = bp->rcv_total_frames; 1830 bp->stats.gen.rx_packets = bp->rcv_total_frames;
1832 bp->stats.gen.tx_packets = bp->xmt_total_frames; 1831 bp->stats.gen.tx_packets = bp->xmt_total_frames;
1833 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 1832 bp->stats.gen.rx_bytes = bp->rcv_total_bytes;
1834 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 1833 bp->stats.gen.tx_bytes = bp->xmt_total_bytes;
1835 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 1834 bp->stats.gen.rx_errors = bp->rcv_crc_errors +
1836 bp->rcv_frame_status_errors + 1835 bp->rcv_frame_status_errors +
1837 bp->rcv_length_errors; 1836 bp->rcv_length_errors;
1838 bp->stats.gen.tx_errors = bp->xmt_length_errors; 1837 bp->stats.gen.tx_errors = bp->xmt_length_errors;
1839 bp->stats.gen.rx_dropped = bp->rcv_discards; 1838 bp->stats.gen.rx_dropped = bp->rcv_discards;
1840 bp->stats.gen.tx_dropped = bp->xmt_discards; 1839 bp->stats.gen.tx_dropped = bp->xmt_discards;
1841 bp->stats.gen.multicast = bp->rcv_multicast_frames; 1840 bp->stats.gen.multicast = bp->rcv_multicast_frames;
1842 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 1841 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */
1843 1842
1844 /* Get FDDI SMT MIB objects */ 1843 /* Get FDDI SMT MIB objects */
1845 1844
1846 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 1845 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
1847 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1846 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1848 return((struct net_device_stats *) &bp->stats); 1847 return((struct net_device_stats *) &bp->stats);
1849 1848
1850 /* Fill the bp->stats structure with the SMT MIB object values */ 1849 /* Fill the bp->stats structure with the SMT MIB object values */
1851 1850
1852 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 1851 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1853 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 1852 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
1854 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 1853 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
1855 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 1854 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
1856 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 1855 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1857 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 1856 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
1858 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 1857 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
1859 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 1858 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
1860 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 1859 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
1861 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 1860 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
1862 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 1861 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
1863 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 1862 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
1864 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 1863 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
1865 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 1864 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
1866 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 1865 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
1867 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 1866 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
1868 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 1867 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
1869 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 1868 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
1870 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 1869 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
1871 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 1870 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1872 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 1871 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
1873 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 1872 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
1874 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 1873 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
1875 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 1874 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1876 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 1875 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1877 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 1876 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
1878 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 1877 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
1879 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 1878 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
1880 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 1879 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
1881 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 1880 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1882 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 1881 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1883 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 1882 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1884 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 1883 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1885 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 1884 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
1886 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 1885 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
1887 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 1886 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
1888 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 1887 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1889 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 1888 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
1890 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 1889 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
1891 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 1890 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
1892 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 1891 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
1893 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 1892 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
1894 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 1893 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
1895 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 1894 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
1896 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 1895 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
1897 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 1896 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
1898 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 1897 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
1899 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 1898 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
1900 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 1899 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
1901 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 1900 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
1902 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 1901 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
1903 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 1902 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
1904 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 1903 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
1905 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 1904 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1906 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 1905 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
1907 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 1906 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
1908 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 1907 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
1909 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 1908 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
1910 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 1909 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1911 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 1910 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1912 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 1911 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
1913 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 1912 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
1914 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 1913 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
1915 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 1914 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
1916 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 1915 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1917 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 1916 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1918 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 1917 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
1919 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 1918 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
1920 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 1919 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
1921 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 1920 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
1922 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 1921 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
1923 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 1922 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
1924 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 1923 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1925 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 1924 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1926 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 1925 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
1927 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 1926 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
1928 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 1927 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
1929 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 1928 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
1930 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 1929 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
1931 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 1930 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
1932 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 1931 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
1933 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 1932 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
1934 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 1933 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
1935 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 1934 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
1936 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 1935 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
1937 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 1936 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
1938 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 1937 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
1939 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 1938 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
1940 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 1939 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
1941 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 1940 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
1942 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 1941 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
1943 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 1942 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
1944 1943
1945 /* Get FDDI counters */ 1944 /* Get FDDI counters */
1946 1945
1947 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 1946 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
1948 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1947 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1949 return((struct net_device_stats *) &bp->stats); 1948 return((struct net_device_stats *) &bp->stats);
1950 1949
1951 /* Fill the bp->stats structure with the FDDI counter values */ 1950 /* Fill the bp->stats structure with the FDDI counter values */
1952 1951
1953 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 1952 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
1954 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 1953 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
1955 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 1954 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
1956 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 1955 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
1957 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 1956 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
1958 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 1957 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
1959 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 1958 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
1960 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 1959 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
1961 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 1960 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
1962 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 1961 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
1963 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 1962 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
1964 1963
1965 return((struct net_device_stats *) &bp->stats); 1964 return((struct net_device_stats *) &bp->stats);
1966 } 1965 }
1967 1966
1968 1967
1969 /* 1968 /*
1970 * ============================== 1969 * ==============================
1971 * = dfx_ctl_set_multicast_list = 1970 * = dfx_ctl_set_multicast_list =
1972 * ============================== 1971 * ==============================
1973 * 1972 *
1974 * Overview: 1973 * Overview:
1975 * Enable/Disable LLC frame promiscuous mode reception 1974 * Enable/Disable LLC frame promiscuous mode reception
1976 * on the adapter and/or update multicast address table. 1975 * on the adapter and/or update multicast address table.
1977 * 1976 *
1978 * Returns: 1977 * Returns:
1979 * None 1978 * None
1980 * 1979 *
1981 * Arguments: 1980 * Arguments:
1982 * dev - pointer to device information 1981 * dev - pointer to device information
1983 * 1982 *
1984 * Functional Description: 1983 * Functional Description:
1985 * This routine follows a fairly simple algorithm for setting the 1984 * This routine follows a fairly simple algorithm for setting the
1986 * adapter filters and CAM: 1985 * adapter filters and CAM:
1987 * 1986 *
1988 * if IFF_PROMISC flag is set 1987 * if IFF_PROMISC flag is set
1989 * enable LLC individual/group promiscuous mode 1988 * enable LLC individual/group promiscuous mode
1990 * else 1989 * else
1991 * disable LLC individual/group promiscuous mode 1990 * disable LLC individual/group promiscuous mode
1992 * if number of incoming multicast addresses > 1991 * if number of incoming multicast addresses >
1993 * (CAM max size - number of unicast addresses in CAM) 1992 * (CAM max size - number of unicast addresses in CAM)
1994 * enable LLC group promiscuous mode 1993 * enable LLC group promiscuous mode
1995 * set driver-maintained multicast address count to zero 1994 * set driver-maintained multicast address count to zero
1996 * else 1995 * else
1997 * disable LLC group promiscuous mode 1996 * disable LLC group promiscuous mode
1998 * set driver-maintained multicast address count to incoming count 1997 * set driver-maintained multicast address count to incoming count
1999 * update adapter CAM 1998 * update adapter CAM
2000 * update adapter filters 1999 * update adapter filters
2001 * 2000 *
2002 * Return Codes: 2001 * Return Codes:
2003 * None 2002 * None
2004 * 2003 *
2005 * Assumptions: 2004 * Assumptions:
2006 * Multicast addresses are presented in canonical (LSB) format. 2005 * Multicast addresses are presented in canonical (LSB) format.
2007 * 2006 *
2008 * Side Effects: 2007 * Side Effects:
2009 * On-board adapter CAM and filters are updated. 2008 * On-board adapter CAM and filters are updated.
2010 */ 2009 */
2011 2010
2012 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2011 static void dfx_ctl_set_multicast_list(struct net_device *dev)
2013 { 2012 {
2014 DFX_board_t *bp = dev->priv; 2013 DFX_board_t *bp = dev->priv;
2015 int i; /* used as index in for loop */ 2014 int i; /* used as index in for loop */
2016 struct dev_mc_list *dmi; /* ptr to multicast addr entry */ 2015 struct dev_mc_list *dmi; /* ptr to multicast addr entry */
2017 2016
2018 /* Enable LLC frame promiscuous mode, if necessary */ 2017 /* Enable LLC frame promiscuous mode, if necessary */
2019 2018
2020 if (dev->flags & IFF_PROMISC) 2019 if (dev->flags & IFF_PROMISC)
2021 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2020 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
2022 2021
2023 /* Else, update multicast address table */ 2022 /* Else, update multicast address table */
2024 2023
2025 else 2024 else
2026 { 2025 {
2027 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2026 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
2028 /* 2027 /*
2029 * Check whether incoming multicast address count exceeds table size 2028 * Check whether incoming multicast address count exceeds table size
2030 * 2029 *
2031 * Note: The adapters utilize an on-board 64 entry CAM for 2030 * Note: The adapters utilize an on-board 64 entry CAM for
2032 * supporting perfect filtering of multicast packets 2031 * supporting perfect filtering of multicast packets
2033 * and bridge functions when adding unicast addresses. 2032 * and bridge functions when adding unicast addresses.
2034 * There is no hash function available. To support 2033 * There is no hash function available. To support
2035 * additional multicast addresses, the all multicast 2034 * additional multicast addresses, the all multicast
2036 * filter (LLC group promiscuous mode) must be enabled. 2035 * filter (LLC group promiscuous mode) must be enabled.
2037 * 2036 *
2038 * The firmware reserves two CAM entries for SMT-related 2037 * The firmware reserves two CAM entries for SMT-related
2039 * multicast addresses, which leaves 62 entries available. 2038 * multicast addresses, which leaves 62 entries available.
2040 * The following code ensures that we're not being asked 2039 * The following code ensures that we're not being asked
2041 * to add more than 62 addresses to the CAM. If we are, 2040 * to add more than 62 addresses to the CAM. If we are,
2042 * the driver will enable the all multicast filter. 2041 * the driver will enable the all multicast filter.
2043 * Should the number of multicast addresses drop below 2042 * Should the number of multicast addresses drop below
2044 * the high water mark, the filter will be disabled and 2043 * the high water mark, the filter will be disabled and
2045 * perfect filtering will be used. 2044 * perfect filtering will be used.
2046 */ 2045 */
2047 2046
2048 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2047 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2049 { 2048 {
2050 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2049 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2051 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2050 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2052 } 2051 }
2053 else 2052 else
2054 { 2053 {
2055 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2054 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
2056 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */ 2055 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
2057 } 2056 }
2058 2057
2059 /* Copy addresses to multicast address table, then update adapter CAM */ 2058 /* Copy addresses to multicast address table, then update adapter CAM */
2060 2059
2061 dmi = dev->mc_list; /* point to first multicast addr */ 2060 dmi = dev->mc_list; /* point to first multicast addr */
2062 for (i=0; i < bp->mc_count; i++) 2061 for (i=0; i < bp->mc_count; i++)
2063 { 2062 {
2064 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN); 2063 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2065 dmi = dmi->next; /* point to next multicast addr */ 2064 dmi = dmi->next; /* point to next multicast addr */
2066 } 2065 }
2067 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2066 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2068 { 2067 {
2069 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2068 DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2070 } 2069 }
2071 else 2070 else
2072 { 2071 {
2073 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2072 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2074 } 2073 }
2075 } 2074 }
2076 2075
2077 /* Update adapter filters */ 2076 /* Update adapter filters */
2078 2077
2079 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2078 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2080 { 2079 {
2081 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2080 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2082 } 2081 }
2083 else 2082 else
2084 { 2083 {
2085 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2084 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2086 } 2085 }
2087 } 2086 }
2088 2087
2089 2088
2090 /* 2089 /*
2091 * =========================== 2090 * ===========================
2092 * = dfx_ctl_set_mac_address = 2091 * = dfx_ctl_set_mac_address =
2093 * =========================== 2092 * ===========================
2094 * 2093 *
2095 * Overview: 2094 * Overview:
2096 * Add node address override (unicast address) to adapter 2095 * Add node address override (unicast address) to adapter
2097 * CAM and update dev_addr field in device table. 2096 * CAM and update dev_addr field in device table.
2098 * 2097 *
2099 * Returns: 2098 * Returns:
2100 * None 2099 * None
2101 * 2100 *
2102 * Arguments: 2101 * Arguments:
2103 * dev - pointer to device information 2102 * dev - pointer to device information
2104 * addr - pointer to sockaddr structure containing unicast address to add 2103 * addr - pointer to sockaddr structure containing unicast address to add
2105 * 2104 *
2106 * Functional Description: 2105 * Functional Description:
2107 * The adapter supports node address overrides by adding one or more 2106 * The adapter supports node address overrides by adding one or more
2108 * unicast addresses to the adapter CAM. This is similar to adding 2107 * unicast addresses to the adapter CAM. This is similar to adding
2109 * multicast addresses. In this routine we'll update the driver and 2108 * multicast addresses. In this routine we'll update the driver and
2110 * device structures with the new address, then update the adapter CAM 2109 * device structures with the new address, then update the adapter CAM
2111 * to ensure that the adapter will copy and strip frames destined and 2110 * to ensure that the adapter will copy and strip frames destined and
2112 * sourced by that address. 2111 * sourced by that address.
2113 * 2112 *
2114 * Return Codes: 2113 * Return Codes:
2115 * Always returns zero. 2114 * Always returns zero.
2116 * 2115 *
2117 * Assumptions: 2116 * Assumptions:
2118 * The address pointed to by addr->sa_data is a valid unicast 2117 * The address pointed to by addr->sa_data is a valid unicast
2119 * address and is presented in canonical (LSB) format. 2118 * address and is presented in canonical (LSB) format.
2120 * 2119 *
2121 * Side Effects: 2120 * Side Effects:
2122 * On-board adapter CAM is updated. On-board adapter filters 2121 * On-board adapter CAM is updated. On-board adapter filters
2123 * may be updated. 2122 * may be updated.
2124 */ 2123 */
2125 2124
2126 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2125 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2127 { 2126 {
2128 DFX_board_t *bp = dev->priv; 2127 DFX_board_t *bp = dev->priv;
2129 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2128 struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2130 2129
2131 /* Copy unicast address to driver-maintained structs and update count */ 2130 /* Copy unicast address to driver-maintained structs and update count */
2132 2131
2133 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2132 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
2134 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2133 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
2135 bp->uc_count = 1; 2134 bp->uc_count = 1;
2136 2135
2137 /* 2136 /*
2138 * Verify we're not exceeding the CAM size by adding unicast address 2137 * Verify we're not exceeding the CAM size by adding unicast address
2139 * 2138 *
2140 * Note: It's possible that before entering this routine we've 2139 * Note: It's possible that before entering this routine we've
2141 * already filled the CAM with 62 multicast addresses. 2140 * already filled the CAM with 62 multicast addresses.
2142 * Since we need to place the node address override into 2141 * Since we need to place the node address override into
2143 * the CAM, we have to check to see that we're not 2142 * the CAM, we have to check to see that we're not
2144 * exceeding the CAM size. If we are, we have to enable 2143 * exceeding the CAM size. If we are, we have to enable
2145 * the LLC group (multicast) promiscuous mode filter as 2144 * the LLC group (multicast) promiscuous mode filter as
2146 * in dfx_ctl_set_multicast_list. 2145 * in dfx_ctl_set_multicast_list.
2147 */ 2146 */
2148 2147
2149 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2148 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2150 { 2149 {
2151 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2150 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2152 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2151 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2153 2152
2154 /* Update adapter filters */ 2153 /* Update adapter filters */
2155 2154
2156 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2155 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2157 { 2156 {
2158 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2157 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2159 } 2158 }
2160 else 2159 else
2161 { 2160 {
2162 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2161 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2163 } 2162 }
2164 } 2163 }
2165 2164
2166 /* Update adapter CAM with new unicast address */ 2165 /* Update adapter CAM with new unicast address */
2167 2166
2168 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2167 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2169 { 2168 {
2170 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2169 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2171 } 2170 }
2172 else 2171 else
2173 { 2172 {
2174 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2173 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2175 } 2174 }
2176 return(0); /* always return zero */ 2175 return(0); /* always return zero */
2177 } 2176 }
2178 2177
2179 2178
2180 /* 2179 /*
2181 * ====================== 2180 * ======================
2182 * = dfx_ctl_update_cam = 2181 * = dfx_ctl_update_cam =
2183 * ====================== 2182 * ======================
2184 * 2183 *
2185 * Overview: 2184 * Overview:
2186 * Procedure to update adapter CAM (Content Addressable Memory) 2185 * Procedure to update adapter CAM (Content Addressable Memory)
2187 * with desired unicast and multicast address entries. 2186 * with desired unicast and multicast address entries.
2188 * 2187 *
2189 * Returns: 2188 * Returns:
2190 * Condition code 2189 * Condition code
2191 * 2190 *
2192 * Arguments: 2191 * Arguments:
2193 * bp - pointer to board information 2192 * bp - pointer to board information
2194 * 2193 *
2195 * Functional Description: 2194 * Functional Description:
2196 * Updates adapter CAM with current contents of board structure 2195 * Updates adapter CAM with current contents of board structure
2197 * unicast and multicast address tables. Since there are only 62 2196 * unicast and multicast address tables. Since there are only 62
2198 * free entries in CAM, this routine ensures that the command 2197 * free entries in CAM, this routine ensures that the command
2199 * request buffer is not overrun. 2198 * request buffer is not overrun.
2200 * 2199 *
2201 * Return Codes: 2200 * Return Codes:
2202 * DFX_K_SUCCESS - Request succeeded 2201 * DFX_K_SUCCESS - Request succeeded
2203 * DFX_K_FAILURE - Request failed 2202 * DFX_K_FAILURE - Request failed
2204 * 2203 *
2205 * Assumptions: 2204 * Assumptions:
2206 * All addresses being added (unicast and multicast) are in canonical 2205 * All addresses being added (unicast and multicast) are in canonical
2207 * order. 2206 * order.
2208 * 2207 *
2209 * Side Effects: 2208 * Side Effects:
2210 * On-board adapter CAM is updated. 2209 * On-board adapter CAM is updated.
2211 */ 2210 */
2212 2211
2213 static int dfx_ctl_update_cam(DFX_board_t *bp) 2212 static int dfx_ctl_update_cam(DFX_board_t *bp)
2214 { 2213 {
2215 int i; /* used as index */ 2214 int i; /* used as index */
2216 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2215 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2217 2216
2218 /* 2217 /*
2219 * Fill in command request information 2218 * Fill in command request information
2220 * 2219 *
2221 * Note: Even though both the unicast and multicast address 2220 * Note: Even though both the unicast and multicast address
2222 * table entries are stored as contiguous 6 byte entries, 2221 * table entries are stored as contiguous 6 byte entries,
2223 * the firmware address filter set command expects each 2222 * the firmware address filter set command expects each
2224 * entry to be two longwords (8 bytes total). We must be 2223 * entry to be two longwords (8 bytes total). We must be
2225 * careful to only copy the six bytes of each unicast and 2224 * careful to only copy the six bytes of each unicast and
2226 * multicast table entry into each command entry. This 2225 * multicast table entry into each command entry. This
2227 * is also why we must first clear the entire command 2226 * is also why we must first clear the entire command
2228 * request buffer. 2227 * request buffer.
2229 */ 2228 */
2230 2229
2231 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2230 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
2232 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2231 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2233 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2232 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2234 2233
2235 /* Now add unicast addresses to command request buffer, if any */ 2234 /* Now add unicast addresses to command request buffer, if any */
2236 2235
2237 for (i=0; i < (int)bp->uc_count; i++) 2236 for (i=0; i < (int)bp->uc_count; i++)
2238 { 2237 {
2239 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2238 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2240 { 2239 {
2241 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2240 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2242 p_addr++; /* point to next command entry */ 2241 p_addr++; /* point to next command entry */
2243 } 2242 }
2244 } 2243 }
2245 2244
2246 /* Now add multicast addresses to command request buffer, if any */ 2245 /* Now add multicast addresses to command request buffer, if any */
2247 2246
2248 for (i=0; i < (int)bp->mc_count; i++) 2247 for (i=0; i < (int)bp->mc_count; i++)
2249 { 2248 {
2250 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2249 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2251 { 2250 {
2252 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2251 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2253 p_addr++; /* point to next command entry */ 2252 p_addr++; /* point to next command entry */
2254 } 2253 }
2255 } 2254 }
2256 2255
2257 /* Issue command to update adapter CAM, then return */ 2256 /* Issue command to update adapter CAM, then return */
2258 2257
2259 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2258 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2260 return(DFX_K_FAILURE); 2259 return(DFX_K_FAILURE);
2261 return(DFX_K_SUCCESS); 2260 return(DFX_K_SUCCESS);
2262 } 2261 }
2263 2262
2264 2263
2265 /* 2264 /*
2266 * ========================== 2265 * ==========================
2267 * = dfx_ctl_update_filters = 2266 * = dfx_ctl_update_filters =
2268 * ========================== 2267 * ==========================
2269 * 2268 *
2270 * Overview: 2269 * Overview:
2271 * Procedure to update adapter filters with desired 2270 * Procedure to update adapter filters with desired
2272 * filter settings. 2271 * filter settings.
2273 * 2272 *
2274 * Returns: 2273 * Returns:
2275 * Condition code 2274 * Condition code
2276 * 2275 *
2277 * Arguments: 2276 * Arguments:
2278 * bp - pointer to board information 2277 * bp - pointer to board information
2279 * 2278 *
2280 * Functional Description: 2279 * Functional Description:
2281 * Enables or disables filter using current filter settings. 2280 * Enables or disables filter using current filter settings.
2282 * 2281 *
2283 * Return Codes: 2282 * Return Codes:
2284 * DFX_K_SUCCESS - Request succeeded. 2283 * DFX_K_SUCCESS - Request succeeded.
2285 * DFX_K_FAILURE - Request failed. 2284 * DFX_K_FAILURE - Request failed.
2286 * 2285 *
2287 * Assumptions: 2286 * Assumptions:
2288 * We must always pass up packets destined to the broadcast 2287 * We must always pass up packets destined to the broadcast
2289 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2288 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2290 * broadcast filter enabled. 2289 * broadcast filter enabled.
2291 * 2290 *
2292 * Side Effects: 2291 * Side Effects:
2293 * On-board adapter filters are updated. 2292 * On-board adapter filters are updated.
2294 */ 2293 */
2295 2294
2296 static int dfx_ctl_update_filters(DFX_board_t *bp) 2295 static int dfx_ctl_update_filters(DFX_board_t *bp)
2297 { 2296 {
2298 int i = 0; /* used as index */ 2297 int i = 0; /* used as index */
2299 2298
2300 /* Fill in command request information */ 2299 /* Fill in command request information */
2301 2300
2302 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2301 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2303 2302
2304 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2303 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2305 2304
2306 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2305 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
2307 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2306 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
2308 2307
2309 /* Initialize LLC Individual/Group Promiscuous filter */ 2308 /* Initialize LLC Individual/Group Promiscuous filter */
2310 2309
2311 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2310 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
2312 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2311 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
2313 2312
2314 /* Initialize LLC Group Promiscuous filter */ 2313 /* Initialize LLC Group Promiscuous filter */
2315 2314
2316 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2315 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
2317 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2316 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
2318 2317
2319 /* Terminate the item code list */ 2318 /* Terminate the item code list */
2320 2319
2321 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2320 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
2322 2321
2323 /* Issue command to update adapter filters, then return */ 2322 /* Issue command to update adapter filters, then return */
2324 2323
2325 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2324 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2326 return(DFX_K_FAILURE); 2325 return(DFX_K_FAILURE);
2327 return(DFX_K_SUCCESS); 2326 return(DFX_K_SUCCESS);
2328 } 2327 }
2329 2328
2330 2329
2331 /* 2330 /*
2332 * ====================== 2331 * ======================
2333 * = dfx_hw_dma_cmd_req = 2332 * = dfx_hw_dma_cmd_req =
2334 * ====================== 2333 * ======================
2335 * 2334 *
2336 * Overview: 2335 * Overview:
2337 * Sends PDQ DMA command to adapter firmware 2336 * Sends PDQ DMA command to adapter firmware
2338 * 2337 *
2339 * Returns: 2338 * Returns:
2340 * Condition code 2339 * Condition code
2341 * 2340 *
2342 * Arguments: 2341 * Arguments:
2343 * bp - pointer to board information 2342 * bp - pointer to board information
2344 * 2343 *
2345 * Functional Description: 2344 * Functional Description:
2346 * The command request and response buffers are posted to the adapter in the manner 2345 * The command request and response buffers are posted to the adapter in the manner
2347 * described in the PDQ Port Specification: 2346 * described in the PDQ Port Specification:
2348 * 2347 *
2349 * 1. Command Response Buffer is posted to adapter. 2348 * 1. Command Response Buffer is posted to adapter.
2350 * 2. Command Request Buffer is posted to adapter. 2349 * 2. Command Request Buffer is posted to adapter.
2351 * 3. Command Request consumer index is polled until it indicates that request 2350 * 3. Command Request consumer index is polled until it indicates that request
2352 * buffer has been DMA'd to adapter. 2351 * buffer has been DMA'd to adapter.
2353 * 4. Command Response consumer index is polled until it indicates that response 2352 * 4. Command Response consumer index is polled until it indicates that response
2354 * buffer has been DMA'd from adapter. 2353 * buffer has been DMA'd from adapter.
2355 * 2354 *
2356 * This ordering ensures that a response buffer is already available for the firmware 2355 * This ordering ensures that a response buffer is already available for the firmware
2357 * to use once it's done processing the request buffer. 2356 * to use once it's done processing the request buffer.
2358 * 2357 *
2359 * Return Codes: 2358 * Return Codes:
2360 * DFX_K_SUCCESS - DMA command succeeded 2359 * DFX_K_SUCCESS - DMA command succeeded
2361 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2360 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2362 * DFX_K_HW_TIMEOUT - DMA command timed out 2361 * DFX_K_HW_TIMEOUT - DMA command timed out
2363 * 2362 *
2364 * Assumptions: 2363 * Assumptions:
2365 * Command request buffer has already been filled with desired DMA command. 2364 * Command request buffer has already been filled with desired DMA command.
2366 * 2365 *
2367 * Side Effects: 2366 * Side Effects:
2368 * None 2367 * None
2369 */ 2368 */
2370 2369
2371 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2370 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2372 { 2371 {
2373 int status; /* adapter status */ 2372 int status; /* adapter status */
2374 int timeout_cnt; /* used in for loops */ 2373 int timeout_cnt; /* used in for loops */
2375 2374
2376 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2375 /* Make sure the adapter is in a state that we can issue the DMA command in */
2377 2376
2378 status = dfx_hw_adap_state_rd(bp); 2377 status = dfx_hw_adap_state_rd(bp);
2379 if ((status == PI_STATE_K_RESET) || 2378 if ((status == PI_STATE_K_RESET) ||
2380 (status == PI_STATE_K_HALTED) || 2379 (status == PI_STATE_K_HALTED) ||
2381 (status == PI_STATE_K_DMA_UNAVAIL) || 2380 (status == PI_STATE_K_DMA_UNAVAIL) ||
2382 (status == PI_STATE_K_UPGRADE)) 2381 (status == PI_STATE_K_UPGRADE))
2383 return(DFX_K_OUTSTATE); 2382 return(DFX_K_OUTSTATE);
2384 2383
2385 /* Put response buffer on the command response queue */ 2384 /* Put response buffer on the command response queue */
2386 2385
2387 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2386 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2388 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2387 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2389 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2388 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2390 2389
2391 /* Bump (and wrap) the producer index and write out to register */ 2390 /* Bump (and wrap) the producer index and write out to register */
2392 2391
2393 bp->cmd_rsp_reg.index.prod += 1; 2392 bp->cmd_rsp_reg.index.prod += 1;
2394 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2393 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2395 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2394 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2396 2395
2397 /* Put request buffer on the command request queue */ 2396 /* Put request buffer on the command request queue */
2398 2397
2399 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2398 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2400 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2399 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2401 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2400 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2402 2401
2403 /* Bump (and wrap) the producer index and write out to register */ 2402 /* Bump (and wrap) the producer index and write out to register */
2404 2403
2405 bp->cmd_req_reg.index.prod += 1; 2404 bp->cmd_req_reg.index.prod += 1;
2406 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2405 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2407 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2406 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2408 2407
2409 /* 2408 /*
2410 * Here we wait for the command request consumer index to be equal 2409 * Here we wait for the command request consumer index to be equal
2411 * to the producer, indicating that the adapter has DMAed the request. 2410 * to the producer, indicating that the adapter has DMAed the request.
2412 */ 2411 */
2413 2412
2414 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2413 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2415 { 2414 {
2416 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2415 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2417 break; 2416 break;
2418 udelay(100); /* wait for 100 microseconds */ 2417 udelay(100); /* wait for 100 microseconds */
2419 } 2418 }
2420 if (timeout_cnt == 0) 2419 if (timeout_cnt == 0)
2421 return(DFX_K_HW_TIMEOUT); 2420 return(DFX_K_HW_TIMEOUT);
2422 2421
2423 /* Bump (and wrap) the completion index and write out to register */ 2422 /* Bump (and wrap) the completion index and write out to register */
2424 2423
2425 bp->cmd_req_reg.index.comp += 1; 2424 bp->cmd_req_reg.index.comp += 1;
2426 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2425 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2427 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2426 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2428 2427
2429 /* 2428 /*
2430 * Here we wait for the command response consumer index to be equal 2429 * Here we wait for the command response consumer index to be equal
2431 * to the producer, indicating that the adapter has DMAed the response. 2430 * to the producer, indicating that the adapter has DMAed the response.
2432 */ 2431 */
2433 2432
2434 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2433 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2435 { 2434 {
2436 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2435 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2437 break; 2436 break;
2438 udelay(100); /* wait for 100 microseconds */ 2437 udelay(100); /* wait for 100 microseconds */
2439 } 2438 }
2440 if (timeout_cnt == 0) 2439 if (timeout_cnt == 0)
2441 return(DFX_K_HW_TIMEOUT); 2440 return(DFX_K_HW_TIMEOUT);
2442 2441
2443 /* Bump (and wrap) the completion index and write out to register */ 2442 /* Bump (and wrap) the completion index and write out to register */
2444 2443
2445 bp->cmd_rsp_reg.index.comp += 1; 2444 bp->cmd_rsp_reg.index.comp += 1;
2446 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2445 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2447 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2446 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2448 return(DFX_K_SUCCESS); 2447 return(DFX_K_SUCCESS);
2449 } 2448 }
2450 2449
2451 2450
2452 /* 2451 /*
2453 * ======================== 2452 * ========================
2454 * = dfx_hw_port_ctrl_req = 2453 * = dfx_hw_port_ctrl_req =
2455 * ======================== 2454 * ========================
2456 * 2455 *
2457 * Overview: 2456 * Overview:
2458 * Sends PDQ port control command to adapter firmware 2457 * Sends PDQ port control command to adapter firmware
2459 * 2458 *
2460 * Returns: 2459 * Returns:
2461 * Host data register value in host_data if ptr is not NULL 2460 * Host data register value in host_data if ptr is not NULL
2462 * 2461 *
2463 * Arguments: 2462 * Arguments:
2464 * bp - pointer to board information 2463 * bp - pointer to board information
2465 * command - port control command 2464 * command - port control command
2466 * data_a - port data A register value 2465 * data_a - port data A register value
2467 * data_b - port data B register value 2466 * data_b - port data B register value
2468 * host_data - ptr to host data register value 2467 * host_data - ptr to host data register value
2469 * 2468 *
2470 * Functional Description: 2469 * Functional Description:
2471 * Send generic port control command to adapter by writing 2470 * Send generic port control command to adapter by writing
2472 * to various PDQ port registers, then polling for completion. 2471 * to various PDQ port registers, then polling for completion.
2473 * 2472 *
2474 * Return Codes: 2473 * Return Codes:
2475 * DFX_K_SUCCESS - port control command succeeded 2474 * DFX_K_SUCCESS - port control command succeeded
2476 * DFX_K_HW_TIMEOUT - port control command timed out 2475 * DFX_K_HW_TIMEOUT - port control command timed out
2477 * 2476 *
2478 * Assumptions: 2477 * Assumptions:
2479 * None 2478 * None
2480 * 2479 *
2481 * Side Effects: 2480 * Side Effects:
2482 * None 2481 * None
2483 */ 2482 */
2484 2483
2485 static int dfx_hw_port_ctrl_req( 2484 static int dfx_hw_port_ctrl_req(
2486 DFX_board_t *bp, 2485 DFX_board_t *bp,
2487 PI_UINT32 command, 2486 PI_UINT32 command,
2488 PI_UINT32 data_a, 2487 PI_UINT32 data_a,
2489 PI_UINT32 data_b, 2488 PI_UINT32 data_b,
2490 PI_UINT32 *host_data 2489 PI_UINT32 *host_data
2491 ) 2490 )
2492 2491
2493 { 2492 {
2494 PI_UINT32 port_cmd; /* Port Control command register value */ 2493 PI_UINT32 port_cmd; /* Port Control command register value */
2495 int timeout_cnt; /* used in for loops */ 2494 int timeout_cnt; /* used in for loops */
2496 2495
2497 /* Set Command Error bit in command longword */ 2496 /* Set Command Error bit in command longword */
2498 2497
2499 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2498 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2500 2499
2501 /* Issue port command to the adapter */ 2500 /* Issue port command to the adapter */
2502 2501
2503 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2502 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2504 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2503 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2505 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2504 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2506 2505
2507 /* Now wait for command to complete */ 2506 /* Now wait for command to complete */
2508 2507
2509 if (command == PI_PCTRL_M_BLAST_FLASH) 2508 if (command == PI_PCTRL_M_BLAST_FLASH)
2510 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2509 timeout_cnt = 600000; /* set command timeout count to 60 seconds */
2511 else 2510 else
2512 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2511 timeout_cnt = 20000; /* set command timeout count to 2 seconds */
2513 2512
2514 for (; timeout_cnt > 0; timeout_cnt--) 2513 for (; timeout_cnt > 0; timeout_cnt--)
2515 { 2514 {
2516 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2515 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2517 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2516 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2518 break; 2517 break;
2519 udelay(100); /* wait for 100 microseconds */ 2518 udelay(100); /* wait for 100 microseconds */
2520 } 2519 }
2521 if (timeout_cnt == 0) 2520 if (timeout_cnt == 0)
2522 return(DFX_K_HW_TIMEOUT); 2521 return(DFX_K_HW_TIMEOUT);
2523 2522
2524 /* 2523 /*
2525 * If the address of host_data is non-zero, assume caller has supplied a 2524 * If the address of host_data is non-zero, assume caller has supplied a
2526 * non NULL pointer, and return the contents of the HOST_DATA register in 2525 * non NULL pointer, and return the contents of the HOST_DATA register in
2527 * it. 2526 * it.
2528 */ 2527 */
2529 2528
2530 if (host_data != NULL) 2529 if (host_data != NULL)
2531 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2530 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2532 return(DFX_K_SUCCESS); 2531 return(DFX_K_SUCCESS);
2533 } 2532 }
2534 2533
2535 2534
2536 /* 2535 /*
2537 * ===================== 2536 * =====================
2538 * = dfx_hw_adap_reset = 2537 * = dfx_hw_adap_reset =
2539 * ===================== 2538 * =====================
2540 * 2539 *
2541 * Overview: 2540 * Overview:
2542 * Resets adapter 2541 * Resets adapter
2543 * 2542 *
2544 * Returns: 2543 * Returns:
2545 * None 2544 * None
2546 * 2545 *
2547 * Arguments: 2546 * Arguments:
2548 * bp - pointer to board information 2547 * bp - pointer to board information
2549 * type - type of reset to perform 2548 * type - type of reset to perform
2550 * 2549 *
2551 * Functional Description: 2550 * Functional Description:
2552 * Issue soft reset to adapter by writing to PDQ Port Reset 2551 * Issue soft reset to adapter by writing to PDQ Port Reset
2553 * register. Use incoming reset type to tell adapter what 2552 * register. Use incoming reset type to tell adapter what
2554 * kind of reset operation to perform. 2553 * kind of reset operation to perform.
2555 * 2554 *
2556 * Return Codes: 2555 * Return Codes:
2557 * None 2556 * None
2558 * 2557 *
2559 * Assumptions: 2558 * Assumptions:
2560 * This routine merely issues a soft reset to the adapter. 2559 * This routine merely issues a soft reset to the adapter.
2561 * It is expected that after this routine returns, the caller 2560 * It is expected that after this routine returns, the caller
2562 * will appropriately poll the Port Status register for the 2561 * will appropriately poll the Port Status register for the
2563 * adapter to enter the proper state. 2562 * adapter to enter the proper state.
2564 * 2563 *
2565 * Side Effects: 2564 * Side Effects:
2566 * Internal adapter registers are cleared. 2565 * Internal adapter registers are cleared.
2567 */ 2566 */
2568 2567
2569 static void dfx_hw_adap_reset( 2568 static void dfx_hw_adap_reset(
2570 DFX_board_t *bp, 2569 DFX_board_t *bp,
2571 PI_UINT32 type 2570 PI_UINT32 type
2572 ) 2571 )
2573 2572
2574 { 2573 {
2575 /* Set Reset type and assert reset */ 2574 /* Set Reset type and assert reset */
2576 2575
2577 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2576 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
2578 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2577 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2579 2578
2580 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2579 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2581 2580
2582 udelay(20); 2581 udelay(20);
2583 2582
2584 /* Deassert reset */ 2583 /* Deassert reset */
2585 2584
2586 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2585 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2587 } 2586 }
2588 2587
2589 2588
2590 /* 2589 /*
2591 * ======================== 2590 * ========================
2592 * = dfx_hw_adap_state_rd = 2591 * = dfx_hw_adap_state_rd =
2593 * ======================== 2592 * ========================
2594 * 2593 *
2595 * Overview: 2594 * Overview:
2596 * Returns current adapter state 2595 * Returns current adapter state
2597 * 2596 *
2598 * Returns: 2597 * Returns:
2599 * Adapter state per PDQ Port Specification 2598 * Adapter state per PDQ Port Specification
2600 * 2599 *
2601 * Arguments: 2600 * Arguments:
2602 * bp - pointer to board information 2601 * bp - pointer to board information
2603 * 2602 *
2604 * Functional Description: 2603 * Functional Description:
2605 * Reads PDQ Port Status register and returns adapter state. 2604 * Reads PDQ Port Status register and returns adapter state.
2606 * 2605 *
2607 * Return Codes: 2606 * Return Codes:
2608 * None 2607 * None
2609 * 2608 *
2610 * Assumptions: 2609 * Assumptions:
2611 * None 2610 * None
2612 * 2611 *
2613 * Side Effects: 2612 * Side Effects:
2614 * None 2613 * None
2615 */ 2614 */
2616 2615
2617 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2616 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2618 { 2617 {
2619 PI_UINT32 port_status; /* Port Status register value */ 2618 PI_UINT32 port_status; /* Port Status register value */
2620 2619
2621 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2620 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2622 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE); 2621 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2623 } 2622 }
2624 2623
2625 2624
2626 /* 2625 /*
2627 * ===================== 2626 * =====================
2628 * = dfx_hw_dma_uninit = 2627 * = dfx_hw_dma_uninit =
2629 * ===================== 2628 * =====================
2630 * 2629 *
2631 * Overview: 2630 * Overview:
2632 * Brings adapter to DMA_UNAVAILABLE state 2631 * Brings adapter to DMA_UNAVAILABLE state
2633 * 2632 *
2634 * Returns: 2633 * Returns:
2635 * Condition code 2634 * Condition code
2636 * 2635 *
2637 * Arguments: 2636 * Arguments:
2638 * bp - pointer to board information 2637 * bp - pointer to board information
2639 * type - type of reset to perform 2638 * type - type of reset to perform
2640 * 2639 *
2641 * Functional Description: 2640 * Functional Description:
2642 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2641 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2643 * 1. Set reset type bit in Port Data A Register then reset adapter. 2642 * 1. Set reset type bit in Port Data A Register then reset adapter.
2644 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2643 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2645 * 2644 *
2646 * Return Codes: 2645 * Return Codes:
2647 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2646 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2648 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2647 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2649 * 2648 *
2650 * Assumptions: 2649 * Assumptions:
2651 * None 2650 * None
2652 * 2651 *
2653 * Side Effects: 2652 * Side Effects:
2654 * Internal adapter registers are cleared. 2653 * Internal adapter registers are cleared.
2655 */ 2654 */
2656 2655
2657 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2656 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2658 { 2657 {
2659 int timeout_cnt; /* used in for loops */ 2658 int timeout_cnt; /* used in for loops */
2660 2659
2661 /* Set reset type bit and reset adapter */ 2660 /* Set reset type bit and reset adapter */
2662 2661
2663 dfx_hw_adap_reset(bp, type); 2662 dfx_hw_adap_reset(bp, type);
2664 2663
2665 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2664 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2666 2665
2667 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2666 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2668 { 2667 {
2669 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2668 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2670 break; 2669 break;
2671 udelay(100); /* wait for 100 microseconds */ 2670 udelay(100); /* wait for 100 microseconds */
2672 } 2671 }
2673 if (timeout_cnt == 0) 2672 if (timeout_cnt == 0)
2674 return(DFX_K_HW_TIMEOUT); 2673 return(DFX_K_HW_TIMEOUT);
2675 return(DFX_K_SUCCESS); 2674 return(DFX_K_SUCCESS);
2676 } 2675 }
2677 2676
2678 /* 2677 /*
2679 * Align an sk_buff to a boundary power of 2 2678 * Align an sk_buff to a boundary power of 2
2680 * 2679 *
2681 */ 2680 */
2682 2681
2683 static void my_skb_align(struct sk_buff *skb, int n) 2682 static void my_skb_align(struct sk_buff *skb, int n)
2684 { 2683 {
2685 unsigned long x = (unsigned long)skb->data; 2684 unsigned long x = (unsigned long)skb->data;
2686 unsigned long v; 2685 unsigned long v;
2687 2686
2688 v = ALIGN(x, n); /* Where we want to be */ 2687 v = ALIGN(x, n); /* Where we want to be */
2689 2688
2690 skb_reserve(skb, v - x); 2689 skb_reserve(skb, v - x);
2691 } 2690 }
2692 2691
2693 2692
2694 /* 2693 /*
2695 * ================ 2694 * ================
2696 * = dfx_rcv_init = 2695 * = dfx_rcv_init =
2697 * ================ 2696 * ================
2698 * 2697 *
2699 * Overview: 2698 * Overview:
2700 * Produces buffers to adapter LLC Host receive descriptor block 2699 * Produces buffers to adapter LLC Host receive descriptor block
2701 * 2700 *
2702 * Returns: 2701 * Returns:
2703 * None 2702 * None
2704 * 2703 *
2705 * Arguments: 2704 * Arguments:
2706 * bp - pointer to board information 2705 * bp - pointer to board information
2707 * get_buffers - non-zero if buffers to be allocated 2706 * get_buffers - non-zero if buffers to be allocated
2708 * 2707 *
2709 * Functional Description: 2708 * Functional Description:
2710 * This routine can be called during dfx_adap_init() or during an adapter 2709 * This routine can be called during dfx_adap_init() or during an adapter
2711 * reset. It initializes the descriptor block and produces all allocated 2710 * reset. It initializes the descriptor block and produces all allocated
2712 * LLC Host queue receive buffers. 2711 * LLC Host queue receive buffers.
2713 * 2712 *
2714 * Return Codes: 2713 * Return Codes:
2715 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2714 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2716 * dynamic buffer allocation). If the buffer allocation failed, the 2715 * dynamic buffer allocation). If the buffer allocation failed, the
2717 * already allocated buffers will not be released and the caller should do 2716 * already allocated buffers will not be released and the caller should do
2718 * this. 2717 * this.
2719 * 2718 *
2720 * Assumptions: 2719 * Assumptions:
2721 * The PDQ has been reset and the adapter and driver maintained Type 2 2720 * The PDQ has been reset and the adapter and driver maintained Type 2
2722 * register indices are cleared. 2721 * register indices are cleared.
2723 * 2722 *
2724 * Side Effects: 2723 * Side Effects:
2725 * Receive buffers are posted to the adapter LLC queue and the adapter 2724 * Receive buffers are posted to the adapter LLC queue and the adapter
2726 * is notified. 2725 * is notified.
2727 */ 2726 */
2728 2727
2729 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2728 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2730 { 2729 {
2731 int i, j; /* used in for loop */ 2730 int i, j; /* used in for loop */
2732 2731
2733 /* 2732 /*
2734 * Since each receive buffer is a single fragment of same length, initialize 2733 * Since each receive buffer is a single fragment of same length, initialize
2735 * first longword in each receive descriptor for entire LLC Host descriptor 2734 * first longword in each receive descriptor for entire LLC Host descriptor
2736 * block. Also initialize second longword in each receive descriptor with 2735 * block. Also initialize second longword in each receive descriptor with
2737 * physical address of receive buffer. We'll always allocate receive 2736 * physical address of receive buffer. We'll always allocate receive
2738 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2737 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2739 * block and produce new receive buffers by simply updating the receive 2738 * block and produce new receive buffers by simply updating the receive
2740 * producer index. 2739 * producer index.
2741 * 2740 *
2742 * Assumptions: 2741 * Assumptions:
2743 * To support all shipping versions of PDQ, the receive buffer size 2742 * To support all shipping versions of PDQ, the receive buffer size
2744 * must be mod 128 in length and the physical address must be 128 byte 2743 * must be mod 128 in length and the physical address must be 128 byte
2745 * aligned. In other words, bits 0-6 of the length and address must 2744 * aligned. In other words, bits 0-6 of the length and address must
2746 * be zero for the following descriptor field entries to be correct on 2745 * be zero for the following descriptor field entries to be correct on
2747 * all PDQ-based boards. We guaranteed both requirements during 2746 * all PDQ-based boards. We guaranteed both requirements during
2748 * driver initialization when we allocated memory for the receive buffers. 2747 * driver initialization when we allocated memory for the receive buffers.
2749 */ 2748 */
2750 2749
2751 if (get_buffers) { 2750 if (get_buffers) {
2752 #ifdef DYNAMIC_BUFFERS 2751 #ifdef DYNAMIC_BUFFERS
2753 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2752 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2754 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2753 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2755 { 2754 {
2756 struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO); 2755 struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2757 if (!newskb) 2756 if (!newskb)
2758 return -ENOMEM; 2757 return -ENOMEM;
2759 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2758 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2760 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2759 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2761 /* 2760 /*
2762 * align to 128 bytes for compatibility with 2761 * align to 128 bytes for compatibility with
2763 * the old EISA boards. 2762 * the old EISA boards.
2764 */ 2763 */
2765 2764
2766 my_skb_align(newskb, 128); 2765 my_skb_align(newskb, 128);
2767 bp->descr_block_virt->rcv_data[i + j].long_1 = 2766 bp->descr_block_virt->rcv_data[i + j].long_1 =
2768 (u32)pci_map_single(bp->pci_dev, newskb->data, 2767 (u32)pci_map_single(bp->pci_dev, newskb->data,
2769 NEW_SKB_SIZE, 2768 NEW_SKB_SIZE,
2770 PCI_DMA_FROMDEVICE); 2769 PCI_DMA_FROMDEVICE);
2771 /* 2770 /*
2772 * p_rcv_buff_va is only used inside the 2771 * p_rcv_buff_va is only used inside the
2773 * kernel so we put the skb pointer here. 2772 * kernel so we put the skb pointer here.
2774 */ 2773 */
2775 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2774 bp->p_rcv_buff_va[i+j] = (char *) newskb;
2776 } 2775 }
2777 #else 2776 #else
2778 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2777 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2779 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2778 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2780 { 2779 {
2781 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2780 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2782 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2781 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2783 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2782 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2784 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2783 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2785 } 2784 }
2786 #endif 2785 #endif
2787 } 2786 }
2788 2787
2789 /* Update receive producer and Type 2 register */ 2788 /* Update receive producer and Type 2 register */
2790 2789
2791 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2790 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2792 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2791 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2793 return 0; 2792 return 0;
2794 } 2793 }
2795 2794
2796 2795
2797 /* 2796 /*
2798 * ========================= 2797 * =========================
2799 * = dfx_rcv_queue_process = 2798 * = dfx_rcv_queue_process =
2800 * ========================= 2799 * =========================
2801 * 2800 *
2802 * Overview: 2801 * Overview:
2803 * Process received LLC frames. 2802 * Process received LLC frames.
2804 * 2803 *
2805 * Returns: 2804 * Returns:
2806 * None 2805 * None
2807 * 2806 *
2808 * Arguments: 2807 * Arguments:
2809 * bp - pointer to board information 2808 * bp - pointer to board information
2810 * 2809 *
2811 * Functional Description: 2810 * Functional Description:
2812 * Received LLC frames are processed until there are no more consumed frames. 2811 * Received LLC frames are processed until there are no more consumed frames.
2813 * Once all frames are processed, the receive buffers are returned to the 2812 * Once all frames are processed, the receive buffers are returned to the
2814 * adapter. Note that this algorithm fixes the length of time that can be spent 2813 * adapter. Note that this algorithm fixes the length of time that can be spent
2815 * in this routine, because there are a fixed number of receive buffers to 2814 * in this routine, because there are a fixed number of receive buffers to
2816 * process and buffers are not produced until this routine exits and returns 2815 * process and buffers are not produced until this routine exits and returns
2817 * to the ISR. 2816 * to the ISR.
2818 * 2817 *
2819 * Return Codes: 2818 * Return Codes:
2820 * None 2819 * None
2821 * 2820 *
2822 * Assumptions: 2821 * Assumptions:
2823 * None 2822 * None
2824 * 2823 *
2825 * Side Effects: 2824 * Side Effects:
2826 * None 2825 * None
2827 */ 2826 */
2828 2827
2829 static void dfx_rcv_queue_process( 2828 static void dfx_rcv_queue_process(
2830 DFX_board_t *bp 2829 DFX_board_t *bp
2831 ) 2830 )
2832 2831
2833 { 2832 {
2834 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 2833 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
2835 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 2834 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
2836 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 2835 u32 descr, pkt_len; /* FMC descriptor field and packet length */
2837 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 2836 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
2838 2837
2839 /* Service all consumed LLC receive frames */ 2838 /* Service all consumed LLC receive frames */
2840 2839
2841 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 2840 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
2842 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 2841 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
2843 { 2842 {
2844 /* Process any errors */ 2843 /* Process any errors */
2845 2844
2846 int entry; 2845 int entry;
2847 2846
2848 entry = bp->rcv_xmt_reg.index.rcv_comp; 2847 entry = bp->rcv_xmt_reg.index.rcv_comp;
2849 #ifdef DYNAMIC_BUFFERS 2848 #ifdef DYNAMIC_BUFFERS
2850 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 2849 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
2851 #else 2850 #else
2852 p_buff = (char *) bp->p_rcv_buff_va[entry]; 2851 p_buff = (char *) bp->p_rcv_buff_va[entry];
2853 #endif 2852 #endif
2854 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 2853 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
2855 2854
2856 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 2855 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
2857 { 2856 {
2858 if (descr & PI_FMC_DESCR_M_RCC_CRC) 2857 if (descr & PI_FMC_DESCR_M_RCC_CRC)
2859 bp->rcv_crc_errors++; 2858 bp->rcv_crc_errors++;
2860 else 2859 else
2861 bp->rcv_frame_status_errors++; 2860 bp->rcv_frame_status_errors++;
2862 } 2861 }
2863 else 2862 else
2864 { 2863 {
2865 int rx_in_place = 0; 2864 int rx_in_place = 0;
2866 2865
2867 /* The frame was received without errors - verify packet length */ 2866 /* The frame was received without errors - verify packet length */
2868 2867
2869 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 2868 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
2870 pkt_len -= 4; /* subtract 4 byte CRC */ 2869 pkt_len -= 4; /* subtract 4 byte CRC */
2871 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 2870 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
2872 bp->rcv_length_errors++; 2871 bp->rcv_length_errors++;
2873 else{ 2872 else{
2874 #ifdef DYNAMIC_BUFFERS 2873 #ifdef DYNAMIC_BUFFERS
2875 if (pkt_len > SKBUFF_RX_COPYBREAK) { 2874 if (pkt_len > SKBUFF_RX_COPYBREAK) {
2876 struct sk_buff *newskb; 2875 struct sk_buff *newskb;
2877 2876
2878 newskb = dev_alloc_skb(NEW_SKB_SIZE); 2877 newskb = dev_alloc_skb(NEW_SKB_SIZE);
2879 if (newskb){ 2878 if (newskb){
2880 rx_in_place = 1; 2879 rx_in_place = 1;
2881 2880
2882 my_skb_align(newskb, 128); 2881 my_skb_align(newskb, 128);
2883 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 2882 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
2884 pci_unmap_single(bp->pci_dev, 2883 pci_unmap_single(bp->pci_dev,
2885 bp->descr_block_virt->rcv_data[entry].long_1, 2884 bp->descr_block_virt->rcv_data[entry].long_1,
2886 NEW_SKB_SIZE, 2885 NEW_SKB_SIZE,
2887 PCI_DMA_FROMDEVICE); 2886 PCI_DMA_FROMDEVICE);
2888 skb_reserve(skb, RCV_BUFF_K_PADDING); 2887 skb_reserve(skb, RCV_BUFF_K_PADDING);
2889 bp->p_rcv_buff_va[entry] = (char *)newskb; 2888 bp->p_rcv_buff_va[entry] = (char *)newskb;
2890 bp->descr_block_virt->rcv_data[entry].long_1 = 2889 bp->descr_block_virt->rcv_data[entry].long_1 =
2891 (u32)pci_map_single(bp->pci_dev, 2890 (u32)pci_map_single(bp->pci_dev,
2892 newskb->data, 2891 newskb->data,
2893 NEW_SKB_SIZE, 2892 NEW_SKB_SIZE,
2894 PCI_DMA_FROMDEVICE); 2893 PCI_DMA_FROMDEVICE);
2895 } else 2894 } else
2896 skb = NULL; 2895 skb = NULL;
2897 } else 2896 } else
2898 #endif 2897 #endif
2899 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 2898 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
2900 if (skb == NULL) 2899 if (skb == NULL)
2901 { 2900 {
2902 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 2901 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
2903 bp->rcv_discards++; 2902 bp->rcv_discards++;
2904 break; 2903 break;
2905 } 2904 }
2906 else { 2905 else {
2907 #ifndef DYNAMIC_BUFFERS 2906 #ifndef DYNAMIC_BUFFERS
2908 if (! rx_in_place) 2907 if (! rx_in_place)
2909 #endif 2908 #endif
2910 { 2909 {
2911 /* Receive buffer allocated, pass receive packet up */ 2910 /* Receive buffer allocated, pass receive packet up */
2912 2911
2913 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3); 2912 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
2914 } 2913 }
2915 2914
2916 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 2915 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
2917 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 2916 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
2918 skb->dev = bp->dev; /* pass up device pointer */ 2917 skb->dev = bp->dev; /* pass up device pointer */
2919 2918
2920 skb->protocol = fddi_type_trans(skb, bp->dev); 2919 skb->protocol = fddi_type_trans(skb, bp->dev);
2921 bp->rcv_total_bytes += skb->len; 2920 bp->rcv_total_bytes += skb->len;
2922 netif_rx(skb); 2921 netif_rx(skb);
2923 2922
2924 /* Update the rcv counters */ 2923 /* Update the rcv counters */
2925 bp->dev->last_rx = jiffies; 2924 bp->dev->last_rx = jiffies;
2926 bp->rcv_total_frames++; 2925 bp->rcv_total_frames++;
2927 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 2926 if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
2928 bp->rcv_multicast_frames++; 2927 bp->rcv_multicast_frames++;
2929 } 2928 }
2930 } 2929 }
2931 } 2930 }
2932 2931
2933 /* 2932 /*
2934 * Advance the producer (for recycling) and advance the completion 2933 * Advance the producer (for recycling) and advance the completion
2935 * (for servicing received frames). Note that it is okay to 2934 * (for servicing received frames). Note that it is okay to
2936 * advance the producer without checking that it passes the 2935 * advance the producer without checking that it passes the
2937 * completion index because they are both advanced at the same 2936 * completion index because they are both advanced at the same
2938 * rate. 2937 * rate.
2939 */ 2938 */
2940 2939
2941 bp->rcv_xmt_reg.index.rcv_prod += 1; 2940 bp->rcv_xmt_reg.index.rcv_prod += 1;
2942 bp->rcv_xmt_reg.index.rcv_comp += 1; 2941 bp->rcv_xmt_reg.index.rcv_comp += 1;
2943 } 2942 }
2944 } 2943 }
2945 2944
2946 2945
2947 /* 2946 /*
2948 * ===================== 2947 * =====================
2949 * = dfx_xmt_queue_pkt = 2948 * = dfx_xmt_queue_pkt =
2950 * ===================== 2949 * =====================
2951 * 2950 *
2952 * Overview: 2951 * Overview:
2953 * Queues packets for transmission 2952 * Queues packets for transmission
2954 * 2953 *
2955 * Returns: 2954 * Returns:
2956 * Condition code 2955 * Condition code
2957 * 2956 *
2958 * Arguments: 2957 * Arguments:
2959 * skb - pointer to sk_buff to queue for transmission 2958 * skb - pointer to sk_buff to queue for transmission
2960 * dev - pointer to device information 2959 * dev - pointer to device information
2961 * 2960 *
2962 * Functional Description: 2961 * Functional Description:
2963 * Here we assume that an incoming skb transmit request 2962 * Here we assume that an incoming skb transmit request
2964 * is contained in a single physically contiguous buffer 2963 * is contained in a single physically contiguous buffer
2965 * in which the virtual address of the start of packet 2964 * in which the virtual address of the start of packet
2966 * (skb->data) can be converted to a physical address 2965 * (skb->data) can be converted to a physical address
2967 * by using pci_map_single(). 2966 * by using pci_map_single().
2968 * 2967 *
2969 * Since the adapter architecture requires a three byte 2968 * Since the adapter architecture requires a three byte
2970 * packet request header to prepend the start of packet, 2969 * packet request header to prepend the start of packet,
2971 * we'll write the three byte field immediately prior to 2970 * we'll write the three byte field immediately prior to
2972 * the FC byte. This assumption is valid because we've 2971 * the FC byte. This assumption is valid because we've
2973 * ensured that dev->hard_header_len includes three pad 2972 * ensured that dev->hard_header_len includes three pad
2974 * bytes. By posting a single fragment to the adapter, 2973 * bytes. By posting a single fragment to the adapter,
2975 * we'll reduce the number of descriptor fetches and 2974 * we'll reduce the number of descriptor fetches and
2976 * bus traffic needed to send the request. 2975 * bus traffic needed to send the request.
2977 * 2976 *
2978 * Also, we can't free the skb until after it's been DMA'd 2977 * Also, we can't free the skb until after it's been DMA'd
2979 * out by the adapter, so we'll queue it in the driver and 2978 * out by the adapter, so we'll queue it in the driver and
2980 * return it in dfx_xmt_done. 2979 * return it in dfx_xmt_done.
2981 * 2980 *
2982 * Return Codes: 2981 * Return Codes:
2983 * 0 - driver queued packet, link is unavailable, or skbuff was bad 2982 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2984 * 1 - caller should requeue the sk_buff for later transmission 2983 * 1 - caller should requeue the sk_buff for later transmission
2985 * 2984 *
2986 * Assumptions: 2985 * Assumptions:
2987 * First and foremost, we assume the incoming skb pointer 2986 * First and foremost, we assume the incoming skb pointer
2988 * is NOT NULL and is pointing to a valid sk_buff structure. 2987 * is NOT NULL and is pointing to a valid sk_buff structure.
2989 * 2988 *
2990 * The outgoing packet is complete, starting with the 2989 * The outgoing packet is complete, starting with the
2991 * frame control byte including the last byte of data, 2990 * frame control byte including the last byte of data,
2992 * but NOT including the 4 byte CRC. We'll let the 2991 * but NOT including the 4 byte CRC. We'll let the
2993 * adapter hardware generate and append the CRC. 2992 * adapter hardware generate and append the CRC.
2994 * 2993 *
2995 * The entire packet is stored in one physically 2994 * The entire packet is stored in one physically
2996 * contiguous buffer which is not cached and whose 2995 * contiguous buffer which is not cached and whose
2997 * 32-bit physical address can be determined. 2996 * 32-bit physical address can be determined.
2998 * 2997 *
2999 * It's vital that this routine is NOT reentered for the 2998 * It's vital that this routine is NOT reentered for the
3000 * same board and that the OS is not in another section of 2999 * same board and that the OS is not in another section of
3001 * code (eg. dfx_int_common) for the same board on a 3000 * code (eg. dfx_int_common) for the same board on a
3002 * different thread. 3001 * different thread.
3003 * 3002 *
3004 * Side Effects: 3003 * Side Effects:
3005 * None 3004 * None
3006 */ 3005 */
3007 3006
3008 static int dfx_xmt_queue_pkt( 3007 static int dfx_xmt_queue_pkt(
3009 struct sk_buff *skb, 3008 struct sk_buff *skb,
3010 struct net_device *dev 3009 struct net_device *dev
3011 ) 3010 )
3012 3011
3013 { 3012 {
3014 DFX_board_t *bp = dev->priv; 3013 DFX_board_t *bp = dev->priv;
3015 u8 prod; /* local transmit producer index */ 3014 u8 prod; /* local transmit producer index */
3016 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3015 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
3017 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3016 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3018 unsigned long flags; 3017 unsigned long flags;
3019 3018
3020 netif_stop_queue(dev); 3019 netif_stop_queue(dev);
3021 3020
3022 /* 3021 /*
3023 * Verify that incoming transmit request is OK 3022 * Verify that incoming transmit request is OK
3024 * 3023 *
3025 * Note: The packet size check is consistent with other 3024 * Note: The packet size check is consistent with other
3026 * Linux device drivers, although the correct packet 3025 * Linux device drivers, although the correct packet
3027 * size should be verified before calling the 3026 * size should be verified before calling the
3028 * transmit routine. 3027 * transmit routine.
3029 */ 3028 */
3030 3029
3031 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3030 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3032 { 3031 {
3033 printk("%s: Invalid packet length - %u bytes\n", 3032 printk("%s: Invalid packet length - %u bytes\n",
3034 dev->name, skb->len); 3033 dev->name, skb->len);
3035 bp->xmt_length_errors++; /* bump error counter */ 3034 bp->xmt_length_errors++; /* bump error counter */
3036 netif_wake_queue(dev); 3035 netif_wake_queue(dev);
3037 dev_kfree_skb(skb); 3036 dev_kfree_skb(skb);
3038 return(0); /* return "success" */ 3037 return(0); /* return "success" */
3039 } 3038 }
3040 /* 3039 /*
3041 * See if adapter link is available, if not, free buffer 3040 * See if adapter link is available, if not, free buffer
3042 * 3041 *
3043 * Note: If the link isn't available, free buffer and return 0 3042 * Note: If the link isn't available, free buffer and return 0
3044 * rather than tell the upper layer to requeue the packet. 3043 * rather than tell the upper layer to requeue the packet.
3045 * The methodology here is that by the time the link 3044 * The methodology here is that by the time the link
3046 * becomes available, the packet to be sent will be 3045 * becomes available, the packet to be sent will be
3047 * fairly stale. By simply dropping the packet, the 3046 * fairly stale. By simply dropping the packet, the
3048 * higher layer protocols will eventually time out 3047 * higher layer protocols will eventually time out
3049 * waiting for response packets which it won't receive. 3048 * waiting for response packets which it won't receive.
3050 */ 3049 */
3051 3050
3052 if (bp->link_available == PI_K_FALSE) 3051 if (bp->link_available == PI_K_FALSE)
3053 { 3052 {
3054 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3053 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
3055 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3054 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
3056 else 3055 else
3057 { 3056 {
3058 bp->xmt_discards++; /* bump error counter */ 3057 bp->xmt_discards++; /* bump error counter */
3059 dev_kfree_skb(skb); /* free sk_buff now */ 3058 dev_kfree_skb(skb); /* free sk_buff now */
3060 netif_wake_queue(dev); 3059 netif_wake_queue(dev);
3061 return(0); /* return "success" */ 3060 return(0); /* return "success" */
3062 } 3061 }
3063 } 3062 }
3064 3063
3065 spin_lock_irqsave(&bp->lock, flags); 3064 spin_lock_irqsave(&bp->lock, flags);
3066 3065
3067 /* Get the current producer and the next free xmt data descriptor */ 3066 /* Get the current producer and the next free xmt data descriptor */
3068 3067
3069 prod = bp->rcv_xmt_reg.index.xmt_prod; 3068 prod = bp->rcv_xmt_reg.index.xmt_prod;
3070 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3069 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3071 3070
3072 /* 3071 /*
3073 * Get pointer to auxiliary queue entry to contain information 3072 * Get pointer to auxiliary queue entry to contain information
3074 * for this packet. 3073 * for this packet.
3075 * 3074 *
3076 * Note: The current xmt producer index will become the 3075 * Note: The current xmt producer index will become the
3077 * current xmt completion index when we complete this 3076 * current xmt completion index when we complete this
3078 * packet later on. So, we'll get the pointer to the 3077 * packet later on. So, we'll get the pointer to the
3079 * next auxiliary queue entry now before we bump the 3078 * next auxiliary queue entry now before we bump the
3080 * producer index. 3079 * producer index.
3081 */ 3080 */
3082 3081
3083 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3082 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
3084 3083
3085 /* Write the three PRH bytes immediately before the FC byte */ 3084 /* Write the three PRH bytes immediately before the FC byte */
3086 3085
3087 skb_push(skb,3); 3086 skb_push(skb,3);
3088 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3087 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
3089 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3088 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
3090 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3089 skb->data[2] = DFX_PRH2_BYTE; /* specification */
3091 3090
3092 /* 3091 /*
3093 * Write the descriptor with buffer info and bump producer 3092 * Write the descriptor with buffer info and bump producer
3094 * 3093 *
3095 * Note: Since we need to start DMA from the packet request 3094 * Note: Since we need to start DMA from the packet request
3096 * header, we'll add 3 bytes to the DMA buffer length, 3095 * header, we'll add 3 bytes to the DMA buffer length,
3097 * and we'll determine the physical address of the 3096 * and we'll determine the physical address of the
3098 * buffer from the PRH, not skb->data. 3097 * buffer from the PRH, not skb->data.
3099 * 3098 *
3100 * Assumptions: 3099 * Assumptions:
3101 * 1. Packet starts with the frame control (FC) byte 3100 * 1. Packet starts with the frame control (FC) byte
3102 * at skb->data. 3101 * at skb->data.
3103 * 2. The 4-byte CRC is not appended to the buffer or 3102 * 2. The 4-byte CRC is not appended to the buffer or
3104 * included in the length. 3103 * included in the length.
3105 * 3. Packet length (skb->len) is from FC to end of 3104 * 3. Packet length (skb->len) is from FC to end of
3106 * data, inclusive. 3105 * data, inclusive.
3107 * 4. The packet length does not exceed the maximum 3106 * 4. The packet length does not exceed the maximum
3108 * FDDI LLC frame length of 4491 bytes. 3107 * FDDI LLC frame length of 4491 bytes.
3109 * 5. The entire packet is contained in a physically 3108 * 5. The entire packet is contained in a physically
3110 * contiguous, non-cached, locked memory space 3109 * contiguous, non-cached, locked memory space
3111 * comprised of a single buffer pointed to by 3110 * comprised of a single buffer pointed to by
3112 * skb->data. 3111 * skb->data.
3113 * 6. The physical address of the start of packet 3112 * 6. The physical address of the start of packet
3114 * can be determined from the virtual address 3113 * can be determined from the virtual address
3115 * by using pci_map_single() and is only 32-bits 3114 * by using pci_map_single() and is only 32-bits
3116 * wide. 3115 * wide.
3117 */ 3116 */
3118 3117
3119 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3118 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3120 p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data, 3119 p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data,
3121 skb->len, PCI_DMA_TODEVICE); 3120 skb->len, PCI_DMA_TODEVICE);
3122 3121
3123 /* 3122 /*
3124 * Verify that descriptor is actually available 3123 * Verify that descriptor is actually available
3125 * 3124 *
3126 * Note: If descriptor isn't available, return 1 which tells 3125 * Note: If descriptor isn't available, return 1 which tells
3127 * the upper layer to requeue the packet for later 3126 * the upper layer to requeue the packet for later
3128 * transmission. 3127 * transmission.
3129 * 3128 *
3130 * We need to ensure that the producer never reaches the 3129 * We need to ensure that the producer never reaches the
3131 * completion, except to indicate that the queue is empty. 3130 * completion, except to indicate that the queue is empty.
3132 */ 3131 */
3133 3132
3134 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3133 if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3135 { 3134 {
3136 skb_pull(skb,3); 3135 skb_pull(skb,3);
3137 spin_unlock_irqrestore(&bp->lock, flags); 3136 spin_unlock_irqrestore(&bp->lock, flags);
3138 return(1); /* requeue packet for later */ 3137 return(1); /* requeue packet for later */
3139 } 3138 }
3140 3139
3141 /* 3140 /*
3142 * Save info for this packet for xmt done indication routine 3141 * Save info for this packet for xmt done indication routine
3143 * 3142 *
3144 * Normally, we'd save the producer index in the p_xmt_drv_descr 3143 * Normally, we'd save the producer index in the p_xmt_drv_descr
3145 * structure so that we'd have it handy when we complete this 3144 * structure so that we'd have it handy when we complete this
3146 * packet later (in dfx_xmt_done). However, since the current 3145 * packet later (in dfx_xmt_done). However, since the current
3147 * transmit architecture guarantees a single fragment for the 3146 * transmit architecture guarantees a single fragment for the
3148 * entire packet, we can simply bump the completion index by 3147 * entire packet, we can simply bump the completion index by
3149 * one (1) for each completed packet. 3148 * one (1) for each completed packet.
3150 * 3149 *
3151 * Note: If this assumption changes and we're presented with 3150 * Note: If this assumption changes and we're presented with
3152 * an inconsistent number of transmit fragments for packet 3151 * an inconsistent number of transmit fragments for packet
3153 * data, we'll need to modify this code to save the current 3152 * data, we'll need to modify this code to save the current
3154 * transmit producer index. 3153 * transmit producer index.
3155 */ 3154 */
3156 3155
3157 p_xmt_drv_descr->p_skb = skb; 3156 p_xmt_drv_descr->p_skb = skb;
3158 3157
3159 /* Update Type 2 register */ 3158 /* Update Type 2 register */
3160 3159
3161 bp->rcv_xmt_reg.index.xmt_prod = prod; 3160 bp->rcv_xmt_reg.index.xmt_prod = prod;
3162 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3161 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3163 spin_unlock_irqrestore(&bp->lock, flags); 3162 spin_unlock_irqrestore(&bp->lock, flags);
3164 netif_wake_queue(dev); 3163 netif_wake_queue(dev);
3165 return(0); /* packet queued to adapter */ 3164 return(0); /* packet queued to adapter */
3166 } 3165 }
3167 3166
3168 3167
3169 /* 3168 /*
3170 * ================ 3169 * ================
3171 * = dfx_xmt_done = 3170 * = dfx_xmt_done =
3172 * ================ 3171 * ================
3173 * 3172 *
3174 * Overview: 3173 * Overview:
3175 * Processes all frames that have been transmitted. 3174 * Processes all frames that have been transmitted.
3176 * 3175 *
3177 * Returns: 3176 * Returns:
3178 * None 3177 * None
3179 * 3178 *
3180 * Arguments: 3179 * Arguments:
3181 * bp - pointer to board information 3180 * bp - pointer to board information
3182 * 3181 *
3183 * Functional Description: 3182 * Functional Description:
3184 * For all consumed transmit descriptors that have not 3183 * For all consumed transmit descriptors that have not
3185 * yet been completed, we'll free the skb we were holding 3184 * yet been completed, we'll free the skb we were holding
3186 * onto using dev_kfree_skb and bump the appropriate 3185 * onto using dev_kfree_skb and bump the appropriate
3187 * counters. 3186 * counters.
3188 * 3187 *
3189 * Return Codes: 3188 * Return Codes:
3190 * None 3189 * None
3191 * 3190 *
3192 * Assumptions: 3191 * Assumptions:
3193 * The Type 2 register is not updated in this routine. It is 3192 * The Type 2 register is not updated in this routine. It is
3194 * assumed that it will be updated in the ISR when dfx_xmt_done 3193 * assumed that it will be updated in the ISR when dfx_xmt_done
3195 * returns. 3194 * returns.
3196 * 3195 *
3197 * Side Effects: 3196 * Side Effects:
3198 * None 3197 * None
3199 */ 3198 */
3200 3199
3201 static int dfx_xmt_done(DFX_board_t *bp) 3200 static int dfx_xmt_done(DFX_board_t *bp)
3202 { 3201 {
3203 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3202 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3204 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3203 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3205 u8 comp; /* local transmit completion index */ 3204 u8 comp; /* local transmit completion index */
3206 int freed = 0; /* buffers freed */ 3205 int freed = 0; /* buffers freed */
3207 3206
3208 /* Service all consumed transmit frames */ 3207 /* Service all consumed transmit frames */
3209 3208
3210 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3209 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3211 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3210 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3212 { 3211 {
3213 /* Get pointer to the transmit driver descriptor block information */ 3212 /* Get pointer to the transmit driver descriptor block information */
3214 3213
3215 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3214 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3216 3215
3217 /* Increment transmit counters */ 3216 /* Increment transmit counters */
3218 3217
3219 bp->xmt_total_frames++; 3218 bp->xmt_total_frames++;
3220 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3219 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3221 3220
3222 /* Return skb to operating system */ 3221 /* Return skb to operating system */
3223 comp = bp->rcv_xmt_reg.index.xmt_comp; 3222 comp = bp->rcv_xmt_reg.index.xmt_comp;
3224 pci_unmap_single(bp->pci_dev, 3223 pci_unmap_single(bp->pci_dev,
3225 bp->descr_block_virt->xmt_data[comp].long_1, 3224 bp->descr_block_virt->xmt_data[comp].long_1,
3226 p_xmt_drv_descr->p_skb->len, 3225 p_xmt_drv_descr->p_skb->len,
3227 PCI_DMA_TODEVICE); 3226 PCI_DMA_TODEVICE);
3228 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3227 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3229 3228
3230 /* 3229 /*
3231 * Move to start of next packet by updating completion index 3230 * Move to start of next packet by updating completion index
3232 * 3231 *
3233 * Here we assume that a transmit packet request is always 3232 * Here we assume that a transmit packet request is always
3234 * serviced by posting one fragment. We can therefore 3233 * serviced by posting one fragment. We can therefore
3235 * simplify the completion code by incrementing the 3234 * simplify the completion code by incrementing the
3236 * completion index by one. This code will need to be 3235 * completion index by one. This code will need to be
3237 * modified if this assumption changes. See comments 3236 * modified if this assumption changes. See comments
3238 * in dfx_xmt_queue_pkt for more details. 3237 * in dfx_xmt_queue_pkt for more details.
3239 */ 3238 */
3240 3239
3241 bp->rcv_xmt_reg.index.xmt_comp += 1; 3240 bp->rcv_xmt_reg.index.xmt_comp += 1;
3242 freed++; 3241 freed++;
3243 } 3242 }
3244 return freed; 3243 return freed;
3245 } 3244 }
3246 3245
3247 3246
3248 /* 3247 /*
3249 * ================= 3248 * =================
3250 * = dfx_rcv_flush = 3249 * = dfx_rcv_flush =
3251 * ================= 3250 * =================
3252 * 3251 *
3253 * Overview: 3252 * Overview:
3254 * Remove all skb's in the receive ring. 3253 * Remove all skb's in the receive ring.
3255 * 3254 *
3256 * Returns: 3255 * Returns:
3257 * None 3256 * None
3258 * 3257 *
3259 * Arguments: 3258 * Arguments:
3260 * bp - pointer to board information 3259 * bp - pointer to board information
3261 * 3260 *
3262 * Functional Description: 3261 * Functional Description:
3263 * Free's all the dynamically allocated skb's that are 3262 * Free's all the dynamically allocated skb's that are
3264 * currently attached to the device receive ring. This 3263 * currently attached to the device receive ring. This
3265 * function is typically only used when the device is 3264 * function is typically only used when the device is
3266 * initialized or reinitialized. 3265 * initialized or reinitialized.
3267 * 3266 *
3268 * Return Codes: 3267 * Return Codes:
3269 * None 3268 * None
3270 * 3269 *
3271 * Side Effects: 3270 * Side Effects:
3272 * None 3271 * None
3273 */ 3272 */
3274 #ifdef DYNAMIC_BUFFERS 3273 #ifdef DYNAMIC_BUFFERS
3275 static void dfx_rcv_flush( DFX_board_t *bp ) 3274 static void dfx_rcv_flush( DFX_board_t *bp )
3276 { 3275 {
3277 int i, j; 3276 int i, j;
3278 3277
3279 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3278 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3280 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3279 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3281 { 3280 {
3282 struct sk_buff *skb; 3281 struct sk_buff *skb;
3283 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3282 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3284 if (skb) 3283 if (skb)
3285 dev_kfree_skb(skb); 3284 dev_kfree_skb(skb);
3286 bp->p_rcv_buff_va[i+j] = NULL; 3285 bp->p_rcv_buff_va[i+j] = NULL;
3287 } 3286 }
3288 3287
3289 } 3288 }
3290 #else 3289 #else
3291 static inline void dfx_rcv_flush( DFX_board_t *bp ) 3290 static inline void dfx_rcv_flush( DFX_board_t *bp )
3292 { 3291 {
3293 } 3292 }
3294 #endif /* DYNAMIC_BUFFERS */ 3293 #endif /* DYNAMIC_BUFFERS */
3295 3294
3296 /* 3295 /*
3297 * ================= 3296 * =================
3298 * = dfx_xmt_flush = 3297 * = dfx_xmt_flush =
3299 * ================= 3298 * =================
3300 * 3299 *
3301 * Overview: 3300 * Overview:
3302 * Processes all frames whether they've been transmitted 3301 * Processes all frames whether they've been transmitted
3303 * or not. 3302 * or not.
3304 * 3303 *
3305 * Returns: 3304 * Returns:
3306 * None 3305 * None
3307 * 3306 *
3308 * Arguments: 3307 * Arguments:
3309 * bp - pointer to board information 3308 * bp - pointer to board information
3310 * 3309 *
3311 * Functional Description: 3310 * Functional Description:
3312 * For all produced transmit descriptors that have not 3311 * For all produced transmit descriptors that have not
3313 * yet been completed, we'll free the skb we were holding 3312 * yet been completed, we'll free the skb we were holding
3314 * onto using dev_kfree_skb and bump the appropriate 3313 * onto using dev_kfree_skb and bump the appropriate
3315 * counters. Of course, it's possible that some of 3314 * counters. Of course, it's possible that some of
3316 * these transmit requests actually did go out, but we 3315 * these transmit requests actually did go out, but we
3317 * won't make that distinction here. Finally, we'll 3316 * won't make that distinction here. Finally, we'll
3318 * update the consumer index to match the producer. 3317 * update the consumer index to match the producer.
3319 * 3318 *
3320 * Return Codes: 3319 * Return Codes:
3321 * None 3320 * None
3322 * 3321 *
3323 * Assumptions: 3322 * Assumptions:
3324 * This routine does NOT update the Type 2 register. It 3323 * This routine does NOT update the Type 2 register. It
3325 * is assumed that this routine is being called during a 3324 * is assumed that this routine is being called during a
3326 * transmit flush interrupt, or a shutdown or close routine. 3325 * transmit flush interrupt, or a shutdown or close routine.
3327 * 3326 *
3328 * Side Effects: 3327 * Side Effects:
3329 * None 3328 * None
3330 */ 3329 */
3331 3330
3332 static void dfx_xmt_flush( DFX_board_t *bp ) 3331 static void dfx_xmt_flush( DFX_board_t *bp )
3333 { 3332 {
3334 u32 prod_cons; /* rcv/xmt consumer block longword */ 3333 u32 prod_cons; /* rcv/xmt consumer block longword */
3335 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3334 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3336 u8 comp; /* local transmit completion index */ 3335 u8 comp; /* local transmit completion index */
3337 3336
3338 /* Flush all outstanding transmit frames */ 3337 /* Flush all outstanding transmit frames */
3339 3338
3340 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3339 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3341 { 3340 {
3342 /* Get pointer to the transmit driver descriptor block information */ 3341 /* Get pointer to the transmit driver descriptor block information */
3343 3342
3344 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3343 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3345 3344
3346 /* Return skb to operating system */ 3345 /* Return skb to operating system */
3347 comp = bp->rcv_xmt_reg.index.xmt_comp; 3346 comp = bp->rcv_xmt_reg.index.xmt_comp;
3348 pci_unmap_single(bp->pci_dev, 3347 pci_unmap_single(bp->pci_dev,
3349 bp->descr_block_virt->xmt_data[comp].long_1, 3348 bp->descr_block_virt->xmt_data[comp].long_1,
3350 p_xmt_drv_descr->p_skb->len, 3349 p_xmt_drv_descr->p_skb->len,
3351 PCI_DMA_TODEVICE); 3350 PCI_DMA_TODEVICE);
3352 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3351 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3353 3352
3354 /* Increment transmit error counter */ 3353 /* Increment transmit error counter */
3355 3354
3356 bp->xmt_discards++; 3355 bp->xmt_discards++;
3357 3356
3358 /* 3357 /*
3359 * Move to start of next packet by updating completion index 3358 * Move to start of next packet by updating completion index
3360 * 3359 *
3361 * Here we assume that a transmit packet request is always 3360 * Here we assume that a transmit packet request is always
3362 * serviced by posting one fragment. We can therefore 3361 * serviced by posting one fragment. We can therefore
3363 * simplify the completion code by incrementing the 3362 * simplify the completion code by incrementing the
3364 * completion index by one. This code will need to be 3363 * completion index by one. This code will need to be
3365 * modified if this assumption changes. See comments 3364 * modified if this assumption changes. See comments
3366 * in dfx_xmt_queue_pkt for more details. 3365 * in dfx_xmt_queue_pkt for more details.
3367 */ 3366 */
3368 3367
3369 bp->rcv_xmt_reg.index.xmt_comp += 1; 3368 bp->rcv_xmt_reg.index.xmt_comp += 1;
3370 } 3369 }
3371 3370
3372 /* Update the transmit consumer index in the consumer block */ 3371 /* Update the transmit consumer index in the consumer block */
3373 3372
3374 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3373 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3375 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3374 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3376 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3375 bp->cons_block_virt->xmt_rcv_data = prod_cons;
3377 } 3376 }
3378 3377
3379 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev) 3378 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev)
3380 { 3379 {
3381 DFX_board_t *bp = dev->priv; 3380 DFX_board_t *bp = dev->priv;
3382 int alloc_size; /* total buffer size used */ 3381 int alloc_size; /* total buffer size used */
3383 3382
3384 unregister_netdev(dev); 3383 unregister_netdev(dev);
3385 release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN ); 3384 release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN );
3386 3385
3387 alloc_size = sizeof(PI_DESCR_BLOCK) + 3386 alloc_size = sizeof(PI_DESCR_BLOCK) +
3388 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3387 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3389 #ifndef DYNAMIC_BUFFERS 3388 #ifndef DYNAMIC_BUFFERS
3390 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3389 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3391 #endif 3390 #endif
3392 sizeof(PI_CONSUMER_BLOCK) + 3391 sizeof(PI_CONSUMER_BLOCK) +
3393 (PI_ALIGN_K_DESC_BLK - 1); 3392 (PI_ALIGN_K_DESC_BLK - 1);
3394 if (bp->kmalloced) 3393 if (bp->kmalloced)
3395 pci_free_consistent(pdev, alloc_size, bp->kmalloced, 3394 pci_free_consistent(pdev, alloc_size, bp->kmalloced,
3396 bp->kmalloced_dma); 3395 bp->kmalloced_dma);
3397 free_netdev(dev); 3396 free_netdev(dev);
3398 } 3397 }
3399 3398
3400 static void __devexit dfx_remove_one (struct pci_dev *pdev) 3399 static void __devexit dfx_remove_one (struct pci_dev *pdev)
3401 { 3400 {
3402 struct net_device *dev = pci_get_drvdata(pdev); 3401 struct net_device *dev = pci_get_drvdata(pdev);
3403 3402
3404 dfx_remove_one_pci_or_eisa(pdev, dev); 3403 dfx_remove_one_pci_or_eisa(pdev, dev);
3405 pci_set_drvdata(pdev, NULL); 3404 pci_set_drvdata(pdev, NULL);
3406 } 3405 }
3407 3406
3408 static struct pci_device_id dfx_pci_tbl[] = { 3407 static struct pci_device_id dfx_pci_tbl[] = {
3409 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, }, 3408 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, },
3410 { 0, } 3409 { 0, }
3411 }; 3410 };
3412 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl); 3411 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl);
3413 3412
3414 static struct pci_driver dfx_driver = { 3413 static struct pci_driver dfx_driver = {
3415 .name = "defxx", 3414 .name = "defxx",
3416 .probe = dfx_init_one, 3415 .probe = dfx_init_one,
3417 .remove = __devexit_p(dfx_remove_one), 3416 .remove = __devexit_p(dfx_remove_one),
3418 .id_table = dfx_pci_tbl, 3417 .id_table = dfx_pci_tbl,
3419 }; 3418 };
3420 3419
3421 static int dfx_have_pci; 3420 static int dfx_have_pci;
3422 static int dfx_have_eisa; 3421 static int dfx_have_eisa;
3423 3422
3424 3423
3425 static void __exit dfx_eisa_cleanup(void) 3424 static void __exit dfx_eisa_cleanup(void)
3426 { 3425 {
3427 struct net_device *dev = root_dfx_eisa_dev; 3426 struct net_device *dev = root_dfx_eisa_dev;
3428 3427
3429 while (dev) 3428 while (dev)
3430 { 3429 {
3431 struct net_device *tmp; 3430 struct net_device *tmp;
3432 DFX_board_t *bp; 3431 DFX_board_t *bp;
3433 3432
3434 bp = (DFX_board_t*)dev->priv; 3433 bp = (DFX_board_t*)dev->priv;
3435 tmp = bp->next; 3434 tmp = bp->next;
3436 dfx_remove_one_pci_or_eisa(NULL, dev); 3435 dfx_remove_one_pci_or_eisa(NULL, dev);
3437 dev = tmp; 3436 dev = tmp;
3438 } 3437 }
3439 } 3438 }
3440 3439
3441 static int __init dfx_init(void) 3440 static int __init dfx_init(void)
3442 { 3441 {
3443 int rc_pci, rc_eisa; 3442 int rc_pci, rc_eisa;
3444 3443
3445 rc_pci = pci_register_driver(&dfx_driver); 3444 rc_pci = pci_register_driver(&dfx_driver);
3446 if (rc_pci >= 0) dfx_have_pci = 1; 3445 if (rc_pci >= 0) dfx_have_pci = 1;
3447 3446
3448 rc_eisa = dfx_eisa_init(); 3447 rc_eisa = dfx_eisa_init();
3449 if (rc_eisa >= 0) dfx_have_eisa = 1; 3448 if (rc_eisa >= 0) dfx_have_eisa = 1;
3450 3449
3451 return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci); 3450 return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci);
3452 } 3451 }
3453 3452
3454 static void __exit dfx_cleanup(void) 3453 static void __exit dfx_cleanup(void)
3455 { 3454 {
3456 if (dfx_have_pci) 3455 if (dfx_have_pci)
3457 pci_unregister_driver(&dfx_driver); 3456 pci_unregister_driver(&dfx_driver);
3458 if (dfx_have_eisa) 3457 if (dfx_have_eisa)
3459 dfx_eisa_cleanup(); 3458 dfx_eisa_cleanup();
3460 3459
3461 } 3460 }
3462 3461
3463 module_init(dfx_init); 3462 module_init(dfx_init);
3464 module_exit(dfx_cleanup); 3463 module_exit(dfx_cleanup);
3465 MODULE_AUTHOR("Lawrence V. Stefani"); 3464 MODULE_AUTHOR("Lawrence V. Stefani");
3466 MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver " 3465 MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver "
3467 DRV_VERSION " " DRV_RELDATE); 3466 DRV_VERSION " " DRV_RELDATE);
3468 MODULE_LICENSE("GPL"); 3467 MODULE_LICENSE("GPL");
3469 3468
3470 3469
3471 /* 3470 /*
3472 * Local variables: 3471 * Local variables:
1 /* 1 /*
2 * File Name: 2 * File Name:
3 * defxx.h 3 * defxx.h
4 * 4 *
5 * Copyright Information: 5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996. 6 * Copyright Digital Equipment Corporation 1996.
7 * 7 *
8 * This software may be used and distributed according to the terms of 8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference. 9 * the GNU General Public License, incorporated herein by reference.
10 * 10 *
11 * Abstract: 11 * Abstract:
12 * Contains all definitions specified by port specification and required 12 * Contains all definitions specified by port specification and required
13 * by the defxx.c driver. 13 * by the defxx.c driver.
14 * 14 *
15 * The original author: 15 * The original author:
16 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 16 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
17 * 17 *
18 * Maintainers: 18 * Maintainers:
19 * macro Maciej W. Rozycki <macro@linux-mips.org> 19 * macro Maciej W. Rozycki <macro@linux-mips.org>
20 * 20 *
21 * Modification History: 21 * Modification History:
22 * Date Name Description 22 * Date Name Description
23 * 16-Aug-96 LVS Created. 23 * 16-Aug-96 LVS Created.
24 * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O 24 * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O
25 * macros to DEFXX.C. 25 * macros to DEFXX.C.
26 * 12-Sep-96 LVS Removed packet request header pointers. 26 * 12-Sep-96 LVS Removed packet request header pointers.
27 * 04 Aug 2003 macro Converted to the DMA API. 27 * 04 Aug 2003 macro Converted to the DMA API.
28 * 23 Oct 2006 macro Big-endian host support.
28 */ 29 */
29 30
30 #ifndef _DEFXX_H_ 31 #ifndef _DEFXX_H_
31 #define _DEFXX_H_ 32 #define _DEFXX_H_
32 33
33 /* Define basic types for unsigned chars, shorts, longs */ 34 /* Define basic types for unsigned chars, shorts, longs */
34 35
35 typedef u8 PI_UINT8; 36 typedef u8 PI_UINT8;
36 typedef u16 PI_UINT16; 37 typedef u16 PI_UINT16;
37 typedef u32 PI_UINT32; 38 typedef u32 PI_UINT32;
38 39
39 /* Define general structures */ 40 /* Define general structures */
40 41
41 typedef struct /* 64-bit counter */ 42 typedef struct /* 64-bit counter */
42 { 43 {
43 PI_UINT32 ms; 44 PI_UINT32 ms;
44 PI_UINT32 ls; 45 PI_UINT32 ls;
45 } PI_CNTR; 46 } PI_CNTR;
46 47
47 typedef struct /* LAN address */ 48 typedef struct /* LAN address */
48 { 49 {
49 PI_UINT32 lwrd_0; 50 PI_UINT32 lwrd_0;
50 PI_UINT32 lwrd_1; 51 PI_UINT32 lwrd_1;
51 } PI_LAN_ADDR; 52 } PI_LAN_ADDR;
52 53
53 typedef struct /* Station ID address */ 54 typedef struct /* Station ID address */
54 { 55 {
55 PI_UINT32 octet_7_4; 56 PI_UINT32 octet_7_4;
56 PI_UINT32 octet_3_0; 57 PI_UINT32 octet_3_0;
57 } PI_STATION_ID; 58 } PI_STATION_ID;
58 59
59 60
60 /* Define general constants */ 61 /* Define general constants */
61 62
62 #define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */ 63 #define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */
63 #define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */ 64 #define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */
64 #define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */ 65 #define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */
65 #define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */ 66 #define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */
66 #define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */ 67 #define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */
67 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */ 68 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
68 #define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */ 69 #define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */
69 70
70 /* Define PHY index values */ 71 /* Define PHY index values */
71 72
72 #define PI_PHY_K_S 0 /* Index to S phy */ 73 #define PI_PHY_K_S 0 /* Index to S phy */
73 #define PI_PHY_K_A 0 /* Index to A phy */ 74 #define PI_PHY_K_A 0 /* Index to A phy */
74 #define PI_PHY_K_B 1 /* Index to B phy */ 75 #define PI_PHY_K_B 1 /* Index to B phy */
75 #define PI_PHY_K_MAX 2 /* Max number of phys */ 76 #define PI_PHY_K_MAX 2 /* Max number of phys */
76 77
77 /* Define FMC descriptor fields */ 78 /* Define FMC descriptor fields */
78 79
79 #define PI_FMC_DESCR_V_SOP 31 80 #define PI_FMC_DESCR_V_SOP 31
80 #define PI_FMC_DESCR_V_EOP 30 81 #define PI_FMC_DESCR_V_EOP 30
81 #define PI_FMC_DESCR_V_FSC 27 82 #define PI_FMC_DESCR_V_FSC 27
82 #define PI_FMC_DESCR_V_FSB_ERROR 26 83 #define PI_FMC_DESCR_V_FSB_ERROR 26
83 #define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25 84 #define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25
84 #define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24 85 #define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24
85 #define PI_FMC_DESCR_V_FSB 22 86 #define PI_FMC_DESCR_V_FSB 22
86 #define PI_FMC_DESCR_V_RCC_FLUSH 21 87 #define PI_FMC_DESCR_V_RCC_FLUSH 21
87 #define PI_FMC_DESCR_V_RCC_CRC 20 88 #define PI_FMC_DESCR_V_RCC_CRC 20
88 #define PI_FMC_DESCR_V_RCC_RRR 17 89 #define PI_FMC_DESCR_V_RCC_RRR 17
89 #define PI_FMC_DESCR_V_RCC_DD 15 90 #define PI_FMC_DESCR_V_RCC_DD 15
90 #define PI_FMC_DESCR_V_RCC_SS 13 91 #define PI_FMC_DESCR_V_RCC_SS 13
91 #define PI_FMC_DESCR_V_RCC 13 92 #define PI_FMC_DESCR_V_RCC 13
92 #define PI_FMC_DESCR_V_LEN 0 93 #define PI_FMC_DESCR_V_LEN 0
93 94
94 #define PI_FMC_DESCR_M_SOP 0x80000000 95 #define PI_FMC_DESCR_M_SOP 0x80000000
95 #define PI_FMC_DESCR_M_EOP 0x40000000 96 #define PI_FMC_DESCR_M_EOP 0x40000000
96 #define PI_FMC_DESCR_M_FSC 0x38000000 97 #define PI_FMC_DESCR_M_FSC 0x38000000
97 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000 98 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
98 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000 99 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
99 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000 100 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
100 #define PI_FMC_DESCR_M_FSB 0x07C00000 101 #define PI_FMC_DESCR_M_FSB 0x07C00000
101 #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000 102 #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000
102 #define PI_FMC_DESCR_M_RCC_CRC 0x00100000 103 #define PI_FMC_DESCR_M_RCC_CRC 0x00100000
103 #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000 104 #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000
104 #define PI_FMC_DESCR_M_RCC_DD 0x00018000 105 #define PI_FMC_DESCR_M_RCC_DD 0x00018000
105 #define PI_FMC_DESCR_M_RCC_SS 0x00006000 106 #define PI_FMC_DESCR_M_RCC_SS 0x00006000
106 #define PI_FMC_DESCR_M_RCC 0x003FE000 107 #define PI_FMC_DESCR_M_RCC 0x003FE000
107 #define PI_FMC_DESCR_M_LEN 0x00001FFF 108 #define PI_FMC_DESCR_M_LEN 0x00001FFF
108 109
109 #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA 110 #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA
110 111
111 #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00 112 #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00
112 #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01 113 #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01
113 #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02 114 #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02
114 #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03 115 #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03
115 #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04 116 #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04
116 #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05 117 #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05
117 #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06 118 #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06
118 #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07 119 #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07
119 120
120 #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0 121 #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0
121 #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1 122 #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1
122 #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2 123 #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2
123 #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3 124 #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3
124 125
125 #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0 126 #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0
126 #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1 127 #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1
127 #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2 128 #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2
128 #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3 129 #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3
129 130
130 /* Define some max buffer sizes */ 131 /* Define some max buffer sizes */
131 132
132 #define PI_CMD_REQ_K_SIZE_MAX 512 133 #define PI_CMD_REQ_K_SIZE_MAX 512
133 #define PI_CMD_RSP_K_SIZE_MAX 512 134 #define PI_CMD_RSP_K_SIZE_MAX 512
134 #define PI_UNSOL_K_SIZE_MAX 512 135 #define PI_UNSOL_K_SIZE_MAX 512
135 #define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */ 136 #define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */
136 #define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */ 137 #define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
137 #define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */ 138 #define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
138 139
139 /* Define adapter states */ 140 /* Define adapter states */
140 141
141 #define PI_STATE_K_RESET 0 142 #define PI_STATE_K_RESET 0
142 #define PI_STATE_K_UPGRADE 1 143 #define PI_STATE_K_UPGRADE 1
143 #define PI_STATE_K_DMA_UNAVAIL 2 144 #define PI_STATE_K_DMA_UNAVAIL 2
144 #define PI_STATE_K_DMA_AVAIL 3 145 #define PI_STATE_K_DMA_AVAIL 3
145 #define PI_STATE_K_LINK_AVAIL 4 146 #define PI_STATE_K_LINK_AVAIL 4
146 #define PI_STATE_K_LINK_UNAVAIL 5 147 #define PI_STATE_K_LINK_UNAVAIL 5
147 #define PI_STATE_K_HALTED 6 148 #define PI_STATE_K_HALTED 6
148 #define PI_STATE_K_RING_MEMBER 7 149 #define PI_STATE_K_RING_MEMBER 7
149 #define PI_STATE_K_NUMBER 8 150 #define PI_STATE_K_NUMBER 8
150 151
151 /* Define codes for command type */ 152 /* Define codes for command type */
152 153
153 #define PI_CMD_K_START 0x00 154 #define PI_CMD_K_START 0x00
154 #define PI_CMD_K_FILTERS_SET 0x01 155 #define PI_CMD_K_FILTERS_SET 0x01
155 #define PI_CMD_K_FILTERS_GET 0x02 156 #define PI_CMD_K_FILTERS_GET 0x02
156 #define PI_CMD_K_CHARS_SET 0x03 157 #define PI_CMD_K_CHARS_SET 0x03
157 #define PI_CMD_K_STATUS_CHARS_GET 0x04 158 #define PI_CMD_K_STATUS_CHARS_GET 0x04
158 #define PI_CMD_K_CNTRS_GET 0x05 159 #define PI_CMD_K_CNTRS_GET 0x05
159 #define PI_CMD_K_CNTRS_SET 0x06 160 #define PI_CMD_K_CNTRS_SET 0x06
160 #define PI_CMD_K_ADDR_FILTER_SET 0x07 161 #define PI_CMD_K_ADDR_FILTER_SET 0x07
161 #define PI_CMD_K_ADDR_FILTER_GET 0x08 162 #define PI_CMD_K_ADDR_FILTER_GET 0x08
162 #define PI_CMD_K_ERROR_LOG_CLEAR 0x09 163 #define PI_CMD_K_ERROR_LOG_CLEAR 0x09
163 #define PI_CMD_K_ERROR_LOG_GET 0x0A 164 #define PI_CMD_K_ERROR_LOG_GET 0x0A
164 #define PI_CMD_K_FDDI_MIB_GET 0x0B 165 #define PI_CMD_K_FDDI_MIB_GET 0x0B
165 #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C 166 #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C
166 #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D 167 #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D
167 #define PI_CMD_K_SNMP_SET 0x0E 168 #define PI_CMD_K_SNMP_SET 0x0E
168 #define PI_CMD_K_UNSOL_TEST 0x0F 169 #define PI_CMD_K_UNSOL_TEST 0x0F
169 #define PI_CMD_K_SMT_MIB_GET 0x10 170 #define PI_CMD_K_SMT_MIB_GET 0x10
170 #define PI_CMD_K_SMT_MIB_SET 0x11 171 #define PI_CMD_K_SMT_MIB_SET 0x11
171 #define PI_CMD_K_MAX 0x11 /* Must match last */ 172 #define PI_CMD_K_MAX 0x11 /* Must match last */
172 173
173 /* Define item codes for Chars_Set and Filters_Set commands */ 174 /* Define item codes for Chars_Set and Filters_Set commands */
174 175
175 #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */ 176 #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */
176 #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */ 177 #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */
177 #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */ 178 #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */
178 #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */ 179 #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */
179 #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */ 180 #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */
180 #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */ 181 #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */
181 #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */ 182 #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */
182 #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */ 183 #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */
183 #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */ 184 #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */
184 #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */ 185 #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */
185 #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */ 186 #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */
186 #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */ 187 #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */
187 #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */ 188 #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */
188 #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */ 189 #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */
189 #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */ 190 #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */
190 #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */ 191 #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */
191 #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */ 192 #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */
192 #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */ 193 #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */
193 #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */ 194 #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */
194 #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */ 195 #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */
195 #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */ 196 #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */
196 #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */ 197 #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */
197 #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */ 198 #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */
198 #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */ 199 #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */
199 #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */ 200 #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */
200 #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */ 201 #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */
201 #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */ 202 #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */
202 #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */ 203 #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */
203 #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */ 204 #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */
204 #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */ 205 #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */
205 #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */ 206 #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */
206 #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */ 207 #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */
207 #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */ 208 #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */
208 #define PI_ITEM_K_MAX 0x2C /* Must equal high item */ 209 #define PI_ITEM_K_MAX 0x2C /* Must equal high item */
209 210
210 /* Values for some of the items */ 211 /* Values for some of the items */
211 212
212 #define PI_K_FALSE 0 /* Generic false */ 213 #define PI_K_FALSE 0 /* Generic false */
213 #define PI_K_TRUE 1 /* Generic true */ 214 #define PI_K_TRUE 1 /* Generic true */
214 215
215 #define PI_SNMP_K_TRUE 1 /* SNMP true/false values */ 216 #define PI_SNMP_K_TRUE 1 /* SNMP true/false values */
216 #define PI_SNMP_K_FALSE 2 217 #define PI_SNMP_K_FALSE 2
217 218
218 #define PI_FSTATE_K_BLOCK 0 /* Filter State */ 219 #define PI_FSTATE_K_BLOCK 0 /* Filter State */
219 #define PI_FSTATE_K_PASS 1 220 #define PI_FSTATE_K_PASS 1
220 221
221 /* Define command return codes */ 222 /* Define command return codes */
222 223
223 #define PI_RSP_K_SUCCESS 0x00 224 #define PI_RSP_K_SUCCESS 0x00
224 #define PI_RSP_K_FAILURE 0x01 225 #define PI_RSP_K_FAILURE 0x01
225 #define PI_RSP_K_WARNING 0x02 226 #define PI_RSP_K_WARNING 0x02
226 #define PI_RSP_K_LOOP_MODE_BAD 0x03 227 #define PI_RSP_K_LOOP_MODE_BAD 0x03
227 #define PI_RSP_K_ITEM_CODE_BAD 0x04 228 #define PI_RSP_K_ITEM_CODE_BAD 0x04
228 #define PI_RSP_K_TVX_BAD 0x05 229 #define PI_RSP_K_TVX_BAD 0x05
229 #define PI_RSP_K_TREQ_BAD 0x06 230 #define PI_RSP_K_TREQ_BAD 0x06
230 #define PI_RSP_K_TOKEN_BAD 0x07 231 #define PI_RSP_K_TOKEN_BAD 0x07
231 #define PI_RSP_K_NO_EOL 0x0C 232 #define PI_RSP_K_NO_EOL 0x0C
232 #define PI_RSP_K_FILTER_STATE_BAD 0x0D 233 #define PI_RSP_K_FILTER_STATE_BAD 0x0D
233 #define PI_RSP_K_CMD_TYPE_BAD 0x0E 234 #define PI_RSP_K_CMD_TYPE_BAD 0x0E
234 #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F 235 #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F
235 #define PI_RSP_K_RING_PURGER_BAD 0x10 236 #define PI_RSP_K_RING_PURGER_BAD 0x10
236 #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11 237 #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11
237 #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12 238 #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12
238 #define PI_RSP_K_FLUSH_TIME_BAD 0x13 239 #define PI_RSP_K_FLUSH_TIME_BAD 0x13
239 #define PI_RSP_K_NOT_IMPLEMENTED 0x14 240 #define PI_RSP_K_NOT_IMPLEMENTED 0x14
240 #define PI_RSP_K_CONFIG_POLICY_BAD 0x15 241 #define PI_RSP_K_CONFIG_POLICY_BAD 0x15
241 #define PI_RSP_K_STATION_ACTION_BAD 0x16 242 #define PI_RSP_K_STATION_ACTION_BAD 0x16
242 #define PI_RSP_K_MAC_ACTION_BAD 0x17 243 #define PI_RSP_K_MAC_ACTION_BAD 0x17
243 #define PI_RSP_K_CON_POLICIES_BAD 0x18 244 #define PI_RSP_K_CON_POLICIES_BAD 0x18
244 #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19 245 #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19
245 #define PI_RSP_K_TB_MAX_BAD 0x1A 246 #define PI_RSP_K_TB_MAX_BAD 0x1A
246 #define PI_RSP_K_LER_CUTOFF_BAD 0x1B 247 #define PI_RSP_K_LER_CUTOFF_BAD 0x1B
247 #define PI_RSP_K_LER_ALARM_BAD 0x1C 248 #define PI_RSP_K_LER_ALARM_BAD 0x1C
248 #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D 249 #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D
249 #define PI_RSP_K_MAC_T_REQ_BAD 0x1E 250 #define PI_RSP_K_MAC_T_REQ_BAD 0x1E
250 #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F 251 #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F
251 #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20 252 #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20
252 #define PI_RSP_K_NO_SUCH_ENTRY 0x21 253 #define PI_RSP_K_NO_SUCH_ENTRY 0x21
253 #define PI_RSP_K_T_NOTIFY_BAD 0x22 254 #define PI_RSP_K_T_NOTIFY_BAD 0x22
254 #define PI_RSP_K_TR_MAX_EXP_BAD 0x23 255 #define PI_RSP_K_TR_MAX_EXP_BAD 0x23
255 #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24 256 #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24
256 #define PI_RSP_K_MAX_T_REQ_BAD 0x25 257 #define PI_RSP_K_MAX_T_REQ_BAD 0x25
257 #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26 258 #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26
258 #define PI_RSP_K_ITEM_INDEX_BAD 0x27 259 #define PI_RSP_K_ITEM_INDEX_BAD 0x27
259 #define PI_RSP_K_PORT_ACTION_BAD 0x28 260 #define PI_RSP_K_PORT_ACTION_BAD 0x28
260 261
261 /* Commonly used structures */ 262 /* Commonly used structures */
262 263
263 typedef struct /* Item list */ 264 typedef struct /* Item list */
264 { 265 {
265 PI_UINT32 item_code; 266 PI_UINT32 item_code;
266 PI_UINT32 value; 267 PI_UINT32 value;
267 } PI_ITEM_LIST; 268 } PI_ITEM_LIST;
268 269
269 typedef struct /* Response header */ 270 typedef struct /* Response header */
270 { 271 {
271 PI_UINT32 reserved; 272 PI_UINT32 reserved;
272 PI_UINT32 cmd_type; 273 PI_UINT32 cmd_type;
273 PI_UINT32 status; 274 PI_UINT32 status;
274 } PI_RSP_HEADER; 275 } PI_RSP_HEADER;
275 276
276 277
277 /* Start Command */ 278 /* Start Command */
278 279
279 typedef struct 280 typedef struct
280 { 281 {
281 PI_UINT32 cmd_type; 282 PI_UINT32 cmd_type;
282 } PI_CMD_START_REQ; 283 } PI_CMD_START_REQ;
283 284
284 /* Start Response */ 285 /* Start Response */
285 286
286 typedef struct 287 typedef struct
287 { 288 {
288 PI_RSP_HEADER header; 289 PI_RSP_HEADER header;
289 } PI_CMD_START_RSP; 290 } PI_CMD_START_RSP;
290 291
291 /* Filters_Set Request */ 292 /* Filters_Set Request */
292 293
293 #define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */ 294 #define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */
294 295
295 typedef struct 296 typedef struct
296 { 297 {
297 PI_UINT32 cmd_type; 298 PI_UINT32 cmd_type;
298 PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX]; 299 PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
299 } PI_CMD_FILTERS_SET_REQ; 300 } PI_CMD_FILTERS_SET_REQ;
300 301
301 /* Filters_Set Response */ 302 /* Filters_Set Response */
302 303
303 typedef struct 304 typedef struct
304 { 305 {
305 PI_RSP_HEADER header; 306 PI_RSP_HEADER header;
306 } PI_CMD_FILTERS_SET_RSP; 307 } PI_CMD_FILTERS_SET_RSP;
307 308
308 /* Filters_Get Request */ 309 /* Filters_Get Request */
309 310
310 typedef struct 311 typedef struct
311 { 312 {
312 PI_UINT32 cmd_type; 313 PI_UINT32 cmd_type;
313 } PI_CMD_FILTERS_GET_REQ; 314 } PI_CMD_FILTERS_GET_REQ;
314 315
315 /* Filters_Get Response */ 316 /* Filters_Get Response */
316 317
317 typedef struct 318 typedef struct
318 { 319 {
319 PI_RSP_HEADER header; 320 PI_RSP_HEADER header;
320 PI_UINT32 ind_group_prom; 321 PI_UINT32 ind_group_prom;
321 PI_UINT32 group_prom; 322 PI_UINT32 group_prom;
322 PI_UINT32 broadcast_all; 323 PI_UINT32 broadcast_all;
323 PI_UINT32 smt_all; 324 PI_UINT32 smt_all;
324 PI_UINT32 smt_user; 325 PI_UINT32 smt_user;
325 PI_UINT32 reserved_all; 326 PI_UINT32 reserved_all;
326 PI_UINT32 implementor_all; 327 PI_UINT32 implementor_all;
327 } PI_CMD_FILTERS_GET_RSP; 328 } PI_CMD_FILTERS_GET_RSP;
328 329
329 330
330 /* Chars_Set Request */ 331 /* Chars_Set Request */
331 332
332 #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */ 333 #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
333 334
334 typedef struct 335 typedef struct
335 { 336 {
336 PI_UINT32 cmd_type; 337 PI_UINT32 cmd_type;
337 struct /* Item list */ 338 struct /* Item list */
338 { 339 {
339 PI_UINT32 item_code; 340 PI_UINT32 item_code;
340 PI_UINT32 value; 341 PI_UINT32 value;
341 PI_UINT32 item_index; 342 PI_UINT32 item_index;
342 } item[PI_CMD_CHARS_SET_K_ITEMS_MAX]; 343 } item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
343 } PI_CMD_CHARS_SET_REQ; 344 } PI_CMD_CHARS_SET_REQ;
344 345
345 /* Chars_Set Response */ 346 /* Chars_Set Response */
346 347
347 typedef struct 348 typedef struct
348 { 349 {
349 PI_RSP_HEADER header; 350 PI_RSP_HEADER header;
350 } PI_CMD_CHARS_SET_RSP; 351 } PI_CMD_CHARS_SET_RSP;
351 352
352 353
353 /* SNMP_Set Request */ 354 /* SNMP_Set Request */
354 355
355 #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */ 356 #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
356 357
357 typedef struct 358 typedef struct
358 { 359 {
359 PI_UINT32 cmd_type; 360 PI_UINT32 cmd_type;
360 struct /* Item list */ 361 struct /* Item list */
361 { 362 {
362 PI_UINT32 item_code; 363 PI_UINT32 item_code;
363 PI_UINT32 value; 364 PI_UINT32 value;
364 PI_UINT32 item_index; 365 PI_UINT32 item_index;
365 } item[PI_CMD_SNMP_SET_K_ITEMS_MAX]; 366 } item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
366 } PI_CMD_SNMP_SET_REQ; 367 } PI_CMD_SNMP_SET_REQ;
367 368
368 /* SNMP_Set Response */ 369 /* SNMP_Set Response */
369 370
370 typedef struct 371 typedef struct
371 { 372 {
372 PI_RSP_HEADER header; 373 PI_RSP_HEADER header;
373 } PI_CMD_SNMP_SET_RSP; 374 } PI_CMD_SNMP_SET_RSP;
374 375
375 376
376 /* SMT_MIB_Set Request */ 377 /* SMT_MIB_Set Request */
377 378
378 #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */ 379 #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */
379 380
380 typedef struct 381 typedef struct
381 { 382 {
382 PI_UINT32 cmd_type; 383 PI_UINT32 cmd_type;
383 struct 384 struct
384 { 385 {
385 PI_UINT32 item_code; 386 PI_UINT32 item_code;
386 PI_UINT32 value; 387 PI_UINT32 value;
387 PI_UINT32 item_index; 388 PI_UINT32 item_index;
388 } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX]; 389 } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
389 } PI_CMD_SMT_MIB_SET_REQ; 390 } PI_CMD_SMT_MIB_SET_REQ;
390 391
391 /* SMT_MIB_Set Response */ 392 /* SMT_MIB_Set Response */
392 393
393 typedef struct 394 typedef struct
394 { 395 {
395 PI_RSP_HEADER header; 396 PI_RSP_HEADER header;
396 } PI_CMD_SMT_MIB_SET_RSP; 397 } PI_CMD_SMT_MIB_SET_RSP;
397 398
398 /* SMT_MIB_Get Request */ 399 /* SMT_MIB_Get Request */
399 400
400 typedef struct 401 typedef struct
401 { 402 {
402 PI_UINT32 cmd_type; 403 PI_UINT32 cmd_type;
403 } PI_CMD_SMT_MIB_GET_REQ; 404 } PI_CMD_SMT_MIB_GET_REQ;
404 405
405 /* SMT_MIB_Get Response */ 406 /* SMT_MIB_Get Response */
406 407
407 typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */ 408 typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */
408 { 409 {
409 PI_RSP_HEADER header; 410 PI_RSP_HEADER header;
410 411
411 /* SMT GROUP */ 412 /* SMT GROUP */
412 413
413 PI_STATION_ID smt_station_id; 414 PI_STATION_ID smt_station_id;
414 PI_UINT32 smt_op_version_id; 415 PI_UINT32 smt_op_version_id;
415 PI_UINT32 smt_hi_version_id; 416 PI_UINT32 smt_hi_version_id;
416 PI_UINT32 smt_lo_version_id; 417 PI_UINT32 smt_lo_version_id;
417 PI_UINT32 smt_user_data[8]; 418 PI_UINT32 smt_user_data[8];
418 PI_UINT32 smt_mib_version_id; 419 PI_UINT32 smt_mib_version_id;
419 PI_UINT32 smt_mac_ct; 420 PI_UINT32 smt_mac_ct;
420 PI_UINT32 smt_non_master_ct; 421 PI_UINT32 smt_non_master_ct;
421 PI_UINT32 smt_master_ct; 422 PI_UINT32 smt_master_ct;
422 PI_UINT32 smt_available_paths; 423 PI_UINT32 smt_available_paths;
423 PI_UINT32 smt_config_capabilities; 424 PI_UINT32 smt_config_capabilities;
424 PI_UINT32 smt_config_policy; 425 PI_UINT32 smt_config_policy;
425 PI_UINT32 smt_connection_policy; 426 PI_UINT32 smt_connection_policy;
426 PI_UINT32 smt_t_notify; 427 PI_UINT32 smt_t_notify;
427 PI_UINT32 smt_stat_rpt_policy; 428 PI_UINT32 smt_stat_rpt_policy;
428 PI_UINT32 smt_trace_max_expiration; 429 PI_UINT32 smt_trace_max_expiration;
429 PI_UINT32 smt_bypass_present; 430 PI_UINT32 smt_bypass_present;
430 PI_UINT32 smt_ecm_state; 431 PI_UINT32 smt_ecm_state;
431 PI_UINT32 smt_cf_state; 432 PI_UINT32 smt_cf_state;
432 PI_UINT32 smt_remote_disconnect_flag; 433 PI_UINT32 smt_remote_disconnect_flag;
433 PI_UINT32 smt_station_status; 434 PI_UINT32 smt_station_status;
434 PI_UINT32 smt_peer_wrap_flag; 435 PI_UINT32 smt_peer_wrap_flag;
435 PI_CNTR smt_msg_time_stamp; 436 PI_CNTR smt_msg_time_stamp;
436 PI_CNTR smt_transition_time_stamp; 437 PI_CNTR smt_transition_time_stamp;
437 438
438 /* MAC GROUP */ 439 /* MAC GROUP */
439 440
440 PI_UINT32 mac_frame_status_functions; 441 PI_UINT32 mac_frame_status_functions;
441 PI_UINT32 mac_t_max_capability; 442 PI_UINT32 mac_t_max_capability;
442 PI_UINT32 mac_tvx_capability; 443 PI_UINT32 mac_tvx_capability;
443 PI_UINT32 mac_available_paths; 444 PI_UINT32 mac_available_paths;
444 PI_UINT32 mac_current_path; 445 PI_UINT32 mac_current_path;
445 PI_LAN_ADDR mac_upstream_nbr; 446 PI_LAN_ADDR mac_upstream_nbr;
446 PI_LAN_ADDR mac_downstream_nbr; 447 PI_LAN_ADDR mac_downstream_nbr;
447 PI_LAN_ADDR mac_old_upstream_nbr; 448 PI_LAN_ADDR mac_old_upstream_nbr;
448 PI_LAN_ADDR mac_old_downstream_nbr; 449 PI_LAN_ADDR mac_old_downstream_nbr;
449 PI_UINT32 mac_dup_address_test; 450 PI_UINT32 mac_dup_address_test;
450 PI_UINT32 mac_requested_paths; 451 PI_UINT32 mac_requested_paths;
451 PI_UINT32 mac_downstream_port_type; 452 PI_UINT32 mac_downstream_port_type;
452 PI_LAN_ADDR mac_smt_address; 453 PI_LAN_ADDR mac_smt_address;
453 PI_UINT32 mac_t_req; 454 PI_UINT32 mac_t_req;
454 PI_UINT32 mac_t_neg; 455 PI_UINT32 mac_t_neg;
455 PI_UINT32 mac_t_max; 456 PI_UINT32 mac_t_max;
456 PI_UINT32 mac_tvx_value; 457 PI_UINT32 mac_tvx_value;
457 PI_UINT32 mac_frame_error_threshold; 458 PI_UINT32 mac_frame_error_threshold;
458 PI_UINT32 mac_frame_error_ratio; 459 PI_UINT32 mac_frame_error_ratio;
459 PI_UINT32 mac_rmt_state; 460 PI_UINT32 mac_rmt_state;
460 PI_UINT32 mac_da_flag; 461 PI_UINT32 mac_da_flag;
461 PI_UINT32 mac_unda_flag; 462 PI_UINT32 mac_unda_flag;
462 PI_UINT32 mac_frame_error_flag; 463 PI_UINT32 mac_frame_error_flag;
463 PI_UINT32 mac_ma_unitdata_available; 464 PI_UINT32 mac_ma_unitdata_available;
464 PI_UINT32 mac_hardware_present; 465 PI_UINT32 mac_hardware_present;
465 PI_UINT32 mac_ma_unitdata_enable; 466 PI_UINT32 mac_ma_unitdata_enable;
466 467
467 /* PATH GROUP */ 468 /* PATH GROUP */
468 469
469 PI_UINT32 path_configuration[8]; 470 PI_UINT32 path_configuration[8];
470 PI_UINT32 path_tvx_lower_bound; 471 PI_UINT32 path_tvx_lower_bound;
471 PI_UINT32 path_t_max_lower_bound; 472 PI_UINT32 path_t_max_lower_bound;
472 PI_UINT32 path_max_t_req; 473 PI_UINT32 path_max_t_req;
473 474
474 /* PORT GROUP */ 475 /* PORT GROUP */
475 476
476 PI_UINT32 port_my_type[PI_PHY_K_MAX]; 477 PI_UINT32 port_my_type[PI_PHY_K_MAX];
477 PI_UINT32 port_neighbor_type[PI_PHY_K_MAX]; 478 PI_UINT32 port_neighbor_type[PI_PHY_K_MAX];
478 PI_UINT32 port_connection_policies[PI_PHY_K_MAX]; 479 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
479 PI_UINT32 port_mac_indicated[PI_PHY_K_MAX]; 480 PI_UINT32 port_mac_indicated[PI_PHY_K_MAX];
480 PI_UINT32 port_current_path[PI_PHY_K_MAX]; 481 PI_UINT32 port_current_path[PI_PHY_K_MAX];
481 PI_UINT32 port_requested_paths[PI_PHY_K_MAX]; 482 PI_UINT32 port_requested_paths[PI_PHY_K_MAX];
482 PI_UINT32 port_mac_placement[PI_PHY_K_MAX]; 483 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
483 PI_UINT32 port_available_paths[PI_PHY_K_MAX]; 484 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
484 PI_UINT32 port_pmd_class[PI_PHY_K_MAX]; 485 PI_UINT32 port_pmd_class[PI_PHY_K_MAX];
485 PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX]; 486 PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX];
486 PI_UINT32 port_bs_flag[PI_PHY_K_MAX]; 487 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
487 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX]; 488 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
488 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX]; 489 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
489 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX]; 490 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
490 PI_UINT32 port_connect_state[PI_PHY_K_MAX]; 491 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
491 PI_UINT32 port_pcm_state[PI_PHY_K_MAX]; 492 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
492 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX]; 493 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
493 PI_UINT32 port_ler_flag[PI_PHY_K_MAX]; 494 PI_UINT32 port_ler_flag[PI_PHY_K_MAX];
494 PI_UINT32 port_hardware_present[PI_PHY_K_MAX]; 495 PI_UINT32 port_hardware_present[PI_PHY_K_MAX];
495 496
496 /* GROUP for things that were added later, so must be at the end. */ 497 /* GROUP for things that were added later, so must be at the end. */
497 498
498 PI_CNTR path_ring_latency; 499 PI_CNTR path_ring_latency;
499 500
500 } PI_CMD_SMT_MIB_GET_RSP; 501 } PI_CMD_SMT_MIB_GET_RSP;
501 502
502 503
503 /* 504 /*
504 * Item and group code definitions for SMT 7.3 mandatory objects. These 505 * Item and group code definitions for SMT 7.3 mandatory objects. These
505 * definitions are to be used as appropriate in SMT_MIB_SET commands and 506 * definitions are to be used as appropriate in SMT_MIB_SET commands and
506 * certain host-sent SMT frames such as PMF Get and Set requests. The 507 * certain host-sent SMT frames such as PMF Get and Set requests. The
507 * codes have been taken from the MIB summary section of ANSI SMT 7.3. 508 * codes have been taken from the MIB summary section of ANSI SMT 7.3.
508 */ 509 */
509 510
510 #define PI_GRP_K_SMT_STATION_ID 0x100A 511 #define PI_GRP_K_SMT_STATION_ID 0x100A
511 #define PI_ITEM_K_SMT_STATION_ID 0x100B 512 #define PI_ITEM_K_SMT_STATION_ID 0x100B
512 #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D 513 #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D
513 #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E 514 #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E
514 #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F 515 #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F
515 #define PI_ITEM_K_SMT_USER_DATA 0x1011 516 #define PI_ITEM_K_SMT_USER_DATA 0x1011
516 #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012 517 #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012
517 518
518 #define PI_GRP_K_SMT_STATION_CONFIG 0x1014 519 #define PI_GRP_K_SMT_STATION_CONFIG 0x1014
519 #define PI_ITEM_K_SMT_MAC_CT 0x1015 520 #define PI_ITEM_K_SMT_MAC_CT 0x1015
520 #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016 521 #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016
521 #define PI_ITEM_K_SMT_MASTER_CT 0x1017 522 #define PI_ITEM_K_SMT_MASTER_CT 0x1017
522 #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018 523 #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018
523 #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019 524 #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019
524 #define PI_ITEM_K_SMT_CONFIG_POL 0x101A 525 #define PI_ITEM_K_SMT_CONFIG_POL 0x101A
525 #define PI_ITEM_K_SMT_CONN_POL 0x101B 526 #define PI_ITEM_K_SMT_CONN_POL 0x101B
526 #define PI_ITEM_K_SMT_T_NOTIFY 0x101D 527 #define PI_ITEM_K_SMT_T_NOTIFY 0x101D
527 #define PI_ITEM_K_SMT_STAT_POL 0x101E 528 #define PI_ITEM_K_SMT_STAT_POL 0x101E
528 #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F 529 #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F
529 #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020 530 #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020
530 #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021 531 #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021
531 #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022 532 #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022
532 533
533 #define PI_GRP_K_SMT_STATUS 0x1028 534 #define PI_GRP_K_SMT_STATUS 0x1028
534 #define PI_ITEM_K_SMT_ECM_STATE 0x1029 535 #define PI_ITEM_K_SMT_ECM_STATE 0x1029
535 #define PI_ITEM_K_SMT_CF_STATE 0x102A 536 #define PI_ITEM_K_SMT_CF_STATE 0x102A
536 #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C 537 #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C
537 #define PI_ITEM_K_SMT_STATION_STATUS 0x102D 538 #define PI_ITEM_K_SMT_STATION_STATUS 0x102D
538 #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E 539 #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E
539 540
540 #define PI_GRP_K_SMT_MIB_OPERATION 0x1032 541 #define PI_GRP_K_SMT_MIB_OPERATION 0x1032
541 #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033 542 #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033
542 #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034 543 #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034
543 544
544 #define PI_ITEM_K_SMT_STATION_ACT 0x103C 545 #define PI_ITEM_K_SMT_STATION_ACT 0x103C
545 546
546 #define PI_GRP_K_MAC_CAPABILITIES 0x200A 547 #define PI_GRP_K_MAC_CAPABILITIES 0x200A
547 #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B 548 #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B
548 #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D 549 #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D
549 #define PI_ITEM_K_MAC_TVX_CAP 0x200E 550 #define PI_ITEM_K_MAC_TVX_CAP 0x200E
550 551
551 #define PI_GRP_K_MAC_CONFIG 0x2014 552 #define PI_GRP_K_MAC_CONFIG 0x2014
552 #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016 553 #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016
553 #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017 554 #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017
554 #define PI_ITEM_K_MAC_UP_NBR 0x2018 555 #define PI_ITEM_K_MAC_UP_NBR 0x2018
555 #define PI_ITEM_K_MAC_DOWN_NBR 0x2019 556 #define PI_ITEM_K_MAC_DOWN_NBR 0x2019
556 #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A 557 #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A
557 #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B 558 #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B
558 #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D 559 #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D
559 #define PI_ITEM_K_MAC_REQ_PATHS 0x2020 560 #define PI_ITEM_K_MAC_REQ_PATHS 0x2020
560 #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021 561 #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021
561 #define PI_ITEM_K_MAC_INDEX 0x2022 562 #define PI_ITEM_K_MAC_INDEX 0x2022
562 563
563 #define PI_GRP_K_MAC_ADDRESS 0x2028 564 #define PI_GRP_K_MAC_ADDRESS 0x2028
564 #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029 565 #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029
565 566
566 #define PI_GRP_K_MAC_OPERATION 0x2032 567 #define PI_GRP_K_MAC_OPERATION 0x2032
567 #define PI_ITEM_K_MAC_TREQ 0x2033 568 #define PI_ITEM_K_MAC_TREQ 0x2033
568 #define PI_ITEM_K_MAC_TNEG 0x2034 569 #define PI_ITEM_K_MAC_TNEG 0x2034
569 #define PI_ITEM_K_MAC_TMAX 0x2035 570 #define PI_ITEM_K_MAC_TMAX 0x2035
570 #define PI_ITEM_K_MAC_TVX_VALUE 0x2036 571 #define PI_ITEM_K_MAC_TVX_VALUE 0x2036
571 572
572 #define PI_GRP_K_MAC_COUNTERS 0x2046 573 #define PI_GRP_K_MAC_COUNTERS 0x2046
573 #define PI_ITEM_K_MAC_FRAME_CT 0x2047 574 #define PI_ITEM_K_MAC_FRAME_CT 0x2047
574 #define PI_ITEM_K_MAC_COPIED_CT 0x2048 575 #define PI_ITEM_K_MAC_COPIED_CT 0x2048
575 #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049 576 #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049
576 #define PI_ITEM_K_MAC_ERROR_CT 0x2051 577 #define PI_ITEM_K_MAC_ERROR_CT 0x2051
577 #define PI_ITEM_K_MAC_LOST_CT 0x2052 578 #define PI_ITEM_K_MAC_LOST_CT 0x2052
578 579
579 #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A 580 #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A
580 #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F 581 #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F
581 #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060 582 #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060
582 583
583 #define PI_GRP_K_MAC_STATUS 0x206E 584 #define PI_GRP_K_MAC_STATUS 0x206E
584 #define PI_ITEM_K_MAC_RMT_STATE 0x206F 585 #define PI_ITEM_K_MAC_RMT_STATE 0x206F
585 #define PI_ITEM_K_MAC_DA_FLAG 0x2070 586 #define PI_ITEM_K_MAC_DA_FLAG 0x2070
586 #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071 587 #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071
587 #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072 588 #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072
588 #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074 589 #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074
589 #define PI_ITEM_K_MAC_HW_PRESENT 0x2075 590 #define PI_ITEM_K_MAC_HW_PRESENT 0x2075
590 #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076 591 #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076
591 592
592 #define PI_GRP_K_PATH_CONFIG 0x320A 593 #define PI_GRP_K_PATH_CONFIG 0x320A
593 #define PI_ITEM_K_PATH_INDEX 0x320B 594 #define PI_ITEM_K_PATH_INDEX 0x320B
594 #define PI_ITEM_K_PATH_CONFIGURATION 0x3212 595 #define PI_ITEM_K_PATH_CONFIGURATION 0x3212
595 #define PI_ITEM_K_PATH_TVX_LB 0x3215 596 #define PI_ITEM_K_PATH_TVX_LB 0x3215
596 #define PI_ITEM_K_PATH_T_MAX_LB 0x3216 597 #define PI_ITEM_K_PATH_T_MAX_LB 0x3216
597 #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217 598 #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217
598 599
599 #define PI_GRP_K_PORT_CONFIG 0x400A 600 #define PI_GRP_K_PORT_CONFIG 0x400A
600 #define PI_ITEM_K_PORT_MY_TYPE 0x400C 601 #define PI_ITEM_K_PORT_MY_TYPE 0x400C
601 #define PI_ITEM_K_PORT_NBR_TYPE 0x400D 602 #define PI_ITEM_K_PORT_NBR_TYPE 0x400D
602 #define PI_ITEM_K_PORT_CONN_POLS 0x400E 603 #define PI_ITEM_K_PORT_CONN_POLS 0x400E
603 #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F 604 #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F
604 #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010 605 #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010
605 #define PI_ITEM_K_PORT_REQ_PATHS 0x4011 606 #define PI_ITEM_K_PORT_REQ_PATHS 0x4011
606 #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012 607 #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012
607 #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013 608 #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013
608 #define PI_ITEM_K_PORT_PMD_CLASS 0x4016 609 #define PI_ITEM_K_PORT_PMD_CLASS 0x4016
609 #define PI_ITEM_K_PORT_CONN_CAPS 0x4017 610 #define PI_ITEM_K_PORT_CONN_CAPS 0x4017
610 #define PI_ITEM_K_PORT_INDEX 0x401D 611 #define PI_ITEM_K_PORT_INDEX 0x401D
611 612
612 #define PI_GRP_K_PORT_OPERATION 0x401E 613 #define PI_GRP_K_PORT_OPERATION 0x401E
613 #define PI_ITEM_K_PORT_BS_FLAG 0x4021 614 #define PI_ITEM_K_PORT_BS_FLAG 0x4021
614 615
615 #define PI_GRP_K_PORT_ERR_CNTRS 0x4028 616 #define PI_GRP_K_PORT_ERR_CNTRS 0x4028
616 #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A 617 #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A
617 618
618 #define PI_GRP_K_PORT_LER 0x4032 619 #define PI_GRP_K_PORT_LER 0x4032
619 #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033 620 #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033
620 #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034 621 #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034
621 #define PI_ITEM_K_PORT_LEM_CT 0x4035 622 #define PI_ITEM_K_PORT_LEM_CT 0x4035
622 #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A 623 #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A
623 #define PI_ITEM_K_PORT_LER_ALARM 0x403B 624 #define PI_ITEM_K_PORT_LER_ALARM 0x403B
624 625
625 #define PI_GRP_K_PORT_STATUS 0x403C 626 #define PI_GRP_K_PORT_STATUS 0x403C
626 #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D 627 #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D
627 #define PI_ITEM_K_PORT_PCM_STATE 0x403E 628 #define PI_ITEM_K_PORT_PCM_STATE 0x403E
628 #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F 629 #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F
629 #define PI_ITEM_K_PORT_LER_FLAG 0x4040 630 #define PI_ITEM_K_PORT_LER_FLAG 0x4040
630 #define PI_ITEM_K_PORT_HW_PRESENT 0x4041 631 #define PI_ITEM_K_PORT_HW_PRESENT 0x4041
631 632
632 #define PI_ITEM_K_PORT_ACT 0x4046 633 #define PI_ITEM_K_PORT_ACT 0x4046
633 634
634 /* Addr_Filter_Set Request */ 635 /* Addr_Filter_Set Request */
635 636
636 #define PI_CMD_ADDR_FILTER_K_SIZE 62 637 #define PI_CMD_ADDR_FILTER_K_SIZE 62
637 638
638 typedef struct 639 typedef struct
639 { 640 {
640 PI_UINT32 cmd_type; 641 PI_UINT32 cmd_type;
641 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE]; 642 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
642 } PI_CMD_ADDR_FILTER_SET_REQ; 643 } PI_CMD_ADDR_FILTER_SET_REQ;
643 644
644 /* Addr_Filter_Set Response */ 645 /* Addr_Filter_Set Response */
645 646
646 typedef struct 647 typedef struct
647 { 648 {
648 PI_RSP_HEADER header; 649 PI_RSP_HEADER header;
649 } PI_CMD_ADDR_FILTER_SET_RSP; 650 } PI_CMD_ADDR_FILTER_SET_RSP;
650 651
651 /* Addr_Filter_Get Request */ 652 /* Addr_Filter_Get Request */
652 653
653 typedef struct 654 typedef struct
654 { 655 {
655 PI_UINT32 cmd_type; 656 PI_UINT32 cmd_type;
656 } PI_CMD_ADDR_FILTER_GET_REQ; 657 } PI_CMD_ADDR_FILTER_GET_REQ;
657 658
658 /* Addr_Filter_Get Response */ 659 /* Addr_Filter_Get Response */
659 660
660 typedef struct 661 typedef struct
661 { 662 {
662 PI_RSP_HEADER header; 663 PI_RSP_HEADER header;
663 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE]; 664 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
664 } PI_CMD_ADDR_FILTER_GET_RSP; 665 } PI_CMD_ADDR_FILTER_GET_RSP;
665 666
666 /* Status_Chars_Get Request */ 667 /* Status_Chars_Get Request */
667 668
668 typedef struct 669 typedef struct
669 { 670 {
670 PI_UINT32 cmd_type; 671 PI_UINT32 cmd_type;
671 } PI_CMD_STATUS_CHARS_GET_REQ; 672 } PI_CMD_STATUS_CHARS_GET_REQ;
672 673
673 /* Status_Chars_Get Response */ 674 /* Status_Chars_Get Response */
674 675
675 typedef struct 676 typedef struct
676 { 677 {
677 PI_RSP_HEADER header; 678 PI_RSP_HEADER header;
678 PI_STATION_ID station_id; /* Station */ 679 PI_STATION_ID station_id; /* Station */
679 PI_UINT32 station_type; 680 PI_UINT32 station_type;
680 PI_UINT32 smt_ver_id; 681 PI_UINT32 smt_ver_id;
681 PI_UINT32 smt_ver_id_max; 682 PI_UINT32 smt_ver_id_max;
682 PI_UINT32 smt_ver_id_min; 683 PI_UINT32 smt_ver_id_min;
683 PI_UINT32 station_state; 684 PI_UINT32 station_state;
684 PI_LAN_ADDR link_addr; /* Link */ 685 PI_LAN_ADDR link_addr; /* Link */
685 PI_UINT32 t_req; 686 PI_UINT32 t_req;
686 PI_UINT32 tvx; 687 PI_UINT32 tvx;
687 PI_UINT32 token_timeout; 688 PI_UINT32 token_timeout;
688 PI_UINT32 purger_enb; 689 PI_UINT32 purger_enb;
689 PI_UINT32 link_state; 690 PI_UINT32 link_state;
690 PI_UINT32 tneg; 691 PI_UINT32 tneg;
691 PI_UINT32 dup_addr_flag; 692 PI_UINT32 dup_addr_flag;
692 PI_LAN_ADDR una; 693 PI_LAN_ADDR una;
693 PI_LAN_ADDR una_old; 694 PI_LAN_ADDR una_old;
694 PI_UINT32 un_dup_addr_flag; 695 PI_UINT32 un_dup_addr_flag;
695 PI_LAN_ADDR dna; 696 PI_LAN_ADDR dna;
696 PI_LAN_ADDR dna_old; 697 PI_LAN_ADDR dna_old;
697 PI_UINT32 purger_state; 698 PI_UINT32 purger_state;
698 PI_UINT32 fci_mode; 699 PI_UINT32 fci_mode;
699 PI_UINT32 error_reason; 700 PI_UINT32 error_reason;
700 PI_UINT32 loopback; 701 PI_UINT32 loopback;
701 PI_UINT32 ring_latency; 702 PI_UINT32 ring_latency;
702 PI_LAN_ADDR last_dir_beacon_sa; 703 PI_LAN_ADDR last_dir_beacon_sa;
703 PI_LAN_ADDR last_dir_beacon_una; 704 PI_LAN_ADDR last_dir_beacon_una;
704 PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */ 705 PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */
705 PI_UINT32 pmd_type[PI_PHY_K_MAX]; 706 PI_UINT32 pmd_type[PI_PHY_K_MAX];
706 PI_UINT32 lem_threshold[PI_PHY_K_MAX]; 707 PI_UINT32 lem_threshold[PI_PHY_K_MAX];
707 PI_UINT32 phy_state[PI_PHY_K_MAX]; 708 PI_UINT32 phy_state[PI_PHY_K_MAX];
708 PI_UINT32 nbor_phy_type[PI_PHY_K_MAX]; 709 PI_UINT32 nbor_phy_type[PI_PHY_K_MAX];
709 PI_UINT32 link_error_est[PI_PHY_K_MAX]; 710 PI_UINT32 link_error_est[PI_PHY_K_MAX];
710 PI_UINT32 broken_reason[PI_PHY_K_MAX]; 711 PI_UINT32 broken_reason[PI_PHY_K_MAX];
711 PI_UINT32 reject_reason[PI_PHY_K_MAX]; 712 PI_UINT32 reject_reason[PI_PHY_K_MAX];
712 PI_UINT32 cntr_interval; /* Miscellaneous */ 713 PI_UINT32 cntr_interval; /* Miscellaneous */
713 PI_UINT32 module_rev; 714 PI_UINT32 module_rev;
714 PI_UINT32 firmware_rev; 715 PI_UINT32 firmware_rev;
715 PI_UINT32 mop_device_type; 716 PI_UINT32 mop_device_type;
716 PI_UINT32 phy_led[PI_PHY_K_MAX]; 717 PI_UINT32 phy_led[PI_PHY_K_MAX];
717 PI_UINT32 flush_time; 718 PI_UINT32 flush_time;
718 } PI_CMD_STATUS_CHARS_GET_RSP; 719 } PI_CMD_STATUS_CHARS_GET_RSP;
719 720
720 /* FDDI_MIB_Get Request */ 721 /* FDDI_MIB_Get Request */
721 722
722 typedef struct 723 typedef struct
723 { 724 {
724 PI_UINT32 cmd_type; 725 PI_UINT32 cmd_type;
725 } PI_CMD_FDDI_MIB_GET_REQ; 726 } PI_CMD_FDDI_MIB_GET_REQ;
726 727
727 /* FDDI_MIB_Get Response */ 728 /* FDDI_MIB_Get Response */
728 729
729 typedef struct 730 typedef struct
730 { 731 {
731 PI_RSP_HEADER header; 732 PI_RSP_HEADER header;
732 733
733 /* SMT GROUP */ 734 /* SMT GROUP */
734 735
735 PI_STATION_ID smt_station_id; 736 PI_STATION_ID smt_station_id;
736 PI_UINT32 smt_op_version_id; 737 PI_UINT32 smt_op_version_id;
737 PI_UINT32 smt_hi_version_id; 738 PI_UINT32 smt_hi_version_id;
738 PI_UINT32 smt_lo_version_id; 739 PI_UINT32 smt_lo_version_id;
739 PI_UINT32 smt_mac_ct; 740 PI_UINT32 smt_mac_ct;
740 PI_UINT32 smt_non_master_ct; 741 PI_UINT32 smt_non_master_ct;
741 PI_UINT32 smt_master_ct; 742 PI_UINT32 smt_master_ct;
742 PI_UINT32 smt_paths_available; 743 PI_UINT32 smt_paths_available;
743 PI_UINT32 smt_config_capabilities; 744 PI_UINT32 smt_config_capabilities;
744 PI_UINT32 smt_config_policy; 745 PI_UINT32 smt_config_policy;
745 PI_UINT32 smt_connection_policy; 746 PI_UINT32 smt_connection_policy;
746 PI_UINT32 smt_t_notify; 747 PI_UINT32 smt_t_notify;
747 PI_UINT32 smt_status_reporting; 748 PI_UINT32 smt_status_reporting;
748 PI_UINT32 smt_ecm_state; 749 PI_UINT32 smt_ecm_state;
749 PI_UINT32 smt_cf_state; 750 PI_UINT32 smt_cf_state;
750 PI_UINT32 smt_hold_state; 751 PI_UINT32 smt_hold_state;
751 PI_UINT32 smt_remote_disconnect_flag; 752 PI_UINT32 smt_remote_disconnect_flag;
752 PI_UINT32 smt_station_action; 753 PI_UINT32 smt_station_action;
753 754
754 /* MAC GROUP */ 755 /* MAC GROUP */
755 756
756 PI_UINT32 mac_frame_status_capabilities; 757 PI_UINT32 mac_frame_status_capabilities;
757 PI_UINT32 mac_t_max_greatest_lower_bound; 758 PI_UINT32 mac_t_max_greatest_lower_bound;
758 PI_UINT32 mac_tvx_greatest_lower_bound; 759 PI_UINT32 mac_tvx_greatest_lower_bound;
759 PI_UINT32 mac_paths_available; 760 PI_UINT32 mac_paths_available;
760 PI_UINT32 mac_current_path; 761 PI_UINT32 mac_current_path;
761 PI_LAN_ADDR mac_upstream_nbr; 762 PI_LAN_ADDR mac_upstream_nbr;
762 PI_LAN_ADDR mac_old_upstream_nbr; 763 PI_LAN_ADDR mac_old_upstream_nbr;
763 PI_UINT32 mac_dup_addr_test; 764 PI_UINT32 mac_dup_addr_test;
764 PI_UINT32 mac_paths_requested; 765 PI_UINT32 mac_paths_requested;
765 PI_UINT32 mac_downstream_port_type; 766 PI_UINT32 mac_downstream_port_type;
766 PI_LAN_ADDR mac_smt_address; 767 PI_LAN_ADDR mac_smt_address;
767 PI_UINT32 mac_t_req; 768 PI_UINT32 mac_t_req;
768 PI_UINT32 mac_t_neg; 769 PI_UINT32 mac_t_neg;
769 PI_UINT32 mac_t_max; 770 PI_UINT32 mac_t_max;
770 PI_UINT32 mac_tvx_value; 771 PI_UINT32 mac_tvx_value;
771 PI_UINT32 mac_t_min; 772 PI_UINT32 mac_t_min;
772 PI_UINT32 mac_current_frame_status; 773 PI_UINT32 mac_current_frame_status;
773 /* mac_frame_cts */ 774 /* mac_frame_cts */
774 /* mac_error_cts */ 775 /* mac_error_cts */
775 /* mac_lost_cts */ 776 /* mac_lost_cts */
776 PI_UINT32 mac_frame_error_threshold; 777 PI_UINT32 mac_frame_error_threshold;
777 PI_UINT32 mac_frame_error_ratio; 778 PI_UINT32 mac_frame_error_ratio;
778 PI_UINT32 mac_rmt_state; 779 PI_UINT32 mac_rmt_state;
779 PI_UINT32 mac_da_flag; 780 PI_UINT32 mac_da_flag;
780 PI_UINT32 mac_una_da_flag; 781 PI_UINT32 mac_una_da_flag;
781 PI_UINT32 mac_frame_condition; 782 PI_UINT32 mac_frame_condition;
782 PI_UINT32 mac_chip_set; 783 PI_UINT32 mac_chip_set;
783 PI_UINT32 mac_action; 784 PI_UINT32 mac_action;
784 785
785 /* PATH GROUP => Does not need to be implemented */ 786 /* PATH GROUP => Does not need to be implemented */
786 787
787 /* PORT GROUP */ 788 /* PORT GROUP */
788 789
789 PI_UINT32 port_pc_type[PI_PHY_K_MAX]; 790 PI_UINT32 port_pc_type[PI_PHY_K_MAX];
790 PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX]; 791 PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX];
791 PI_UINT32 port_connection_policies[PI_PHY_K_MAX]; 792 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
792 PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX]; 793 PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX];
793 PI_UINT32 port_ce_state[PI_PHY_K_MAX]; 794 PI_UINT32 port_ce_state[PI_PHY_K_MAX];
794 PI_UINT32 port_paths_requested[PI_PHY_K_MAX]; 795 PI_UINT32 port_paths_requested[PI_PHY_K_MAX];
795 PI_UINT32 port_mac_placement[PI_PHY_K_MAX]; 796 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
796 PI_UINT32 port_available_paths[PI_PHY_K_MAX]; 797 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
797 PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX]; 798 PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX];
798 PI_UINT32 port_tb_max[PI_PHY_K_MAX]; 799 PI_UINT32 port_tb_max[PI_PHY_K_MAX];
799 PI_UINT32 port_bs_flag[PI_PHY_K_MAX]; 800 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
800 /* port_lct_fail_cts[PI_PHY_K_MAX]; */ 801 /* port_lct_fail_cts[PI_PHY_K_MAX]; */
801 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX]; 802 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
802 /* port_lem_reject_cts[PI_PHY_K_MAX]; */ 803 /* port_lem_reject_cts[PI_PHY_K_MAX]; */
803 /* port_lem_cts[PI_PHY_K_MAX]; */ 804 /* port_lem_cts[PI_PHY_K_MAX]; */
804 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX]; 805 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
805 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX]; 806 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
806 PI_UINT32 port_connect_state[PI_PHY_K_MAX]; 807 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
807 PI_UINT32 port_pcm_state[PI_PHY_K_MAX]; 808 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
808 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX]; 809 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
809 PI_UINT32 port_ler_condition[PI_PHY_K_MAX]; 810 PI_UINT32 port_ler_condition[PI_PHY_K_MAX];
810 PI_UINT32 port_chip_set[PI_PHY_K_MAX]; 811 PI_UINT32 port_chip_set[PI_PHY_K_MAX];
811 PI_UINT32 port_action[PI_PHY_K_MAX]; 812 PI_UINT32 port_action[PI_PHY_K_MAX];
812 813
813 /* ATTACHMENT GROUP */ 814 /* ATTACHMENT GROUP */
814 815
815 PI_UINT32 attachment_class; 816 PI_UINT32 attachment_class;
816 PI_UINT32 attachment_ob_present; 817 PI_UINT32 attachment_ob_present;
817 PI_UINT32 attachment_imax_expiration; 818 PI_UINT32 attachment_imax_expiration;
818 PI_UINT32 attachment_inserted_status; 819 PI_UINT32 attachment_inserted_status;
819 PI_UINT32 attachment_insert_policy; 820 PI_UINT32 attachment_insert_policy;
820 821
821 /* CHIP SET GROUP => Does not need to be implemented */ 822 /* CHIP SET GROUP => Does not need to be implemented */
822 823
823 } PI_CMD_FDDI_MIB_GET_RSP; 824 } PI_CMD_FDDI_MIB_GET_RSP;
824 825
825 /* DEC_Ext_MIB_Get Request */ 826 /* DEC_Ext_MIB_Get Request */
826 827
827 typedef struct 828 typedef struct
828 { 829 {
829 PI_UINT32 cmd_type; 830 PI_UINT32 cmd_type;
830 } PI_CMD_DEC_EXT_MIB_GET_REQ; 831 } PI_CMD_DEC_EXT_MIB_GET_REQ;
831 832
832 /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */ 833 /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
833 834
834 typedef struct 835 typedef struct
835 { 836 {
836 PI_RSP_HEADER header; 837 PI_RSP_HEADER header;
837 838
838 /* SMT GROUP */ 839 /* SMT GROUP */
839 840
840 PI_UINT32 esmt_station_type; 841 PI_UINT32 esmt_station_type;
841 842
842 /* MAC GROUP */ 843 /* MAC GROUP */
843 844
844 PI_UINT32 emac_link_state; 845 PI_UINT32 emac_link_state;
845 PI_UINT32 emac_ring_purger_state; 846 PI_UINT32 emac_ring_purger_state;
846 PI_UINT32 emac_ring_purger_enable; 847 PI_UINT32 emac_ring_purger_enable;
847 PI_UINT32 emac_frame_strip_mode; 848 PI_UINT32 emac_frame_strip_mode;
848 PI_UINT32 emac_ring_error_reason; 849 PI_UINT32 emac_ring_error_reason;
849 PI_UINT32 emac_up_nbr_dup_addr_flag; 850 PI_UINT32 emac_up_nbr_dup_addr_flag;
850 PI_UINT32 emac_restricted_token_timeout; 851 PI_UINT32 emac_restricted_token_timeout;
851 852
852 /* PORT GROUP */ 853 /* PORT GROUP */
853 854
854 PI_UINT32 eport_pmd_type[PI_PHY_K_MAX]; 855 PI_UINT32 eport_pmd_type[PI_PHY_K_MAX];
855 PI_UINT32 eport_phy_state[PI_PHY_K_MAX]; 856 PI_UINT32 eport_phy_state[PI_PHY_K_MAX];
856 PI_UINT32 eport_reject_reason[PI_PHY_K_MAX]; 857 PI_UINT32 eport_reject_reason[PI_PHY_K_MAX];
857 858
858 /* FDX (Full-Duplex) GROUP */ 859 /* FDX (Full-Duplex) GROUP */
859 860
860 PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */ 861 PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */
861 PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */ 862 PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */
862 PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */ 863 PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */
863 864
864 } PI_CMD_DEC_EXT_MIB_GET_RSP; 865 } PI_CMD_DEC_EXT_MIB_GET_RSP;
865 866
866 typedef struct 867 typedef struct
867 { 868 {
868 PI_CNTR traces_rcvd; /* Station */ 869 PI_CNTR traces_rcvd; /* Station */
869 PI_CNTR frame_cnt; /* Link */ 870 PI_CNTR frame_cnt; /* Link */
870 PI_CNTR error_cnt; 871 PI_CNTR error_cnt;
871 PI_CNTR lost_cnt; 872 PI_CNTR lost_cnt;
872 PI_CNTR octets_rcvd; 873 PI_CNTR octets_rcvd;
873 PI_CNTR octets_sent; 874 PI_CNTR octets_sent;
874 PI_CNTR pdus_rcvd; 875 PI_CNTR pdus_rcvd;
875 PI_CNTR pdus_sent; 876 PI_CNTR pdus_sent;
876 PI_CNTR mcast_octets_rcvd; 877 PI_CNTR mcast_octets_rcvd;
877 PI_CNTR mcast_octets_sent; 878 PI_CNTR mcast_octets_sent;
878 PI_CNTR mcast_pdus_rcvd; 879 PI_CNTR mcast_pdus_rcvd;
879 PI_CNTR mcast_pdus_sent; 880 PI_CNTR mcast_pdus_sent;
880 PI_CNTR xmt_underruns; 881 PI_CNTR xmt_underruns;
881 PI_CNTR xmt_failures; 882 PI_CNTR xmt_failures;
882 PI_CNTR block_check_errors; 883 PI_CNTR block_check_errors;
883 PI_CNTR frame_status_errors; 884 PI_CNTR frame_status_errors;
884 PI_CNTR pdu_length_errors; 885 PI_CNTR pdu_length_errors;
885 PI_CNTR rcv_overruns; 886 PI_CNTR rcv_overruns;
886 PI_CNTR user_buff_unavailable; 887 PI_CNTR user_buff_unavailable;
887 PI_CNTR inits_initiated; 888 PI_CNTR inits_initiated;
888 PI_CNTR inits_rcvd; 889 PI_CNTR inits_rcvd;
889 PI_CNTR beacons_initiated; 890 PI_CNTR beacons_initiated;
890 PI_CNTR dup_addrs; 891 PI_CNTR dup_addrs;
891 PI_CNTR dup_tokens; 892 PI_CNTR dup_tokens;
892 PI_CNTR purge_errors; 893 PI_CNTR purge_errors;
893 PI_CNTR fci_strip_errors; 894 PI_CNTR fci_strip_errors;
894 PI_CNTR traces_initiated; 895 PI_CNTR traces_initiated;
895 PI_CNTR directed_beacons_rcvd; 896 PI_CNTR directed_beacons_rcvd;
896 PI_CNTR emac_frame_alignment_errors; 897 PI_CNTR emac_frame_alignment_errors;
897 PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */ 898 PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */
898 PI_CNTR lct_rejects[PI_PHY_K_MAX]; 899 PI_CNTR lct_rejects[PI_PHY_K_MAX];
899 PI_CNTR lem_rejects[PI_PHY_K_MAX]; 900 PI_CNTR lem_rejects[PI_PHY_K_MAX];
900 PI_CNTR link_errors[PI_PHY_K_MAX]; 901 PI_CNTR link_errors[PI_PHY_K_MAX];
901 PI_CNTR connections[PI_PHY_K_MAX]; 902 PI_CNTR connections[PI_PHY_K_MAX];
902 PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */ 903 PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */
903 PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */ 904 PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */
904 PI_CNTR tokens; 905 PI_CNTR tokens;
905 } PI_CNTR_BLK; 906 } PI_CNTR_BLK;
906 907
907 /* Counters_Get Request */ 908 /* Counters_Get Request */
908 909
909 typedef struct 910 typedef struct
910 { 911 {
911 PI_UINT32 cmd_type; 912 PI_UINT32 cmd_type;
912 } PI_CMD_CNTRS_GET_REQ; 913 } PI_CMD_CNTRS_GET_REQ;
913 914
914 /* Counters_Get Response */ 915 /* Counters_Get Response */
915 916
916 typedef struct 917 typedef struct
917 { 918 {
918 PI_RSP_HEADER header; 919 PI_RSP_HEADER header;
919 PI_CNTR time_since_reset; 920 PI_CNTR time_since_reset;
920 PI_CNTR_BLK cntrs; 921 PI_CNTR_BLK cntrs;
921 } PI_CMD_CNTRS_GET_RSP; 922 } PI_CMD_CNTRS_GET_RSP;
922 923
923 /* Counters_Set Request */ 924 /* Counters_Set Request */
924 925
925 typedef struct 926 typedef struct
926 { 927 {
927 PI_UINT32 cmd_type; 928 PI_UINT32 cmd_type;
928 PI_CNTR_BLK cntrs; 929 PI_CNTR_BLK cntrs;
929 } PI_CMD_CNTRS_SET_REQ; 930 } PI_CMD_CNTRS_SET_REQ;
930 931
931 /* Counters_Set Response */ 932 /* Counters_Set Response */
932 933
933 typedef struct 934 typedef struct
934 { 935 {
935 PI_RSP_HEADER header; 936 PI_RSP_HEADER header;
936 } PI_CMD_CNTRS_SET_RSP; 937 } PI_CMD_CNTRS_SET_RSP;
937 938
938 /* Error_Log_Clear Request */ 939 /* Error_Log_Clear Request */
939 940
940 typedef struct 941 typedef struct
941 { 942 {
942 PI_UINT32 cmd_type; 943 PI_UINT32 cmd_type;
943 } PI_CMD_ERROR_LOG_CLEAR_REQ; 944 } PI_CMD_ERROR_LOG_CLEAR_REQ;
944 945
945 /* Error_Log_Clear Response */ 946 /* Error_Log_Clear Response */
946 947
947 typedef struct 948 typedef struct
948 { 949 {
949 PI_RSP_HEADER header; 950 PI_RSP_HEADER header;
950 } PI_CMD_ERROR_LOG_CLEAR_RSP; 951 } PI_CMD_ERROR_LOG_CLEAR_RSP;
951 952
952 /* Error_Log_Get Request */ 953 /* Error_Log_Get Request */
953 954
954 #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */ 955 #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */
955 956
956 typedef struct 957 typedef struct
957 { 958 {
958 PI_UINT32 cmd_type; 959 PI_UINT32 cmd_type;
959 PI_UINT32 entry_index; 960 PI_UINT32 entry_index;
960 } PI_CMD_ERROR_LOG_GET_REQ; 961 } PI_CMD_ERROR_LOG_GET_REQ;
961 962
962 /* Error_Log_Get Response */ 963 /* Error_Log_Get Response */
963 964
964 #define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */ 965 #define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */
965 #define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */ 966 #define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */
966 967
967 typedef struct 968 typedef struct
968 { 969 {
969 struct 970 struct
970 { 971 {
971 PI_UINT32 fru_imp_mask; 972 PI_UINT32 fru_imp_mask;
972 PI_UINT32 test_id; 973 PI_UINT32 test_id;
973 PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE]; 974 PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE];
974 } diag; 975 } diag;
975 PI_UINT32 fw[PI_K_LOG_FW_SIZE]; 976 PI_UINT32 fw[PI_K_LOG_FW_SIZE];
976 } PI_LOG_ENTRY; 977 } PI_LOG_ENTRY;
977 978
978 typedef struct 979 typedef struct
979 { 980 {
980 PI_RSP_HEADER header; 981 PI_RSP_HEADER header;
981 PI_UINT32 event_status; 982 PI_UINT32 event_status;
982 PI_UINT32 caller_id; 983 PI_UINT32 caller_id;
983 PI_UINT32 timestamp_l; 984 PI_UINT32 timestamp_l;
984 PI_UINT32 timestamp_h; 985 PI_UINT32 timestamp_h;
985 PI_UINT32 write_count; 986 PI_UINT32 write_count;
986 PI_LOG_ENTRY entry_info; 987 PI_LOG_ENTRY entry_info;
987 } PI_CMD_ERROR_LOG_GET_RSP; 988 } PI_CMD_ERROR_LOG_GET_RSP;
988 989
989 /* Define error log related constants and types. */ 990 /* Define error log related constants and types. */
990 /* Not all of the caller id's can occur. The only ones currently */ 991 /* Not all of the caller id's can occur. The only ones currently */
991 /* implemented are: none, selftest, mfg, fw, console */ 992 /* implemented are: none, selftest, mfg, fw, console */
992 993
993 #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */ 994 #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */
994 #define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */ 995 #define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */
995 #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */ 996 #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */
996 #define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */ 997 #define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */
997 #define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */ 998 #define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */
998 #define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */ 999 #define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */
999 #define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */ 1000 #define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */
1000 #define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */ 1001 #define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */
1001 #define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */ 1002 #define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */
1002 #define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */ 1003 #define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */
1003 #define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */ 1004 #define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */
1004 1005
1005 /* 1006 /*
1006 * Place all DMA commands in the following request and response structures 1007 * Place all DMA commands in the following request and response structures
1007 * to simplify code. 1008 * to simplify code.
1008 */ 1009 */
1009 1010
1010 typedef union 1011 typedef union
1011 { 1012 {
1012 PI_UINT32 cmd_type; 1013 PI_UINT32 cmd_type;
1013 PI_CMD_START_REQ start; 1014 PI_CMD_START_REQ start;
1014 PI_CMD_FILTERS_SET_REQ filter_set; 1015 PI_CMD_FILTERS_SET_REQ filter_set;
1015 PI_CMD_FILTERS_GET_REQ filter_get; 1016 PI_CMD_FILTERS_GET_REQ filter_get;
1016 PI_CMD_CHARS_SET_REQ char_set; 1017 PI_CMD_CHARS_SET_REQ char_set;
1017 PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set; 1018 PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set;
1018 PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get; 1019 PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get;
1019 PI_CMD_STATUS_CHARS_GET_REQ stat_char_get; 1020 PI_CMD_STATUS_CHARS_GET_REQ stat_char_get;
1020 PI_CMD_CNTRS_GET_REQ cntrs_get; 1021 PI_CMD_CNTRS_GET_REQ cntrs_get;
1021 PI_CMD_CNTRS_SET_REQ cntrs_set; 1022 PI_CMD_CNTRS_SET_REQ cntrs_set;
1022 PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear; 1023 PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear;
1023 PI_CMD_ERROR_LOG_GET_REQ error_log_read; 1024 PI_CMD_ERROR_LOG_GET_REQ error_log_read;
1024 PI_CMD_SNMP_SET_REQ snmp_set; 1025 PI_CMD_SNMP_SET_REQ snmp_set;
1025 PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get; 1026 PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get;
1026 PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get; 1027 PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get;
1027 PI_CMD_SMT_MIB_SET_REQ smt_mib_set; 1028 PI_CMD_SMT_MIB_SET_REQ smt_mib_set;
1028 PI_CMD_SMT_MIB_GET_REQ smt_mib_get; 1029 PI_CMD_SMT_MIB_GET_REQ smt_mib_get;
1029 char pad[PI_CMD_REQ_K_SIZE_MAX]; 1030 char pad[PI_CMD_REQ_K_SIZE_MAX];
1030 } PI_DMA_CMD_REQ; 1031 } PI_DMA_CMD_REQ;
1031 1032
1032 typedef union 1033 typedef union
1033 { 1034 {
1034 PI_RSP_HEADER header; 1035 PI_RSP_HEADER header;
1035 PI_CMD_START_RSP start; 1036 PI_CMD_START_RSP start;
1036 PI_CMD_FILTERS_SET_RSP filter_set; 1037 PI_CMD_FILTERS_SET_RSP filter_set;
1037 PI_CMD_FILTERS_GET_RSP filter_get; 1038 PI_CMD_FILTERS_GET_RSP filter_get;
1038 PI_CMD_CHARS_SET_RSP char_set; 1039 PI_CMD_CHARS_SET_RSP char_set;
1039 PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set; 1040 PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set;
1040 PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get; 1041 PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get;
1041 PI_CMD_STATUS_CHARS_GET_RSP stat_char_get; 1042 PI_CMD_STATUS_CHARS_GET_RSP stat_char_get;
1042 PI_CMD_CNTRS_GET_RSP cntrs_get; 1043 PI_CMD_CNTRS_GET_RSP cntrs_get;
1043 PI_CMD_CNTRS_SET_RSP cntrs_set; 1044 PI_CMD_CNTRS_SET_RSP cntrs_set;
1044 PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear; 1045 PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear;
1045 PI_CMD_ERROR_LOG_GET_RSP error_log_get; 1046 PI_CMD_ERROR_LOG_GET_RSP error_log_get;
1046 PI_CMD_SNMP_SET_RSP snmp_set; 1047 PI_CMD_SNMP_SET_RSP snmp_set;
1047 PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get; 1048 PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get;
1048 PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get; 1049 PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get;
1049 PI_CMD_SMT_MIB_SET_RSP smt_mib_set; 1050 PI_CMD_SMT_MIB_SET_RSP smt_mib_set;
1050 PI_CMD_SMT_MIB_GET_RSP smt_mib_get; 1051 PI_CMD_SMT_MIB_GET_RSP smt_mib_get;
1051 char pad[PI_CMD_RSP_K_SIZE_MAX]; 1052 char pad[PI_CMD_RSP_K_SIZE_MAX];
1052 } PI_DMA_CMD_RSP; 1053 } PI_DMA_CMD_RSP;
1053 1054
1054 typedef union 1055 typedef union
1055 { 1056 {
1056 PI_DMA_CMD_REQ request; 1057 PI_DMA_CMD_REQ request;
1057 PI_DMA_CMD_RSP response; 1058 PI_DMA_CMD_RSP response;
1058 } PI_DMA_CMD_BUFFER; 1059 } PI_DMA_CMD_BUFFER;
1059 1060
1060 1061
1061 /* Define format of Consumer Block (resident in host memory) */ 1062 /* Define format of Consumer Block (resident in host memory) */
1062 1063
1063 typedef struct 1064 typedef struct
1064 { 1065 {
1065 volatile PI_UINT32 xmt_rcv_data; 1066 volatile PI_UINT32 xmt_rcv_data;
1066 volatile PI_UINT32 reserved_1; 1067 volatile PI_UINT32 reserved_1;
1067 volatile PI_UINT32 smt_host; 1068 volatile PI_UINT32 smt_host;
1068 volatile PI_UINT32 reserved_2; 1069 volatile PI_UINT32 reserved_2;
1069 volatile PI_UINT32 unsol; 1070 volatile PI_UINT32 unsol;
1070 volatile PI_UINT32 reserved_3; 1071 volatile PI_UINT32 reserved_3;
1071 volatile PI_UINT32 cmd_rsp; 1072 volatile PI_UINT32 cmd_rsp;
1072 volatile PI_UINT32 reserved_4; 1073 volatile PI_UINT32 reserved_4;
1073 volatile PI_UINT32 cmd_req; 1074 volatile PI_UINT32 cmd_req;
1074 volatile PI_UINT32 reserved_5; 1075 volatile PI_UINT32 reserved_5;
1075 } PI_CONSUMER_BLOCK; 1076 } PI_CONSUMER_BLOCK;
1076 1077
1077 #define PI_CONS_M_RCV_INDEX 0x000000FF 1078 #define PI_CONS_M_RCV_INDEX 0x000000FF
1078 #define PI_CONS_M_XMT_INDEX 0x00FF0000 1079 #define PI_CONS_M_XMT_INDEX 0x00FF0000
1079 #define PI_CONS_V_RCV_INDEX 0 1080 #define PI_CONS_V_RCV_INDEX 0
1080 #define PI_CONS_V_XMT_INDEX 16 1081 #define PI_CONS_V_XMT_INDEX 16
1081 1082
1082 /* Offsets into consumer block */ 1083 /* Offsets into consumer block */
1083 1084
1084 #define PI_CONS_BLK_K_XMT_RCV 0x00 1085 #define PI_CONS_BLK_K_XMT_RCV 0x00
1085 #define PI_CONS_BLK_K_SMT_HOST 0x08 1086 #define PI_CONS_BLK_K_SMT_HOST 0x08
1086 #define PI_CONS_BLK_K_UNSOL 0x10 1087 #define PI_CONS_BLK_K_UNSOL 0x10
1087 #define PI_CONS_BLK_K_CMD_RSP 0x18 1088 #define PI_CONS_BLK_K_CMD_RSP 0x18
1088 #define PI_CONS_BLK_K_CMD_REQ 0x20 1089 #define PI_CONS_BLK_K_CMD_REQ 0x20
1089 1090
1090 /* Offsets into descriptor block */ 1091 /* Offsets into descriptor block */
1091 1092
1092 #define PI_DESCR_BLK_K_RCV_DATA 0x0000 1093 #define PI_DESCR_BLK_K_RCV_DATA 0x0000
1093 #define PI_DESCR_BLK_K_XMT_DATA 0x0800 1094 #define PI_DESCR_BLK_K_XMT_DATA 0x0800
1094 #define PI_DESCR_BLK_K_SMT_HOST 0x1000 1095 #define PI_DESCR_BLK_K_SMT_HOST 0x1000
1095 #define PI_DESCR_BLK_K_UNSOL 0x1200 1096 #define PI_DESCR_BLK_K_UNSOL 0x1200
1096 #define PI_DESCR_BLK_K_CMD_RSP 0x1280 1097 #define PI_DESCR_BLK_K_CMD_RSP 0x1280
1097 #define PI_DESCR_BLK_K_CMD_REQ 0x1300 1098 #define PI_DESCR_BLK_K_CMD_REQ 0x1300
1098 1099
1099 /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */ 1100 /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */
1100 /* Note a field has been added for later versions of the PDQ to allow for */ 1101 /* Note a field has been added for later versions of the PDQ to allow for */
1101 /* finer granularity of the rcv buffer alignment. For backwards */ 1102 /* finer granularity of the rcv buffer alignment. For backwards */
1102 /* compatibility, the two bits (which allow the rcv buffer to be longword */ 1103 /* compatibility, the two bits (which allow the rcv buffer to be longword */
1103 /* aligned) have been added at the MBZ bits. To support previous drivers, */ 1104 /* aligned) have been added at the MBZ bits. To support previous drivers, */
1104 /* the MBZ definition is left intact. */ 1105 /* the MBZ definition is left intact. */
1105 1106
1106 typedef struct 1107 typedef struct
1107 { 1108 {
1108 PI_UINT32 long_0; 1109 PI_UINT32 long_0;
1109 PI_UINT32 long_1; 1110 PI_UINT32 long_1;
1110 } PI_RCV_DESCR; 1111 } PI_RCV_DESCR;
1111 1112
1112 #define PI_RCV_DESCR_M_SOP 0x80000000 1113 #define PI_RCV_DESCR_M_SOP 0x80000000
1113 #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000 1114 #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000
1114 #define PI_RCV_DESCR_M_MBZ 0x60000000 1115 #define PI_RCV_DESCR_M_MBZ 0x60000000
1115 #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000 1116 #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000
1116 #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000 1117 #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000
1117 #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000 1118 #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000
1118 #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF 1119 #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF
1119 1120
1120 #define PI_RCV_DESCR_V_SOP 31 1121 #define PI_RCV_DESCR_V_SOP 31
1121 #define PI_RCV_DESCR_V_SEG_LEN_LO 29 1122 #define PI_RCV_DESCR_V_SEG_LEN_LO 29
1122 #define PI_RCV_DESCR_V_MBZ 29 1123 #define PI_RCV_DESCR_V_MBZ 29
1123 #define PI_RCV_DESCR_V_SEG_LEN 23 1124 #define PI_RCV_DESCR_V_SEG_LEN 23
1124 #define PI_RCV_DESCR_V_SEG_LEN_HI 20 1125 #define PI_RCV_DESCR_V_SEG_LEN_HI 20
1125 #define PI_RCV_DESCR_V_SEG_CNT 16 1126 #define PI_RCV_DESCR_V_SEG_CNT 16
1126 #define PI_RCV_DESCR_V_BUFF_HI 0 1127 #define PI_RCV_DESCR_V_BUFF_HI 0
1127 1128
1128 /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */ 1129 /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1129 1130
1130 typedef struct 1131 typedef struct
1131 { 1132 {
1132 PI_UINT32 long_0; 1133 PI_UINT32 long_0;
1133 PI_UINT32 long_1; 1134 PI_UINT32 long_1;
1134 } PI_XMT_DESCR; 1135 } PI_XMT_DESCR;
1135 1136
1136 #define PI_XMT_DESCR_M_SOP 0x80000000 1137 #define PI_XMT_DESCR_M_SOP 0x80000000
1137 #define PI_XMT_DESCR_M_EOP 0x40000000 1138 #define PI_XMT_DESCR_M_EOP 0x40000000
1138 #define PI_XMT_DESCR_M_MBZ 0x20000000 1139 #define PI_XMT_DESCR_M_MBZ 0x20000000
1139 #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000 1140 #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000
1140 #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF 1141 #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF
1141 1142
1142 #define PI_XMT_DESCR_V_SOP 31 1143 #define PI_XMT_DESCR_V_SOP 31
1143 #define PI_XMT_DESCR_V_EOP 30 1144 #define PI_XMT_DESCR_V_EOP 30
1144 #define PI_XMT_DESCR_V_MBZ 29 1145 #define PI_XMT_DESCR_V_MBZ 29
1145 #define PI_XMT_DESCR_V_SEG_LEN 16 1146 #define PI_XMT_DESCR_V_SEG_LEN 16
1146 #define PI_XMT_DESCR_V_BUFF_HI 0 1147 #define PI_XMT_DESCR_V_BUFF_HI 0
1147 1148
1148 /* Define format of the Descriptor Block (resident in host memory) */ 1149 /* Define format of the Descriptor Block (resident in host memory) */
1149 1150
1150 #define PI_RCV_DATA_K_NUM_ENTRIES 256 1151 #define PI_RCV_DATA_K_NUM_ENTRIES 256
1151 #define PI_XMT_DATA_K_NUM_ENTRIES 256 1152 #define PI_XMT_DATA_K_NUM_ENTRIES 256
1152 #define PI_SMT_HOST_K_NUM_ENTRIES 64 1153 #define PI_SMT_HOST_K_NUM_ENTRIES 64
1153 #define PI_UNSOL_K_NUM_ENTRIES 16 1154 #define PI_UNSOL_K_NUM_ENTRIES 16
1154 #define PI_CMD_RSP_K_NUM_ENTRIES 16 1155 #define PI_CMD_RSP_K_NUM_ENTRIES 16
1155 #define PI_CMD_REQ_K_NUM_ENTRIES 16 1156 #define PI_CMD_REQ_K_NUM_ENTRIES 16
1156 1157
1157 typedef struct 1158 typedef struct
1158 { 1159 {
1159 PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES]; 1160 PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1160 PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES]; 1161 PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1161 PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES]; 1162 PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1162 PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES]; 1163 PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES];
1163 PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES]; 1164 PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1164 PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES]; 1165 PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1165 } PI_DESCR_BLOCK; 1166 } PI_DESCR_BLOCK;
1166 1167
1167 /* Define Port Registers - offsets from PDQ Base address */ 1168 /* Define Port Registers - offsets from PDQ Base address */
1168 1169
1169 #define PI_PDQ_K_REG_PORT_RESET 0x00000000 1170 #define PI_PDQ_K_REG_PORT_RESET 0x00000000
1170 #define PI_PDQ_K_REG_HOST_DATA 0x00000004 1171 #define PI_PDQ_K_REG_HOST_DATA 0x00000004
1171 #define PI_PDQ_K_REG_PORT_CTRL 0x00000008 1172 #define PI_PDQ_K_REG_PORT_CTRL 0x00000008
1172 #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C 1173 #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C
1173 #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010 1174 #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010
1174 #define PI_PDQ_K_REG_PORT_STATUS 0x00000014 1175 #define PI_PDQ_K_REG_PORT_STATUS 0x00000014
1175 #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018 1176 #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018
1176 #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C 1177 #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C
1177 #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020 1178 #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020
1178 #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024 1179 #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024
1179 #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028 1180 #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028
1180 #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C 1181 #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C
1181 #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030 1182 #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030
1182 #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034 1183 #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034
1183 1184
1184 /* Port Control Register - Command codes for primary commands */ 1185 /* Port Control Register - Command codes for primary commands */
1185 1186
1186 #define PI_PCTRL_M_CMD_ERROR 0x8000 1187 #define PI_PCTRL_M_CMD_ERROR 0x8000
1187 #define PI_PCTRL_M_BLAST_FLASH 0x4000 1188 #define PI_PCTRL_M_BLAST_FLASH 0x4000
1188 #define PI_PCTRL_M_HALT 0x2000 1189 #define PI_PCTRL_M_HALT 0x2000
1189 #define PI_PCTRL_M_COPY_DATA 0x1000 1190 #define PI_PCTRL_M_COPY_DATA 0x1000
1190 #define PI_PCTRL_M_ERROR_LOG_START 0x0800 1191 #define PI_PCTRL_M_ERROR_LOG_START 0x0800
1191 #define PI_PCTRL_M_ERROR_LOG_READ 0x0400 1192 #define PI_PCTRL_M_ERROR_LOG_READ 0x0400
1192 #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200 1193 #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200
1193 #define PI_PCTRL_M_INIT 0x0100 1194 #define PI_PCTRL_M_INIT 0x0100
1194 #define PI_PCTRL_M_INIT_START 0x0080 1195 #define PI_PCTRL_M_INIT_START 0x0080
1195 #define PI_PCTRL_M_CONS_BLOCK 0x0040 1196 #define PI_PCTRL_M_CONS_BLOCK 0x0040
1196 #define PI_PCTRL_M_UNINIT 0x0020 1197 #define PI_PCTRL_M_UNINIT 0x0020
1197 #define PI_PCTRL_M_RING_MEMBER 0x0010 1198 #define PI_PCTRL_M_RING_MEMBER 0x0010
1198 #define PI_PCTRL_M_MLA 0x0008 1199 #define PI_PCTRL_M_MLA 0x0008
1199 #define PI_PCTRL_M_FW_REV_READ 0x0004 1200 #define PI_PCTRL_M_FW_REV_READ 0x0004
1200 #define PI_PCTRL_M_DEV_SPECIFIC 0x0002 1201 #define PI_PCTRL_M_DEV_SPECIFIC 0x0002
1201 #define PI_PCTRL_M_SUB_CMD 0x0001 1202 #define PI_PCTRL_M_SUB_CMD 0x0001
1202 1203
1203 /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */ 1204 /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1204 1205
1205 #define PI_SUB_CMD_K_LINK_UNINIT 0x0001 1206 #define PI_SUB_CMD_K_LINK_UNINIT 0x0001
1206 #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002 1207 #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002
1207 #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004 1208 #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004
1208 #define PI_SUB_CMD_K_HW_REV_GET 0x0008 1209 #define PI_SUB_CMD_K_HW_REV_GET 0x0008
1209 1210
1210 /* Define some Port Data B values */ 1211 /* Define some Port Data B values */
1211 1212
1212 #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */ 1213 #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */
1213 #define PI_PDATA_B_DMA_BURST_SIZE_8 1 1214 #define PI_PDATA_B_DMA_BURST_SIZE_8 1
1214 #define PI_PDATA_B_DMA_BURST_SIZE_16 2 1215 #define PI_PDATA_B_DMA_BURST_SIZE_16 2
1215 #define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */ 1216 #define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */
1216 #define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16 1217 #define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16
1217 1218
1218 /* Port Data A Reset state */ 1219 /* Port Data A Reset state */
1219 1220
1220 #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001 1221 #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001
1221 #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002 1222 #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002
1222 #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004 1223 #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004
1223 1224
1224 /* Read adapter MLA address port control command constants */ 1225 /* Read adapter MLA address port control command constants */
1225 1226
1226 #define PI_PDATA_A_MLA_K_LO 0 1227 #define PI_PDATA_A_MLA_K_LO 0
1227 #define PI_PDATA_A_MLA_K_HI 1 1228 #define PI_PDATA_A_MLA_K_HI 1
1228 1229
1229 /* Byte Swap values for init command */ 1230 /* Byte Swap values for init command */
1230 1231
1231 #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000 1232 #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000
1232 #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC 1233 #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC
1233 #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002 1234 #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002
1234 #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001 1235 #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001
1235 1236
1236 #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13 1237 #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13
1237 #define PI_PDATA_A_INIT_V_RESERVED 3 1238 #define PI_PDATA_A_INIT_V_RESERVED 3
1238 #define PI_PDATA_A_INIT_V_BSWAP_DATA 1 1239 #define PI_PDATA_A_INIT_V_BSWAP_DATA 1
1239 #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0 1240 #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0
1240 1241
1241 /* Port Reset Register */ 1242 /* Port Reset Register */
1242 1243
1243 #define PI_RESET_M_ASSERT_RESET 1 1244 #define PI_RESET_M_ASSERT_RESET 1
1244 1245
1245 /* Port Status register */ 1246 /* Port Status register */
1246 1247
1247 #define PI_PSTATUS_V_RCV_DATA_PENDING 31 1248 #define PI_PSTATUS_V_RCV_DATA_PENDING 31
1248 #define PI_PSTATUS_V_XMT_DATA_PENDING 30 1249 #define PI_PSTATUS_V_XMT_DATA_PENDING 30
1249 #define PI_PSTATUS_V_SMT_HOST_PENDING 29 1250 #define PI_PSTATUS_V_SMT_HOST_PENDING 29
1250 #define PI_PSTATUS_V_UNSOL_PENDING 28 1251 #define PI_PSTATUS_V_UNSOL_PENDING 28
1251 #define PI_PSTATUS_V_CMD_RSP_PENDING 27 1252 #define PI_PSTATUS_V_CMD_RSP_PENDING 27
1252 #define PI_PSTATUS_V_CMD_REQ_PENDING 26 1253 #define PI_PSTATUS_V_CMD_REQ_PENDING 26
1253 #define PI_PSTATUS_V_TYPE_0_PENDING 25 1254 #define PI_PSTATUS_V_TYPE_0_PENDING 25
1254 #define PI_PSTATUS_V_RESERVED_1 16 1255 #define PI_PSTATUS_V_RESERVED_1 16
1255 #define PI_PSTATUS_V_RESERVED_2 11 1256 #define PI_PSTATUS_V_RESERVED_2 11
1256 #define PI_PSTATUS_V_STATE 8 1257 #define PI_PSTATUS_V_STATE 8
1257 #define PI_PSTATUS_V_HALT_ID 0 1258 #define PI_PSTATUS_V_HALT_ID 0
1258 1259
1259 #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000 1260 #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000
1260 #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000 1261 #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000
1261 #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000 1262 #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000
1262 #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000 1263 #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000
1263 #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000 1264 #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000
1264 #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000 1265 #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000
1265 #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000 1266 #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000
1266 #define PI_PSTATUS_M_RESERVED_1 0x01FF0000 1267 #define PI_PSTATUS_M_RESERVED_1 0x01FF0000
1267 #define PI_PSTATUS_M_RESERVED_2 0x0000F800 1268 #define PI_PSTATUS_M_RESERVED_2 0x0000F800
1268 #define PI_PSTATUS_M_STATE 0x00000700 1269 #define PI_PSTATUS_M_STATE 0x00000700
1269 #define PI_PSTATUS_M_HALT_ID 0x000000FF 1270 #define PI_PSTATUS_M_HALT_ID 0x000000FF
1270 1271
1271 /* Define Halt Id's */ 1272 /* Define Halt Id's */
1272 /* Do not insert into this list, only append. */ 1273 /* Do not insert into this list, only append. */
1273 1274
1274 #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0 1275 #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0
1275 #define PI_HALT_ID_K_PARITY_ERROR 1 1276 #define PI_HALT_ID_K_PARITY_ERROR 1
1276 #define PI_HALT_ID_K_HOST_DIR_HALT 2 1277 #define PI_HALT_ID_K_HOST_DIR_HALT 2
1277 #define PI_HALT_ID_K_SW_FAULT 3 1278 #define PI_HALT_ID_K_SW_FAULT 3
1278 #define PI_HALT_ID_K_HW_FAULT 4 1279 #define PI_HALT_ID_K_HW_FAULT 4
1279 #define PI_HALT_ID_K_PC_TRACE 5 1280 #define PI_HALT_ID_K_PC_TRACE 5
1280 #define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */ 1281 #define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */
1281 #define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */ 1282 #define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */
1282 #define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */ 1283 #define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */
1283 1284
1284 /* Host Interrupt Enable Register as seen by host */ 1285 /* Host Interrupt Enable Register as seen by host */
1285 1286
1286 #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */ 1287 #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */
1287 #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000 1288 #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000
1288 #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */ 1289 #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */
1289 #define PI_HOST_INT_M_UNSOL_ENB 0x20000000 1290 #define PI_HOST_INT_M_UNSOL_ENB 0x20000000
1290 #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000 1291 #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000
1291 #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000 1292 #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000
1292 #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000 1293 #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000
1293 #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */ 1294 #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */
1294 #define PI_HOST_INT_M_1MS 0x00000080 1295 #define PI_HOST_INT_M_1MS 0x00000080
1295 #define PI_HOST_INT_M_20MS 0x00000040 1296 #define PI_HOST_INT_M_20MS 0x00000040
1296 #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020 1297 #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020
1297 #define PI_HOST_INT_M_STATE_CHANGE 0x00000010 1298 #define PI_HOST_INT_M_STATE_CHANGE 0x00000010
1298 #define PI_HOST_INT_M_XMT_FLUSH 0x00000008 1299 #define PI_HOST_INT_M_XMT_FLUSH 0x00000008
1299 #define PI_HOST_INT_M_NXM 0x00000004 1300 #define PI_HOST_INT_M_NXM 0x00000004
1300 #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002 1301 #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002
1301 #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001 1302 #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001
1302 1303
1303 #define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */ 1304 #define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */
1304 #define PI_HOST_INT_V_RCV_DATA_ENB 30 1305 #define PI_HOST_INT_V_RCV_DATA_ENB 30
1305 #define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */ 1306 #define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */
1306 #define PI_HOST_INT_V_UNSOL_ENB 28 1307 #define PI_HOST_INT_V_UNSOL_ENB 28
1307 #define PI_HOST_INT_V_CMD_RSP_ENB 27 1308 #define PI_HOST_INT_V_CMD_RSP_ENB 27
1308 #define PI_HOST_INT_V_CMD_REQ_ENB 26 1309 #define PI_HOST_INT_V_CMD_REQ_ENB 26
1309 #define PI_HOST_INT_V_TYPE_1_RESERVED 16 1310 #define PI_HOST_INT_V_TYPE_1_RESERVED 16
1310 #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */ 1311 #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */
1311 #define PI_HOST_INT_V_1MS_ENB 7 1312 #define PI_HOST_INT_V_1MS_ENB 7
1312 #define PI_HOST_INT_V_20MS_ENB 6 1313 #define PI_HOST_INT_V_20MS_ENB 6
1313 #define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5 1314 #define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5
1314 #define PI_HOST_INT_V_STATE_CHANGE_ENB 4 1315 #define PI_HOST_INT_V_STATE_CHANGE_ENB 4
1315 #define PI_HOST_INT_V_XMT_FLUSH_ENB 3 1316 #define PI_HOST_INT_V_XMT_FLUSH_ENB 3
1316 #define PI_HOST_INT_V_NXM_ENB 2 1317 #define PI_HOST_INT_V_NXM_ENB 2
1317 #define PI_HOST_INT_V_PM_PAR_ERR_ENB 1 1318 #define PI_HOST_INT_V_PM_PAR_ERR_ENB 1
1318 #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0 1319 #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0
1319 1320
1320 #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF 1321 #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF
1321 #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000 1322 #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000
1322 #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF 1323 #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF
1323 #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F 1324 #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F
1324 1325
1325 /* Type 0 Interrupt Status Register */ 1326 /* Type 0 Interrupt Status Register */
1326 1327
1327 #define PI_TYPE_0_STAT_M_1MS 0x00000080 1328 #define PI_TYPE_0_STAT_M_1MS 0x00000080
1328 #define PI_TYPE_0_STAT_M_20MS 0x00000040 1329 #define PI_TYPE_0_STAT_M_20MS 0x00000040
1329 #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020 1330 #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020
1330 #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010 1331 #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010
1331 #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008 1332 #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008
1332 #define PI_TYPE_0_STAT_M_NXM 0x00000004 1333 #define PI_TYPE_0_STAT_M_NXM 0x00000004
1333 #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002 1334 #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002
1334 #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001 1335 #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001
1335 1336
1336 #define PI_TYPE_0_STAT_V_1MS 7 1337 #define PI_TYPE_0_STAT_V_1MS 7
1337 #define PI_TYPE_0_STAT_V_20MS 6 1338 #define PI_TYPE_0_STAT_V_20MS 6
1338 #define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5 1339 #define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5
1339 #define PI_TYPE_0_STAT_V_STATE_CHANGE 4 1340 #define PI_TYPE_0_STAT_V_STATE_CHANGE 4
1340 #define PI_TYPE_0_STAT_V_XMT_FLUSH 3 1341 #define PI_TYPE_0_STAT_V_XMT_FLUSH 3
1341 #define PI_TYPE_0_STAT_V_NXM 2 1342 #define PI_TYPE_0_STAT_V_NXM 2
1342 #define PI_TYPE_0_STAT_V_PM_PAR_ERR 1 1343 #define PI_TYPE_0_STAT_V_PM_PAR_ERR 1
1343 #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0 1344 #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0
1344 1345
1345 /* Register definition structures are defined for both big and little endian systems */ 1346 /* Register definition structures are defined for both big and little endian systems */
1346 1347
1347 #ifndef BIG_ENDIAN 1348 #ifndef __BIG_ENDIAN
1348 1349
1349 /* Little endian format of Type 1 Producer register */ 1350 /* Little endian format of Type 1 Producer register */
1350 1351
1351 typedef union 1352 typedef union
1352 { 1353 {
1353 PI_UINT32 lword; 1354 PI_UINT32 lword;
1354 struct 1355 struct
1355 { 1356 {
1356 PI_UINT8 prod; 1357 PI_UINT8 prod;
1357 PI_UINT8 comp; 1358 PI_UINT8 comp;
1358 PI_UINT8 mbz_1; 1359 PI_UINT8 mbz_1;
1359 PI_UINT8 mbz_2; 1360 PI_UINT8 mbz_2;
1360 } index; 1361 } index;
1361 } PI_TYPE_1_PROD_REG; 1362 } PI_TYPE_1_PROD_REG;
1362 1363
1363 /* Little endian format of Type 2 Producer register */ 1364 /* Little endian format of Type 2 Producer register */
1364 1365
1365 typedef union 1366 typedef union
1366 { 1367 {
1367 PI_UINT32 lword; 1368 PI_UINT32 lword;
1368 struct 1369 struct
1369 { 1370 {
1370 PI_UINT8 rcv_prod; 1371 PI_UINT8 rcv_prod;
1371 PI_UINT8 xmt_prod; 1372 PI_UINT8 xmt_prod;
1372 PI_UINT8 rcv_comp; 1373 PI_UINT8 rcv_comp;
1373 PI_UINT8 xmt_comp; 1374 PI_UINT8 xmt_comp;
1374 } index; 1375 } index;
1375 } PI_TYPE_2_PROD_REG; 1376 } PI_TYPE_2_PROD_REG;
1376 1377
1377 /* Little endian format of Type 1 Consumer Block longword */ 1378 /* Little endian format of Type 1 Consumer Block longword */
1378 1379
1379 typedef union 1380 typedef union
1380 { 1381 {
1381 PI_UINT32 lword; 1382 PI_UINT32 lword;
1382 struct 1383 struct
1383 { 1384 {
1384 PI_UINT8 cons; 1385 PI_UINT8 cons;
1385 PI_UINT8 res0; 1386 PI_UINT8 res0;
1386 PI_UINT8 res1; 1387 PI_UINT8 res1;
1387 PI_UINT8 res2; 1388 PI_UINT8 res2;
1388 } index; 1389 } index;
1389 } PI_TYPE_1_CONSUMER; 1390 } PI_TYPE_1_CONSUMER;
1390 1391
1391 /* Little endian format of Type 2 Consumer Block longword */ 1392 /* Little endian format of Type 2 Consumer Block longword */
1392 1393
1393 typedef union 1394 typedef union
1394 { 1395 {
1395 PI_UINT32 lword; 1396 PI_UINT32 lword;
1396 struct 1397 struct
1397 { 1398 {
1398 PI_UINT8 rcv_cons; 1399 PI_UINT8 rcv_cons;
1399 PI_UINT8 res0; 1400 PI_UINT8 res0;
1400 PI_UINT8 xmt_cons; 1401 PI_UINT8 xmt_cons;
1401 PI_UINT8 res1; 1402 PI_UINT8 res1;
1402 } index; 1403 } index;
1403 } PI_TYPE_2_CONSUMER; 1404 } PI_TYPE_2_CONSUMER;
1404 1405
1405 #else 1406 /* Define swapping required by DMA transfers. */
1407 #define PI_PDATA_A_INIT_M_BSWAP_INIT \
1408 (PI_PDATA_A_INIT_M_BSWAP_DATA)
1406 1409
1410 #else /* __BIG_ENDIAN */
1411
1407 /* Big endian format of Type 1 Producer register */ 1412 /* Big endian format of Type 1 Producer register */
1408 1413
1409 typedef union 1414 typedef union
1410 { 1415 {
1411 PI_UINT32 lword; 1416 PI_UINT32 lword;
1412 struct 1417 struct
1413 { 1418 {
1414 PI_UINT8 mbz_2; 1419 PI_UINT8 mbz_2;
1415 PI_UINT8 mbz_1; 1420 PI_UINT8 mbz_1;
1416 PI_UINT8 comp; 1421 PI_UINT8 comp;
1417 PI_UINT8 prod; 1422 PI_UINT8 prod;
1418 } index; 1423 } index;
1419 } PI_TYPE_1_PROD_REG; 1424 } PI_TYPE_1_PROD_REG;
1420 1425
1421 /* Big endian format of Type 2 Producer register */ 1426 /* Big endian format of Type 2 Producer register */
1422 1427
1423 typedef union 1428 typedef union
1424 { 1429 {
1425 PI_UINT32 lword; 1430 PI_UINT32 lword;
1426 struct 1431 struct
1427 { 1432 {
1428 PI_UINT8 xmt_comp; 1433 PI_UINT8 xmt_comp;
1429 PI_UINT8 rcv_comp; 1434 PI_UINT8 rcv_comp;
1430 PI_UINT8 xmt_prod; 1435 PI_UINT8 xmt_prod;
1431 PI_UINT8 rcv_prod; 1436 PI_UINT8 rcv_prod;
1432 } index; 1437 } index;
1433 } PI_TYPE_2_PROD_REG; 1438 } PI_TYPE_2_PROD_REG;
1434 1439
1435 /* Big endian format of Type 1 Consumer Block longword */ 1440 /* Big endian format of Type 1 Consumer Block longword */
1436 1441
1437 typedef union 1442 typedef union
1438 { 1443 {
1439 PI_UINT32 lword; 1444 PI_UINT32 lword;
1440 struct 1445 struct
1441 { 1446 {
1442 PI_UINT8 res2; 1447 PI_UINT8 res2;
1443 PI_UINT8 res1; 1448 PI_UINT8 res1;
1444 PI_UINT8 res0; 1449 PI_UINT8 res0;
1445 PI_UINT8 cons; 1450 PI_UINT8 cons;
1446 } index; 1451 } index;
1447 } PI_TYPE_1_CONSUMER; 1452 } PI_TYPE_1_CONSUMER;
1448 1453
1449 /* Big endian format of Type 2 Consumer Block longword */ 1454 /* Big endian format of Type 2 Consumer Block longword */
1450 1455
1451 typedef union 1456 typedef union
1452 { 1457 {
1453 PI_UINT32 lword; 1458 PI_UINT32 lword;
1454 struct 1459 struct
1455 { 1460 {
1456 PI_UINT8 res1; 1461 PI_UINT8 res1;
1457 PI_UINT8 xmt_cons; 1462 PI_UINT8 xmt_cons;
1458 PI_UINT8 res0; 1463 PI_UINT8 res0;
1459 PI_UINT8 rcv_cons; 1464 PI_UINT8 rcv_cons;
1460 } index; 1465 } index;
1461 } PI_TYPE_2_CONSUMER; 1466 } PI_TYPE_2_CONSUMER;
1462 1467
1463 #endif /* #ifndef BIG_ENDIAN */ 1468 /* Define swapping required by DMA transfers. */
1469 #define PI_PDATA_A_INIT_M_BSWAP_INIT \
1470 (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
1471
1472 #endif /* __BIG_ENDIAN */
1464 1473
1465 /* Define EISA controller register offsets */ 1474 /* Define EISA controller register offsets */
1466 1475
1467 #define PI_ESIC_K_BURST_HOLDOFF 0x040 1476 #define PI_ESIC_K_BURST_HOLDOFF 0x040
1468 #define PI_ESIC_K_SLOT_ID 0xC80 1477 #define PI_ESIC_K_SLOT_ID 0xC80
1469 #define PI_ESIC_K_SLOT_CNTRL 0xC84 1478 #define PI_ESIC_K_SLOT_CNTRL 0xC84
1470 #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85 1479 #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85
1471 #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86 1480 #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86
1472 #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87 1481 #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87
1473 #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88 1482 #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88
1474 #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89 1483 #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89
1475 #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A 1484 #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A
1476 #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B 1485 #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B
1477 #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C 1486 #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C
1478 #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D 1487 #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D
1479 #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E 1488 #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E
1480 #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F 1489 #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F
1481 #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90 1490 #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90
1482 #define PI_ESIC_K_IO_CMP_0_0 0xC91 1491 #define PI_ESIC_K_IO_CMP_0_0 0xC91
1483 #define PI_ESIC_K_IO_CMP_0_1 0xC92 1492 #define PI_ESIC_K_IO_CMP_0_1 0xC92
1484 #define PI_ESIC_K_IO_CMP_1_0 0xC93 1493 #define PI_ESIC_K_IO_CMP_1_0 0xC93
1485 #define PI_ESIC_K_IO_CMP_1_1 0xC94 1494 #define PI_ESIC_K_IO_CMP_1_1 0xC94
1486 #define PI_ESIC_K_IO_CMP_2_0 0xC95 1495 #define PI_ESIC_K_IO_CMP_2_0 0xC95
1487 #define PI_ESIC_K_IO_CMP_2_1 0xC96 1496 #define PI_ESIC_K_IO_CMP_2_1 0xC96
1488 #define PI_ESIC_K_IO_CMP_3_0 0xC97 1497 #define PI_ESIC_K_IO_CMP_3_0 0xC97
1489 #define PI_ESIC_K_IO_CMP_3_1 0xC98 1498 #define PI_ESIC_K_IO_CMP_3_1 0xC98
1490 #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99 1499 #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99
1491 #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A 1500 #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A
1492 #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B 1501 #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B
1493 #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C 1502 #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C
1494 #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D 1503 #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D
1495 #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E 1504 #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E
1496 #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F 1505 #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F
1497 #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0 1506 #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0
1498 #define PI_ESIC_K_MOD_CONFIG_1 0xCA1 1507 #define PI_ESIC_K_MOD_CONFIG_1 0xCA1
1499 #define PI_ESIC_K_MOD_CONFIG_2 0xCA2 1508 #define PI_ESIC_K_MOD_CONFIG_2 0xCA2
1500 #define PI_ESIC_K_MOD_CONFIG_3 0xCA3 1509 #define PI_ESIC_K_MOD_CONFIG_3 0xCA3
1501 #define PI_ESIC_K_MOD_CONFIG_4 0xCA4 1510 #define PI_ESIC_K_MOD_CONFIG_4 0xCA4
1502 #define PI_ESIC_K_MOD_CONFIG_5 0xCA5 1511 #define PI_ESIC_K_MOD_CONFIG_5 0xCA5
1503 #define PI_ESIC_K_MOD_CONFIG_6 0xCA6 1512 #define PI_ESIC_K_MOD_CONFIG_6 0xCA6
1504 #define PI_ESIC_K_MOD_CONFIG_7 0xCA7 1513 #define PI_ESIC_K_MOD_CONFIG_7 0xCA7
1505 #define PI_ESIC_K_DIP_SWITCH 0xCA8 1514 #define PI_ESIC_K_DIP_SWITCH 0xCA8
1506 #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9 1515 #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9
1507 #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA 1516 #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA
1508 #define PI_ESIC_K_DMA_CONFIG 0xCAB 1517 #define PI_ESIC_K_DMA_CONFIG 0xCAB
1509 #define PI_ESIC_K_INPUT_PORT 0xCAC 1518 #define PI_ESIC_K_INPUT_PORT 0xCAC
1510 #define PI_ESIC_K_OUTPUT_PORT 0xCAD 1519 #define PI_ESIC_K_OUTPUT_PORT 0xCAD
1511 #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE 1520 #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE
1512 #define PI_ESIC_K_CSR_IO_LEN PI_ESIC_K_FUNCTION_CNTRL+1 /* always last reg + 1 */ 1521 #define PI_ESIC_K_CSR_IO_LEN PI_ESIC_K_FUNCTION_CNTRL+1 /* always last reg + 1 */
1513 1522
1514 /* Define the value all drivers must write to the function control register. */ 1523 /* Define the value all drivers must write to the function control register. */
1515 1524
1516 #define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB 0x03 1525 #define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB 0x03
1517 1526
1518 /* Define the bits in the slot control register. */ 1527 /* Define the bits in the slot control register. */
1519 1528
1520 #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */ 1529 #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */
1521 #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */ 1530 #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */
1522 #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */ 1531 #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */
1523 1532
1524 /* Define the bits in the burst holdoff register. */ 1533 /* Define the bits in the burst holdoff register. */
1525 1534
1526 #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC 1535 #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC
1527 #define PI_BURST_HOLDOFF_M_RESERVED 0x02 1536 #define PI_BURST_HOLDOFF_M_RESERVED 0x02
1528 #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01 1537 #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01
1529 1538
1530 #define PI_BURST_HOLDOFF_V_HOLDOFF 2 1539 #define PI_BURST_HOLDOFF_V_HOLDOFF 2
1531 #define PI_BURST_HOLDOFF_V_RESERVED 1 1540 #define PI_BURST_HOLDOFF_V_RESERVED 1
1532 #define PI_BURST_HOLDOFF_V_MEM_MAP 0 1541 #define PI_BURST_HOLDOFF_V_MEM_MAP 0
1533 1542
1534 /* 1543 /*
1535 * Define the fields in the IO Compare registers. 1544 * Define the fields in the IO Compare registers.
1536 * The driver must initialize the slot field with the slot ID shifted by the 1545 * The driver must initialize the slot field with the slot ID shifted by the
1537 * amount shown below. 1546 * amount shown below.
1538 */ 1547 */
1539 1548
1540 #define PI_IO_CMP_V_SLOT 4 1549 #define PI_IO_CMP_V_SLOT 4
1541 1550
1542 /* Define the fields in the Interrupt Channel Configuration and Status reg */ 1551 /* Define the fields in the Interrupt Channel Configuration and Status reg */
1543 1552
1544 #define PI_CONFIG_STAT_0_M_PEND 0x80 1553 #define PI_CONFIG_STAT_0_M_PEND 0x80
1545 #define PI_CONFIG_STAT_0_M_RES_1 0x40 1554 #define PI_CONFIG_STAT_0_M_RES_1 0x40
1546 #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20 1555 #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20
1547 #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10 1556 #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10
1548 #define PI_CONFIG_STAT_0_M_INT_ENB 0x08 1557 #define PI_CONFIG_STAT_0_M_INT_ENB 0x08
1549 #define PI_CONFIG_STAT_0_M_RES_0 0x04 1558 #define PI_CONFIG_STAT_0_M_RES_0 0x04
1550 #define PI_CONFIG_STAT_0_M_IRQ 0x03 1559 #define PI_CONFIG_STAT_0_M_IRQ 0x03
1551 1560
1552 #define PI_CONFIG_STAT_0_V_PEND 7 1561 #define PI_CONFIG_STAT_0_V_PEND 7
1553 #define PI_CONFIG_STAT_0_V_RES_1 6 1562 #define PI_CONFIG_STAT_0_V_RES_1 6
1554 #define PI_CONFIG_STAT_0_V_IREQ_OUT 5 1563 #define PI_CONFIG_STAT_0_V_IREQ_OUT 5
1555 #define PI_CONFIG_STAT_0_V_IREQ_IN 4 1564 #define PI_CONFIG_STAT_0_V_IREQ_IN 4
1556 #define PI_CONFIG_STAT_0_V_INT_ENB 3 1565 #define PI_CONFIG_STAT_0_V_INT_ENB 3
1557 #define PI_CONFIG_STAT_0_V_RES_0 2 1566 #define PI_CONFIG_STAT_0_V_RES_0 2
1558 #define PI_CONFIG_STAT_0_V_IRQ 0 1567 #define PI_CONFIG_STAT_0_V_IRQ 0
1559 1568
1560 #define PI_CONFIG_STAT_0_IRQ_K_9 0 1569 #define PI_CONFIG_STAT_0_IRQ_K_9 0
1561 #define PI_CONFIG_STAT_0_IRQ_K_10 1 1570 #define PI_CONFIG_STAT_0_IRQ_K_10 1
1562 #define PI_CONFIG_STAT_0_IRQ_K_11 2 1571 #define PI_CONFIG_STAT_0_IRQ_K_11 2
1563 #define PI_CONFIG_STAT_0_IRQ_K_15 3 1572 #define PI_CONFIG_STAT_0_IRQ_K_15 3
1564 1573
1565 /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */ 1574 /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1566 1575
1567 #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */ 1576 #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */
1568 #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */ 1577 #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */
1569 #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */ 1578 #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */
1570 #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */ 1579 #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */
1571 1580
1572 /**********************************************/ 1581 /**********************************************/
1573 /* Digital PFI Specification v1.0 Definitions */ 1582 /* Digital PFI Specification v1.0 Definitions */
1574 /**********************************************/ 1583 /**********************************************/
1575 1584
1576 /* PCI Configuration Space Constants */ 1585 /* PCI Configuration Space Constants */
1577 1586
1578 #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */ 1587 #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */
1579 #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */ 1588 #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */
1580 #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */ 1589 #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */
1581 #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */ 1590 #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */
1582 #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */ 1591 #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */
1583 1592
1584 /* PFI Register Offsets (starting at PDQ Register Base Address) */ 1593 /* PFI Register Offsets (starting at PDQ Register Base Address) */
1585 1594
1586 #define PFI_K_REG_RESERVED_0 0X00000038 1595 #define PFI_K_REG_RESERVED_0 0X00000038
1587 #define PFI_K_REG_RESERVED_1 0X0000003C 1596 #define PFI_K_REG_RESERVED_1 0X0000003C
1588 #define PFI_K_REG_MODE_CTRL 0X00000040 1597 #define PFI_K_REG_MODE_CTRL 0X00000040
1589 #define PFI_K_REG_STATUS 0X00000044 1598 #define PFI_K_REG_STATUS 0X00000044
1590 #define PFI_K_REG_FIFO_WRITE 0X00000048 1599 #define PFI_K_REG_FIFO_WRITE 0X00000048
1591 #define PFI_K_REG_FIFO_READ 0X0000004C 1600 #define PFI_K_REG_FIFO_READ 0X0000004C
1592 1601
1593 /* PFI Mode Control Register Constants */ 1602 /* PFI Mode Control Register Constants */
1594 1603
1595 #define PFI_MODE_M_RESERVED 0XFFFFFFF0 1604 #define PFI_MODE_M_RESERVED 0XFFFFFFF0
1596 #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008 1605 #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008
1597 #define PFI_MODE_M_PDQ_INT_ENB 0X00000004 1606 #define PFI_MODE_M_PDQ_INT_ENB 0X00000004
1598 #define PFI_MODE_M_PFI_INT_ENB 0X00000002 1607 #define PFI_MODE_M_PFI_INT_ENB 0X00000002
1599 #define PFI_MODE_M_DMA_ENB 0X00000001 1608 #define PFI_MODE_M_DMA_ENB 0X00000001
1600 1609
1601 #define PFI_MODE_V_RESERVED 4 1610 #define PFI_MODE_V_RESERVED 4
1602 #define PFI_MODE_V_TGT_ABORT_ENB 3 1611 #define PFI_MODE_V_TGT_ABORT_ENB 3
1603 #define PFI_MODE_V_PDQ_INT_ENB 2 1612 #define PFI_MODE_V_PDQ_INT_ENB 2
1604 #define PFI_MODE_V_PFI_INT_ENB 1 1613 #define PFI_MODE_V_PFI_INT_ENB 1
1605 #define PFI_MODE_V_DMA_ENB 0 1614 #define PFI_MODE_V_DMA_ENB 0
1606 1615
1607 #define PFI_MODE_K_ALL_DISABLE 0X00000000 1616 #define PFI_MODE_K_ALL_DISABLE 0X00000000
1608 1617
1609 /* PFI Status Register Constants */ 1618 /* PFI Status Register Constants */
1610 1619
1611 #define PFI_STATUS_M_RESERVED 0XFFFFFFC0 1620 #define PFI_STATUS_M_RESERVED 0XFFFFFFC0
1612 #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */ 1621 #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */
1613 #define PFI_STATUS_M_PDQ_INT 0X00000010 1622 #define PFI_STATUS_M_PDQ_INT 0X00000010
1614 #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008 1623 #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008
1615 #define PFI_STATUS_M_FIFO_FULL 0X00000004 1624 #define PFI_STATUS_M_FIFO_FULL 0X00000004
1616 #define PFI_STATUS_M_FIFO_EMPTY 0X00000002 1625 #define PFI_STATUS_M_FIFO_EMPTY 0X00000002
1617 #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001 1626 #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001
1618 1627
1619 #define PFI_STATUS_V_RESERVED 6 1628 #define PFI_STATUS_V_RESERVED 6
1620 #define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */ 1629 #define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */
1621 #define PFI_STATUS_V_PDQ_INT 4 1630 #define PFI_STATUS_V_PDQ_INT 4
1622 #define PFI_STATUS_V_PDQ_DMA_ABORT 3 1631 #define PFI_STATUS_V_PDQ_DMA_ABORT 3
1623 #define PFI_STATUS_V_FIFO_FULL 2 1632 #define PFI_STATUS_V_FIFO_FULL 2
1624 #define PFI_STATUS_V_FIFO_EMPTY 1 1633 #define PFI_STATUS_V_FIFO_EMPTY 1
1625 #define PFI_STATUS_V_DMA_IN_PROGRESS 0 1634 #define PFI_STATUS_V_DMA_IN_PROGRESS 0
1626 1635
1627 #define DFX_MAX_EISA_SLOTS 16 /* maximum number of EISA slots to scan */ 1636 #define DFX_MAX_EISA_SLOTS 16 /* maximum number of EISA slots to scan */
1628 #define DFX_MAX_NUM_BOARDS 8 /* maximum number of adapters supported */ 1637 #define DFX_MAX_NUM_BOARDS 8 /* maximum number of adapters supported */
1629 1638
1630 #define DFX_BUS_TYPE_PCI 0 /* type code for DEC FDDIcontroller/PCI */ 1639 #define DFX_BUS_TYPE_PCI 0 /* type code for DEC FDDIcontroller/PCI */
1631 #define DFX_BUS_TYPE_EISA 1 /* type code for DEC FDDIcontroller/EISA */ 1640 #define DFX_BUS_TYPE_EISA 1 /* type code for DEC FDDIcontroller/EISA */
1632 1641
1633 #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */ 1642 #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */
1634 #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */ 1643 #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */
1635 #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */ 1644 #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */
1636 #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */ 1645 #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */
1637 1646
1638 /* Driver routine status (return) codes */ 1647 /* Driver routine status (return) codes */
1639 1648
1640 #define DFX_K_SUCCESS 0 /* routine succeeded */ 1649 #define DFX_K_SUCCESS 0 /* routine succeeded */
1641 #define DFX_K_FAILURE 1 /* routine failed */ 1650 #define DFX_K_FAILURE 1 /* routine failed */
1642 #define DFX_K_OUTSTATE 2 /* bad state for command */ 1651 #define DFX_K_OUTSTATE 2 /* bad state for command */
1643 #define DFX_K_HW_TIMEOUT 3 /* command timed out */ 1652 #define DFX_K_HW_TIMEOUT 3 /* command timed out */
1644 1653
1645 /* Define LLC host receive buffer min/max/default values */ 1654 /* Define LLC host receive buffer min/max/default values */
1646 1655
1647 #define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */ 1656 #define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */
1648 #define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */ 1657 #define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */
1649 #define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */ 1658 #define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */
1650 1659
1651 /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */ 1660 /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
1652 1661
1653 #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */ 1662 #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */
1654 #define RCV_BUFF_K_PADDING 4 /* three null bytes */ 1663 #define RCV_BUFF_K_PADDING 4 /* three null bytes */
1655 #define RCV_BUFF_K_FC 7 /* one byte frame control */ 1664 #define RCV_BUFF_K_FC 7 /* one byte frame control */
1656 #define RCV_BUFF_K_DA 8 /* six byte destination address */ 1665 #define RCV_BUFF_K_DA 8 /* six byte destination address */
1657 #define RCV_BUFF_K_SA 14 /* six byte source address */ 1666 #define RCV_BUFF_K_SA 14 /* six byte source address */
1658 #define RCV_BUFF_K_DATA 20 /* offset to start of packet data */ 1667 #define RCV_BUFF_K_DATA 20 /* offset to start of packet data */
1659 1668
1660 /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */ 1669 /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
1661 1670
1662 #define XMT_BUFF_K_FC 0 /* one byte frame control */ 1671 #define XMT_BUFF_K_FC 0 /* one byte frame control */
1663 #define XMT_BUFF_K_DA 1 /* six byte destination address */ 1672 #define XMT_BUFF_K_DA 1 /* six byte destination address */
1664 #define XMT_BUFF_K_SA 7 /* six byte source address */ 1673 #define XMT_BUFF_K_SA 7 /* six byte source address */
1665 #define XMT_BUFF_K_DATA 13 /* offset to start of packet data */ 1674 #define XMT_BUFF_K_DATA 13 /* offset to start of packet data */
1666 1675
1667 /* Macro for checking a "value" is within a specific range */ 1676 /* Macro for checking a "value" is within a specific range */
1668 1677
1669 #define IN_RANGE(value,low,high) ((value >= low) && (value <= high)) 1678 #define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
1670 1679
1671 /* Only execute special print call when debug driver was built */ 1680 /* Only execute special print call when debug driver was built */
1672 1681
1673 #ifdef DEFXX_DEBUG 1682 #ifdef DEFXX_DEBUG
1674 #define DBG_printk(args...) printk(## args) 1683 #define DBG_printk(args...) printk(## args)
1675 #else 1684 #else
1676 #define DBG_printk(args...) 1685 #define DBG_printk(args...)
1677 #endif 1686 #endif
1678 1687
1679 /* Define constants for masking/unmasking interrupts */ 1688 /* Define constants for masking/unmasking interrupts */
1680 1689
1681 #define DFX_MASK_INTERRUPTS 1 1690 #define DFX_MASK_INTERRUPTS 1
1682 #define DFX_UNMASK_INTERRUPTS 0 1691 #define DFX_UNMASK_INTERRUPTS 0
1683 1692
1684 /* Define structure for driver transmit descriptor block */ 1693 /* Define structure for driver transmit descriptor block */
1685 1694
1686 typedef struct 1695 typedef struct
1687 { 1696 {
1688 struct sk_buff *p_skb; /* ptr to skb */ 1697 struct sk_buff *p_skb; /* ptr to skb */
1689 } XMT_DRIVER_DESCR; 1698 } XMT_DRIVER_DESCR;
1690 1699
1691 typedef struct DFX_board_tag 1700 typedef struct DFX_board_tag
1692 { 1701 {
1693 /* Keep virtual and physical pointers to locked, physically contiguous memory */ 1702 /* Keep virtual and physical pointers to locked, physically contiguous memory */
1694 1703
1695 char *kmalloced; /* pci_free_consistent this on unload */ 1704 char *kmalloced; /* pci_free_consistent this on unload */
1696 dma_addr_t kmalloced_dma; 1705 dma_addr_t kmalloced_dma;
1697 /* DMA handle for the above */ 1706 /* DMA handle for the above */
1698 PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */ 1707 PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */
1699 dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */ 1708 dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */
1700 PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */ 1709 PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */
1701 dma_addr_t cmd_req_phys; /* Command request buffer phys address */ 1710 dma_addr_t cmd_req_phys; /* Command request buffer phys address */
1702 PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */ 1711 PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */
1703 dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */ 1712 dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */
1704 char *rcv_block_virt; /* LLC host receive queue buf blk virt */ 1713 char *rcv_block_virt; /* LLC host receive queue buf blk virt */
1705 dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */ 1714 dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */
1706 PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */ 1715 PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */
1707 dma_addr_t cons_block_phys; /* PDQ consumer block phys address */ 1716 dma_addr_t cons_block_phys; /* PDQ consumer block phys address */
1708 1717
1709 /* Keep local copies of Type 1 and Type 2 register data */ 1718 /* Keep local copies of Type 1 and Type 2 register data */
1710 1719
1711 PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */ 1720 PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */
1712 PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */ 1721 PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */
1713 PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */ 1722 PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */
1714 1723
1715 /* Storage for unicast and multicast address entries in adapter CAM */ 1724 /* Storage for unicast and multicast address entries in adapter CAM */
1716 1725
1717 u8 uc_table[1*FDDI_K_ALEN]; 1726 u8 uc_table[1*FDDI_K_ALEN];
1718 u32 uc_count; /* number of unicast addresses */ 1727 u32 uc_count; /* number of unicast addresses */
1719 u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN]; 1728 u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
1720 u32 mc_count; /* number of multicast addresses */ 1729 u32 mc_count; /* number of multicast addresses */
1721 1730
1722 /* Current packet filter settings */ 1731 /* Current packet filter settings */
1723 1732
1724 u32 ind_group_prom; /* LLC individual & group frame prom mode */ 1733 u32 ind_group_prom; /* LLC individual & group frame prom mode */
1725 u32 group_prom; /* LLC group (multicast) frame prom mode */ 1734 u32 group_prom; /* LLC group (multicast) frame prom mode */
1726 1735
1727 /* Link available flag needed to determine whether to drop outgoing packet requests */ 1736 /* Link available flag needed to determine whether to drop outgoing packet requests */
1728 1737
1729 u32 link_available; /* is link available? */ 1738 u32 link_available; /* is link available? */
1730 1739
1731 /* Resources to indicate reset type when resetting adapter */ 1740 /* Resources to indicate reset type when resetting adapter */
1732 1741
1733 u32 reset_type; /* skip or rerun diagnostics */ 1742 u32 reset_type; /* skip or rerun diagnostics */
1734 1743
1735 /* Store pointers to receive buffers for queue processing code */ 1744 /* Store pointers to receive buffers for queue processing code */
1736 1745
1737 char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES]; 1746 char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
1738 1747
1739 /* Store pointers to transmit buffers for transmit completion code */ 1748 /* Store pointers to transmit buffers for transmit completion code */
1740 1749
1741 XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES]; 1750 XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
1742 1751
1743 /* Transmit spinlocks */ 1752 /* Transmit spinlocks */
1744 1753
1745 spinlock_t lock; 1754 spinlock_t lock;
1746 1755
1747 /* Store device, bus-specific, and parameter information for this adapter */ 1756 /* Store device, bus-specific, and parameter information for this adapter */
1748 1757
1749 struct net_device *dev; /* pointer to device structure */ 1758 struct net_device *dev; /* pointer to device structure */
1750 struct net_device *next; 1759 struct net_device *next;
1751 u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */ 1760 u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */
1752 u16 base_addr; /* base I/O address (same as dev->base_addr) */ 1761 u16 base_addr; /* base I/O address (same as dev->base_addr) */
1753 struct pci_dev * pci_dev; 1762 struct pci_dev * pci_dev;
1754 u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */ 1763 u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */
1755 u32 req_ttrt; /* requested TTRT value (in 80ns units) */ 1764 u32 req_ttrt; /* requested TTRT value (in 80ns units) */
1756 u32 burst_size; /* adapter burst size (enumerated) */ 1765 u32 burst_size; /* adapter burst size (enumerated) */
1757 u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */ 1766 u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */
1758 u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */ 1767 u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */
1759 1768
1760 /* Common FDDI statistics structure and private counters */ 1769 /* Common FDDI statistics structure and private counters */
1761 1770
1762 struct fddi_statistics stats; 1771 struct fddi_statistics stats;
1763 1772
1764 u32 rcv_discards; 1773 u32 rcv_discards;
1765 u32 rcv_crc_errors; 1774 u32 rcv_crc_errors;
1766 u32 rcv_frame_status_errors; 1775 u32 rcv_frame_status_errors;
1767 u32 rcv_length_errors; 1776 u32 rcv_length_errors;
1768 u32 rcv_total_frames; 1777 u32 rcv_total_frames;
1769 u32 rcv_multicast_frames; 1778 u32 rcv_multicast_frames;
1770 u32 rcv_total_bytes; 1779 u32 rcv_total_bytes;
1771 1780
1772 u32 xmt_discards; 1781 u32 xmt_discards;
1773 u32 xmt_length_errors; 1782 u32 xmt_length_errors;
1774 u32 xmt_total_frames; 1783 u32 xmt_total_frames;
1775 u32 xmt_total_bytes; 1784 u32 xmt_total_bytes;
1776 } DFX_board_t; 1785 } DFX_board_t;
1777 1786
1778 #endif /* #ifndef _DEFXX_H_ */ 1787 #endif /* #ifndef _DEFXX_H_ */
1779 1788