Commit b2e68aa337f950e4a8c893a82b95b1755309bc56
Committed by
Jeff Garzik
Jeff Garzik
1 parent
c3a9392e4f
Exists in
master
and in
4 other branches
[PATCH] defxx: Big-endian hosts support
The PDQ DMA engine requires a different byte-swapping mode for big-endian hosts; also the MAC address which is read from a register through PIO has to be byte-swapped. These changes have been verified with DEFPA-DC (PCI) boards and a Broadcom BCM91250A (MIPS CPU based) host. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Showing 2 changed files with 31 additions and 23 deletions Side-by-side Diff
drivers/net/defxx.c
| ... | ... | @@ -192,6 +192,7 @@ |
| 192 | 192 | * 04 Aug 2003 macro Converted to the DMA API. |
| 193 | 193 | * 14 Aug 2004 macro Fix device names reported. |
| 194 | 194 | * 14 Jun 2005 macro Use irqreturn_t. |
| 195 | + * 23 Oct 2006 macro Big-endian host support. | |
| 195 | 196 | */ |
| 196 | 197 | |
| 197 | 198 | /* Include files */ |
| ... | ... | @@ -218,8 +219,8 @@ |
| 218 | 219 | |
| 219 | 220 | /* Version information string should be updated prior to each new release! */ |
| 220 | 221 | #define DRV_NAME "defxx" |
| 221 | -#define DRV_VERSION "v1.08" | |
| 222 | -#define DRV_RELDATE "2005/06/14" | |
| 222 | +#define DRV_VERSION "v1.09" | |
| 223 | +#define DRV_RELDATE "2006/10/23" | |
| 223 | 224 | |
| 224 | 225 | static char version[] __devinitdata = |
| 225 | 226 | DRV_NAME ": " DRV_VERSION " " DRV_RELDATE |
| ... | ... | @@ -859,6 +860,7 @@ |
| 859 | 860 | print_name); |
| 860 | 861 | return(DFX_K_FAILURE); |
| 861 | 862 | } |
| 863 | + data = cpu_to_le32(data); | |
| 862 | 864 | memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); |
| 863 | 865 | |
| 864 | 866 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, |
| ... | ... | @@ -867,6 +869,7 @@ |
| 867 | 869 | print_name); |
| 868 | 870 | return(DFX_K_FAILURE); |
| 869 | 871 | } |
| 872 | + data = cpu_to_le32(data); | |
| 870 | 873 | memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); |
| 871 | 874 | |
| 872 | 875 | /* |
| 873 | 876 | |
| 874 | 877 | |
| 875 | 878 | |
| ... | ... | @@ -1085,27 +1088,23 @@ |
| 1085 | 1088 | } |
| 1086 | 1089 | |
| 1087 | 1090 | /* |
| 1088 | - * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state | |
| 1091 | + * Set the base address of Descriptor Block and bring adapter | |
| 1092 | + * to DMA_AVAILABLE state. | |
| 1089 | 1093 | * |
| 1090 | - * Note: We also set the literal and data swapping requirements in this | |
| 1091 | - * command. Since this driver presently runs on Intel platforms | |
| 1092 | - * which are Little Endian, we'll tell the adapter to byte swap | |
| 1093 | - * data only. This code will need to change when we support | |
| 1094 | - * Big Endian systems (eg. PowerPC). | |
| 1094 | + * Note: We also set the literal and data swapping requirements | |
| 1095 | + * in this command. | |
| 1095 | 1096 | * |
| 1096 | - * Assumption: 32-bit physical address of descriptor block is 8Kbyte | |
| 1097 | - * aligned. That is, bits 0-12 of the address must be zero. | |
| 1097 | + * Assumption: 32-bit physical address of descriptor block | |
| 1098 | + * is 8Kbyte aligned. | |
| 1098 | 1099 | */ |
| 1099 | - | |
| 1100 | - if (dfx_hw_port_ctrl_req(bp, | |
| 1101 | - PI_PCTRL_M_INIT, | |
| 1102 | - (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA), | |
| 1103 | - 0, | |
| 1104 | - NULL) != DFX_K_SUCCESS) | |
| 1105 | - { | |
| 1106 | - printk("%s: Could not set descriptor block address!\n", bp->dev->name); | |
| 1107 | - return(DFX_K_FAILURE); | |
| 1108 | - } | |
| 1100 | + if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, | |
| 1101 | + (u32)(bp->descr_block_phys | | |
| 1102 | + PI_PDATA_A_INIT_M_BSWAP_INIT), | |
| 1103 | + 0, NULL) != DFX_K_SUCCESS) { | |
| 1104 | + printk("%s: Could not set descriptor block address!\n", | |
| 1105 | + bp->dev->name); | |
| 1106 | + return DFX_K_FAILURE; | |
| 1107 | + } | |
| 1109 | 1108 | |
| 1110 | 1109 | /* Set transmit flush timeout value */ |
| 1111 | 1110 |
drivers/net/defxx.h
| ... | ... | @@ -25,6 +25,7 @@ |
| 25 | 25 | * macros to DEFXX.C. |
| 26 | 26 | * 12-Sep-96 LVS Removed packet request header pointers. |
| 27 | 27 | * 04 Aug 2003 macro Converted to the DMA API. |
| 28 | + * 23 Oct 2006 macro Big-endian host support. | |
| 28 | 29 | */ |
| 29 | 30 | |
| 30 | 31 | #ifndef _DEFXX_H_ |
| ... | ... | @@ -1344,7 +1345,7 @@ |
| 1344 | 1345 | |
| 1345 | 1346 | /* Register definition structures are defined for both big and little endian systems */ |
| 1346 | 1347 | |
| 1347 | -#ifndef BIG_ENDIAN | |
| 1348 | +#ifndef __BIG_ENDIAN | |
| 1348 | 1349 | |
| 1349 | 1350 | /* Little endian format of Type 1 Producer register */ |
| 1350 | 1351 | |
| 1351 | 1352 | |
| ... | ... | @@ -1402,8 +1403,12 @@ |
| 1402 | 1403 | } index; |
| 1403 | 1404 | } PI_TYPE_2_CONSUMER; |
| 1404 | 1405 | |
| 1405 | -#else | |
| 1406 | +/* Define swapping required by DMA transfers. */ | |
| 1407 | +#define PI_PDATA_A_INIT_M_BSWAP_INIT \ | |
| 1408 | + (PI_PDATA_A_INIT_M_BSWAP_DATA) | |
| 1406 | 1409 | |
| 1410 | +#else /* __BIG_ENDIAN */ | |
| 1411 | + | |
| 1407 | 1412 | /* Big endian format of Type 1 Producer register */ |
| 1408 | 1413 | |
| 1409 | 1414 | typedef union |
| ... | ... | @@ -1460,7 +1465,11 @@ |
| 1460 | 1465 | } index; |
| 1461 | 1466 | } PI_TYPE_2_CONSUMER; |
| 1462 | 1467 | |
| 1463 | -#endif /* #ifndef BIG_ENDIAN */ | |
| 1468 | +/* Define swapping required by DMA transfers. */ | |
| 1469 | +#define PI_PDATA_A_INIT_M_BSWAP_INIT \ | |
| 1470 | + (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL) | |
| 1471 | + | |
| 1472 | +#endif /* __BIG_ENDIAN */ | |
| 1464 | 1473 | |
| 1465 | 1474 | /* Define EISA controller register offsets */ |
| 1466 | 1475 |