Eric Lee / linux-smarc-t335x-v3.2

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Commit ba0cef3d149ce4db293c572bf36ed352b11ce7b9

Authored by Stephane Eranian
Committed by Ingo Molnar
1 parent c530ccd9a1
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

perf_events: Fix bogus AMD64 generic TLB events 

PERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 which
counts nothing. Needed to be 0x7 (to count all possibilities).

PERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 which
counts nothing. Needed to be 0x3 (to count all possibilities).

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Robert Richter <robert.richter@amd.com>
Cc: <stable@kernel.org> # as far back as it applies
LKML-Reference: <4cb85478.41e9d80a.44e2.3f00@mx.google.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 1 changed file with 2 additions and 2 deletions Side-by-side Diff

arch/x86/kernel/cpu/perf_event_amd.c
Diff comments   View file @ ba0cef3
... ... @@ -52,7 +52,7 @@
52 52 [ C(DTLB) ] = {
53 53 [ C(OP_READ) ] = {
54 54 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
55   - [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
  55 + [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
56 56 },
57 57 [ C(OP_WRITE) ] = {
58 58 [ C(RESULT_ACCESS) ] = 0,
... ... @@ -66,7 +66,7 @@
66 66 [ C(ITLB) ] = {
67 67 [ C(OP_READ) ] = {
68 68 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
69   - [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
  69 + [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
70 70 },
71 71 [ C(OP_WRITE) ] = {
72 72 [ C(RESULT_ACCESS) ] = -1,