Commit c11389406f19e4bddc7b347e5259aebda02b23f1

Authored by Michal Simek
1 parent a2f526994e

microblaze: Fix unaligned value saving to the stack for system with MMU

Several registers weren't saved correctly to the stack.

Unaligned expection for system with MMU stores
value in ex_tmp_data_loc_X address which is load to registers r3.
The next step is to move this value from r3 to a destination
register which caused unaligned exception. For several registers
this value was directly moved to the register.

For example for r28:
by "or r28, r0, r3"

but register r28 was rewritten when kernel returns from exception
handler by value saved on stack.

This patch changed r3 saving to the correct address on the stack.
For example for r28:
by "swi r3, r1, 4 * 28"

When kernel returns from the exception handler, correct value is restored.

Signed-off-by: Michal Simek <monstr@monstr.eu>

Showing 1 changed file with 28 additions and 28 deletions Side-by-side Diff

arch/microblaze/kernel/hw_exception_handler.S
... ... @@ -1113,23 +1113,23 @@
1113 1113 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1114 1114 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1115 1115 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1116   -lw_r14_vm: R3_TO_LWREG_VM (14);
  1116 +lw_r14_vm: R3_TO_LWREG_VM_V (14);
1117 1117 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1118   -lw_r16_vm: R3_TO_LWREG_VM (16);
  1118 +lw_r16_vm: R3_TO_LWREG_VM_V (16);
1119 1119 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1120 1120 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1121   -lw_r19_vm: R3_TO_LWREG_VM (19);
1122   -lw_r20_vm: R3_TO_LWREG_VM (20);
1123   -lw_r21_vm: R3_TO_LWREG_VM (21);
1124   -lw_r22_vm: R3_TO_LWREG_VM (22);
1125   -lw_r23_vm: R3_TO_LWREG_VM (23);
1126   -lw_r24_vm: R3_TO_LWREG_VM (24);
1127   -lw_r25_vm: R3_TO_LWREG_VM (25);
1128   -lw_r26_vm: R3_TO_LWREG_VM (26);
1129   -lw_r27_vm: R3_TO_LWREG_VM (27);
1130   -lw_r28_vm: R3_TO_LWREG_VM (28);
1131   -lw_r29_vm: R3_TO_LWREG_VM (29);
1132   -lw_r30_vm: R3_TO_LWREG_VM (30);
  1121 +lw_r19_vm: R3_TO_LWREG_VM_V (19);
  1122 +lw_r20_vm: R3_TO_LWREG_VM_V (20);
  1123 +lw_r21_vm: R3_TO_LWREG_VM_V (21);
  1124 +lw_r22_vm: R3_TO_LWREG_VM_V (22);
  1125 +lw_r23_vm: R3_TO_LWREG_VM_V (23);
  1126 +lw_r24_vm: R3_TO_LWREG_VM_V (24);
  1127 +lw_r25_vm: R3_TO_LWREG_VM_V (25);
  1128 +lw_r26_vm: R3_TO_LWREG_VM_V (26);
  1129 +lw_r27_vm: R3_TO_LWREG_VM_V (27);
  1130 +lw_r28_vm: R3_TO_LWREG_VM_V (28);
  1131 +lw_r29_vm: R3_TO_LWREG_VM_V (29);
  1132 +lw_r30_vm: R3_TO_LWREG_VM_V (30);
1133 1133 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1134 1134  
1135 1135 sw_table_vm:
1136 1136  
1137 1137  
... ... @@ -1147,23 +1147,23 @@
1147 1147 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1148 1148 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1149 1149 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1150   -sw_r14_vm: SWREG_TO_R3_VM (14);
  1150 +sw_r14_vm: SWREG_TO_R3_VM_V (14);
1151 1151 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1152   -sw_r16_vm: SWREG_TO_R3_VM (16);
  1152 +sw_r16_vm: SWREG_TO_R3_VM_V (16);
1153 1153 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1154 1154 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1155   -sw_r19_vm: SWREG_TO_R3_VM (19);
1156   -sw_r20_vm: SWREG_TO_R3_VM (20);
1157   -sw_r21_vm: SWREG_TO_R3_VM (21);
1158   -sw_r22_vm: SWREG_TO_R3_VM (22);
1159   -sw_r23_vm: SWREG_TO_R3_VM (23);
1160   -sw_r24_vm: SWREG_TO_R3_VM (24);
1161   -sw_r25_vm: SWREG_TO_R3_VM (25);
1162   -sw_r26_vm: SWREG_TO_R3_VM (26);
1163   -sw_r27_vm: SWREG_TO_R3_VM (27);
1164   -sw_r28_vm: SWREG_TO_R3_VM (28);
1165   -sw_r29_vm: SWREG_TO_R3_VM (29);
1166   -sw_r30_vm: SWREG_TO_R3_VM (30);
  1155 +sw_r19_vm: SWREG_TO_R3_VM_V (19);
  1156 +sw_r20_vm: SWREG_TO_R3_VM_V (20);
  1157 +sw_r21_vm: SWREG_TO_R3_VM_V (21);
  1158 +sw_r22_vm: SWREG_TO_R3_VM_V (22);
  1159 +sw_r23_vm: SWREG_TO_R3_VM_V (23);
  1160 +sw_r24_vm: SWREG_TO_R3_VM_V (24);
  1161 +sw_r25_vm: SWREG_TO_R3_VM_V (25);
  1162 +sw_r26_vm: SWREG_TO_R3_VM_V (26);
  1163 +sw_r27_vm: SWREG_TO_R3_VM_V (27);
  1164 +sw_r28_vm: SWREG_TO_R3_VM_V (28);
  1165 +sw_r29_vm: SWREG_TO_R3_VM_V (29);
  1166 +sw_r30_vm: SWREG_TO_R3_VM_V (30);
1167 1167 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1168 1168 #endif /* CONFIG_MMU */
1169 1169