gpio: sx150x: add Semtech I2C sx150x gpio expander driver

Add support for Semtech SX150-series I2C GPIO expanders. Compatible models include: 8 bits: sx1508q 16 bits: sx1509q Signed-off-by: Gregory Bean <gbean@codeaurora.org> Cc: David Brownell <david-b@pacbell.net> Cc: Jean Delvare <khali@linux-fr.org> Cc: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

gpio: sx150x: add Semtech I2C sx150x gpio expander driver
Add support for Semtech SX150-series I2C GPIO expanders. Compatible models include: 8 bits: sx1508q 16 bits: sx1509q Signed-off-by: Gregory Bean <gbean@codeaurora.org> Cc: David Brownell <david-b@pacbell.net> Cc: Jean Delvare <khali@linux-fr.org> Cc: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Gregory Bean · Linus Torvalds
1 parent 364fadb32b
Showing 4 changed files with 735 additions and 0 deletions Side-by-side Diff
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/sx150x.c
include/linux/i2c/sx150x.h
@@ -195,6 +195,17 @@
 	  This driver provides an in-kernel interface to those GPIOs using
 	  platform-neutral GPIO calls.
  
+config GPIO_SX150X
+	bool "Semtech SX150x I2C GPIO expander"
+	depends on I2C=y
+	default n
+	help
+	  Say yes here to provide support for Semtech SX150-series I2C
+	  GPIO expanders. Compatible models include:
+
+	  8 bits:  sx1508q
+	  16 bits: sx1509q
+
 config GPIO_TC35892
 	bool "TC35892 GPIOs"
 	depends on MFD_TC35892
@@ -35,4 +35,5 @@
 obj-$(CONFIG_GPIO_SCH)		+= sch_gpio.o
 obj-$(CONFIG_GPIO_RDC321X)	+= rdc321x-gpio.o
 obj-$(CONFIG_GPIO_JANZ_TTL)	+= janz-ttl.o
+obj-$(CONFIG_GPIO_SX150X)	+= sx150x.o
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/i2c/sx150x.h>
+
+struct sx150x_device_data {
+	u8 reg_pullup;
+	u8 reg_pulldn;
+	u8 reg_drain;
+	u8 reg_polarity;
+	u8 reg_dir;
+	u8 reg_data;
+	u8 reg_irq_mask;
+	u8 reg_irq_src;
+	u8 reg_sense;
+	u8 reg_clock;
+	u8 reg_misc;
+	u8 reg_reset;
+	u8 ngpios;
+};
+
+struct sx150x_chip {
+	struct gpio_chip                 gpio_chip;
+	struct i2c_client               *client;
+	const struct sx150x_device_data *dev_cfg;
+	int                              irq_summary;
+	int                              irq_base;
+	u32                              irq_sense;
+	unsigned long                    irq_set_type_pending;
+	struct irq_chip                  irq_chip;
+	struct mutex                     lock;
+};
+
+static const struct sx150x_device_data sx150x_devices[] = {
+	[0] = { /* sx1508q */
+		.reg_pullup   = 0x03,
+		.reg_pulldn   = 0x04,
+		.reg_drain    = 0x05,
+		.reg_polarity = 0x06,
+		.reg_dir      = 0x07,
+		.reg_data     = 0x08,
+		.reg_irq_mask = 0x09,
+		.reg_irq_src  = 0x0c,
+		.reg_sense    = 0x0b,
+		.reg_clock    = 0x0f,
+		.reg_misc     = 0x10,
+		.reg_reset    = 0x7d,
+		.ngpios       = 8
+	},
+	[1] = { /* sx1509q */
+		.reg_pullup   = 0x07,
+		.reg_pulldn   = 0x09,
+		.reg_drain    = 0x0b,
+		.reg_polarity = 0x0d,
+		.reg_dir      = 0x0f,
+		.reg_data     = 0x11,
+		.reg_irq_mask = 0x13,
+		.reg_irq_src  = 0x19,
+		.reg_sense    = 0x17,
+		.reg_clock    = 0x1e,
+		.reg_misc     = 0x1f,
+		.reg_reset    = 0x7d,
+		.ngpios       = 16
+	},
+};
+
+static const struct i2c_device_id sx150x_id[] = {
+	{"sx1508q", 0},
+	{"sx1509q", 1},
+	{}
+};
+MODULE_DEVICE_TABLE(i2c, sx150x_id);
+
+static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
+{
+	s32 err = i2c_smbus_write_byte_data(client, reg, val);
+
+	if (err < 0)
+		dev_warn(&client->dev,
+			"i2c write fail: can't write %02x to %02x: %d\n",
+			val, reg, err);
+	return err;
+}
+
+static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
+{
+	s32 err = i2c_smbus_read_byte_data(client, reg);
+
+	if (err >= 0)
+		*val = err;
+	else
+		dev_warn(&client->dev,
+			"i2c read fail: can't read from %02x: %d\n",
+			reg, err);
+	return err;
+}
+
+static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
+{
+	return (chip->dev_cfg->ngpios == offset);
+}
+
+/*
+ * These utility functions solve the common problem of locating and setting
+ * configuration bits.  Configuration bits are grouped into registers
+ * whose indexes increase downwards.  For example, with eight-bit registers,
+ * sixteen gpios would have their config bits grouped in the following order:
+ * REGISTER N-1 [ f e d c b a 9 8 ]
+ *          N   [ 7 6 5 4 3 2 1 0 ]
+ *
+ * For multi-bit configurations, the pattern gets wider:
+ * REGISTER N-3 [ f f e e d d c c ]
+ *          N-2 [ b b a a 9 9 8 8 ]
+ *          N-1 [ 7 7 6 6 5 5 4 4 ]
+ *          N   [ 3 3 2 2 1 1 0 0 ]
+ *
+ * Given the address of the starting register 'N', the index of the gpio
+ * whose configuration we seek to change, and the width in bits of that
+ * configuration, these functions allow us to locate the correct
+ * register and mask the correct bits.
+ */
+static inline void sx150x_find_cfg(u8 offset, u8 width,
+				u8 *reg, u8 *mask, u8 *shift)
+{
+	*reg   -= offset * width / 8;
+	*mask   = (1 << width) - 1;
+	*shift  = (offset * width) % 8;
+	*mask <<= *shift;
+}
+
+static s32 sx150x_write_cfg(struct sx150x_chip *chip,
+			u8 offset, u8 width, u8 reg, u8 val)
+{
+	u8  mask;
+	u8  data;
+	u8  shift;
+	s32 err;
+
+	sx150x_find_cfg(offset, width, &reg, &mask, &shift);
+	err = sx150x_i2c_read(chip->client, reg, &data);
+	if (err < 0)
+		return err;
+
+	data &= ~mask;
+	data |= (val << shift) & mask;
+	return sx150x_i2c_write(chip->client, reg, data);
+}
+
+static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
+{
+	u8  reg = chip->dev_cfg->reg_data;
+	u8  mask;
+	u8  data;
+	u8  shift;
+	s32 err;
+
+	sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
+	err = sx150x_i2c_read(chip->client, reg, &data);
+	if (err >= 0)
+		err = (data & mask) != 0 ? 1 : 0;
+
+	return err;
+}
+
+static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
+{
+	sx150x_i2c_write(chip->client,
+			chip->dev_cfg->reg_clock,
+			(val ? 0x1f : 0x10));
+}
+
+static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
+{
+	sx150x_write_cfg(chip,
+			offset,
+			1,
+			chip->dev_cfg->reg_data,
+			(val ? 1 : 0));
+}
+
+static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
+{
+	return sx150x_write_cfg(chip,
+				offset,
+				1,
+				chip->dev_cfg->reg_dir,
+				1);
+}
+
+static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
+{
+	int err;
+
+	err = sx150x_write_cfg(chip,
+			offset,
+			1,
+			chip->dev_cfg->reg_data,
+			(val ? 1 : 0));
+	if (err >= 0)
+		err = sx150x_write_cfg(chip,
+				offset,
+				1,
+				chip->dev_cfg->reg_dir,
+				0);
+	return err;
+}
+
+static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+	struct sx150x_chip *chip;
+	int status = -EINVAL;
+
+	chip = container_of(gc, struct sx150x_chip, gpio_chip);
+
+	if (!offset_is_oscio(chip, offset)) {
+		mutex_lock(&chip->lock);
+		status = sx150x_get_io(chip, offset);
+		mutex_unlock(&chip->lock);
+	}
+
+	return status;
+}
+
+static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
+{
+	struct sx150x_chip *chip;
+
+	chip = container_of(gc, struct sx150x_chip, gpio_chip);
+
+	mutex_lock(&chip->lock);
+	if (offset_is_oscio(chip, offset))
+		sx150x_set_oscio(chip, val);
+	else
+		sx150x_set_io(chip, offset, val);
+	mutex_unlock(&chip->lock);
+}
+
+static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+	struct sx150x_chip *chip;
+	int status = -EINVAL;
+
+	chip = container_of(gc, struct sx150x_chip, gpio_chip);
+
+	if (!offset_is_oscio(chip, offset)) {
+		mutex_lock(&chip->lock);
+		status = sx150x_io_input(chip, offset);
+		mutex_unlock(&chip->lock);
+	}
+	return status;
+}
+
+static int sx150x_gpio_direction_output(struct gpio_chip *gc,
+					unsigned offset,
+					int val)
+{
+	struct sx150x_chip *chip;
+	int status = 0;
+
+	chip = container_of(gc, struct sx150x_chip, gpio_chip);
+
+	if (!offset_is_oscio(chip, offset)) {
+		mutex_lock(&chip->lock);
+		status = sx150x_io_output(chip, offset, val);
+		mutex_unlock(&chip->lock);
+	}
+	return status;
+}
+
+static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+	struct sx150x_chip *chip;
+
+	chip = container_of(gc, struct sx150x_chip, gpio_chip);
+
+	if (offset >= chip->dev_cfg->ngpios)
+		return -EINVAL;
+
+	if (chip->irq_base < 0)
+		return -EINVAL;
+
+	return chip->irq_base + offset;
+}
+
+static void sx150x_irq_mask(unsigned int irq)
+{
+	struct irq_chip *ic = get_irq_chip(irq);
+	struct sx150x_chip *chip;
+	unsigned n;
+
+	chip = container_of(ic, struct sx150x_chip, irq_chip);
+	n = irq - chip->irq_base;
+
+	sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
+	sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
+}
+
+static void sx150x_irq_unmask(unsigned int irq)
+{
+	struct irq_chip *ic = get_irq_chip(irq);
+	struct sx150x_chip *chip;
+	unsigned n;
+
+	chip = container_of(ic, struct sx150x_chip, irq_chip);
+	n = irq - chip->irq_base;
+
+	sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
+	sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
+			 chip->irq_sense >> (n * 2));
+}
+
+static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+	struct irq_chip *ic = get_irq_chip(irq);
+	struct sx150x_chip *chip;
+	unsigned n, val = 0;
+
+	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
+		return -EINVAL;
+
+	chip = container_of(ic, struct sx150x_chip, irq_chip);
+	n = irq - chip->irq_base;
+
+	if (flow_type & IRQ_TYPE_EDGE_RISING)
+		val |= 0x1;
+	if (flow_type & IRQ_TYPE_EDGE_FALLING)
+		val |= 0x2;
+
+	chip->irq_sense &= ~(3UL << (n * 2));
+	chip->irq_sense |= val << (n * 2);
+	chip->irq_set_type_pending |= BIT(n);
+	return 0;
+}
+
+static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
+{
+	struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
+	unsigned nhandled = 0;
+	unsigned sub_irq;
+	unsigned n;
+	s32 err;
+	u8 val;
+	int i;
+
+	for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
+		err = sx150x_i2c_read(chip->client,
+				      chip->dev_cfg->reg_irq_src - i,
+				      &val);
+		if (err < 0)
+			continue;
+
+		sx150x_i2c_write(chip->client,
+				chip->dev_cfg->reg_irq_src - i,
+				val);
+		for (n = 0; n < 8; ++n) {
+			if (val & (1 << n)) {
+				sub_irq = chip->irq_base + (i * 8) + n;
+				handle_nested_irq(sub_irq);
+				++nhandled;
+			}
+		}
+	}
+
+	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
+}
+
+static void sx150x_irq_bus_lock(unsigned int irq)
+{
+	struct irq_chip *ic = get_irq_chip(irq);
+	struct sx150x_chip *chip;
+
+	chip = container_of(ic, struct sx150x_chip, irq_chip);
+
+	mutex_lock(&chip->lock);
+}
+
+static void sx150x_irq_bus_sync_unlock(unsigned int irq)
+{
+	struct irq_chip *ic = get_irq_chip(irq);
+	struct sx150x_chip *chip;
+	unsigned n;
+
+	chip = container_of(ic, struct sx150x_chip, irq_chip);
+
+	while (chip->irq_set_type_pending) {
+		n = __ffs(chip->irq_set_type_pending);
+		chip->irq_set_type_pending &= ~BIT(n);
+		if (!(irq_to_desc(n + chip->irq_base)->status & IRQ_MASKED))
+			sx150x_write_cfg(chip, n, 2,
+					chip->dev_cfg->reg_sense,
+					chip->irq_sense >> (n * 2));
+	}
+
+	mutex_unlock(&chip->lock);
+}
+
+static void sx150x_init_chip(struct sx150x_chip *chip,
+			struct i2c_client *client,
+			kernel_ulong_t driver_data,
+			struct sx150x_platform_data *pdata)
+{
+	mutex_init(&chip->lock);
+
+	chip->client                     = client;
+	chip->dev_cfg                    = &sx150x_devices[driver_data];
+	chip->gpio_chip.label            = client->name;
+	chip->gpio_chip.direction_input  = sx150x_gpio_direction_input;
+	chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
+	chip->gpio_chip.get              = sx150x_gpio_get;
+	chip->gpio_chip.set              = sx150x_gpio_set;
+	chip->gpio_chip.to_irq           = sx150x_gpio_to_irq;
+	chip->gpio_chip.base             = pdata->gpio_base;
+	chip->gpio_chip.can_sleep        = 1;
+	chip->gpio_chip.ngpio            = chip->dev_cfg->ngpios;
+	if (pdata->oscio_is_gpo)
+		++chip->gpio_chip.ngpio;
+
+	chip->irq_chip.name            = client->name;
+	chip->irq_chip.mask            = sx150x_irq_mask;
+	chip->irq_chip.unmask          = sx150x_irq_unmask;
+	chip->irq_chip.set_type        = sx150x_irq_set_type;
+	chip->irq_chip.bus_lock        = sx150x_irq_bus_lock;
+	chip->irq_chip.bus_sync_unlock = sx150x_irq_bus_sync_unlock;
+	chip->irq_summary              = -1;
+	chip->irq_base                 = -1;
+	chip->irq_sense                = 0;
+	chip->irq_set_type_pending     = 0;
+}
+
+static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
+{
+	int err = 0;
+	unsigned n;
+
+	for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
+		err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
+	return err;
+}
+
+static int sx150x_init_hw(struct sx150x_chip *chip,
+			struct sx150x_platform_data *pdata)
+{
+	int err = 0;
+
+	err = i2c_smbus_write_word_data(chip->client,
+					chip->dev_cfg->reg_reset,
+					0x3412);
+	if (err < 0)
+		return err;
+
+	err = sx150x_i2c_write(chip->client,
+			chip->dev_cfg->reg_misc,
+			0x01);
+	if (err < 0)
+		return err;
+
+	err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
+			pdata->io_pullup_ena);
+	if (err < 0)
+		return err;
+
+	err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
+			pdata->io_pulldn_ena);
+	if (err < 0)
+		return err;
+
+	err = sx150x_init_io(chip, chip->dev_cfg->reg_drain,
+			pdata->io_open_drain_ena);
+	if (err < 0)
+		return err;
+
+	err = sx150x_init_io(chip, chip->dev_cfg->reg_polarity,
+			pdata->io_polarity);
+	if (err < 0)
+		return err;
+
+	if (pdata->oscio_is_gpo)
+		sx150x_set_oscio(chip, 0);
+
+	return err;
+}
+
+static int sx150x_install_irq_chip(struct sx150x_chip *chip,
+				int irq_summary,
+				int irq_base)
+{
+	int err;
+	unsigned n;
+	unsigned irq;
+
+	chip->irq_summary = irq_summary;
+	chip->irq_base    = irq_base;
+
+	for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
+		irq = irq_base + n;
+		set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
+		set_irq_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+		set_irq_flags(irq, IRQF_VALID);
+#else
+		set_irq_noprobe(irq);
+#endif
+	}
+
+	err = request_threaded_irq(irq_summary,
+				NULL,
+				sx150x_irq_thread_fn,
+				IRQF_SHARED | IRQF_TRIGGER_FALLING,
+				chip->irq_chip.name,
+				chip);
+	if (err < 0) {
+		chip->irq_summary = -1;
+		chip->irq_base    = -1;
+	}
+
+	return err;
+}
+
+static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
+{
+	unsigned n;
+	unsigned irq;
+
+	free_irq(chip->irq_summary, chip);
+
+	for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
+		irq = chip->irq_base + n;
+		set_irq_handler(irq, NULL);
+		set_irq_chip(irq, NULL);
+	}
+}
+
+static int __devinit sx150x_probe(struct i2c_client *client,
+				const struct i2c_device_id *id)
+{
+	static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
+				     I2C_FUNC_SMBUS_WRITE_WORD_DATA;
+	struct sx150x_platform_data *pdata;
+	struct sx150x_chip *chip;
+	int rc;
+
+	pdata = client->dev.platform_data;
+	if (!pdata)
+		return -EINVAL;
+
+	if (!i2c_check_functionality(client->adapter, i2c_funcs))
+		return -ENOSYS;
+
+	chip = kzalloc(sizeof(struct sx150x_chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	sx150x_init_chip(chip, client, id->driver_data, pdata);
+	rc = sx150x_init_hw(chip, pdata);
+	if (rc < 0)
+		goto probe_fail_pre_gpiochip_add;
+
+	rc = gpiochip_add(&chip->gpio_chip);
+	if (rc < 0)
+		goto probe_fail_pre_gpiochip_add;
+
+	if (pdata->irq_summary >= 0) {
+		rc = sx150x_install_irq_chip(chip,
+					pdata->irq_summary,
+					pdata->irq_base);
+		if (rc < 0)
+			goto probe_fail_post_gpiochip_add;
+	}
+
+	i2c_set_clientdata(client, chip);
+
+	return 0;
+probe_fail_post_gpiochip_add:
+	WARN_ON(gpiochip_remove(&chip->gpio_chip) < 0);
+probe_fail_pre_gpiochip_add:
+	kfree(chip);
+	return rc;
+}
+
+static int __devexit sx150x_remove(struct i2c_client *client)
+{
+	struct sx150x_chip *chip;
+	int rc;
+
+	chip = i2c_get_clientdata(client);
+	rc = gpiochip_remove(&chip->gpio_chip);
+	if (rc < 0)
+		return rc;
+
+	if (chip->irq_summary >= 0)
+		sx150x_remove_irq_chip(chip);
+
+	kfree(chip);
+
+	return 0;
+}
+
+static struct i2c_driver sx150x_driver = {
+	.driver = {
+		.name = "sx150x",
+		.owner = THIS_MODULE
+	},
+	.probe    = sx150x_probe,
+	.remove   = __devexit_p(sx150x_remove),
+	.id_table = sx150x_id,
+};
+
+static int __init sx150x_init(void)
+{
+	return i2c_add_driver(&sx150x_driver);
+}
+subsys_initcall(sx150x_init);
+
+static void __exit sx150x_exit(void)
+{
+	return i2c_del_driver(&sx150x_driver);
+}
+module_exit(sx150x_exit);
+
+MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
+MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("i2c:sx150x");
+/*
+ * Driver for the Semtech SX150x I2C GPIO Expanders
+ *
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __LINUX_I2C_SX150X_H
+#define __LINUX_I2C_SX150X_H
+
+/**
+ * struct sx150x_platform_data - config data for SX150x driver
+ * @gpio_base: The index number of the first GPIO assigned to this
+ *             GPIO expander.  The expander will create a block of
+ *             consecutively numbered gpios beginning at the given base,
+ *             with the size of the block depending on the model of the
+ *             expander chip.
+ * @oscio_is_gpo: If set to true, the driver will configure OSCIO as a GPO
+ *                instead of as an oscillator, increasing the size of the
+ *                GP(I)O pool created by this expander by one.  The
+ *                output-only GPO pin will be added at the end of the block.
+ * @io_pullup_ena: A bit-mask which enables or disables the pull-up resistor
+ *                 for each IO line in the expander.  Setting the bit at
+ *                 position n will enable the pull-up for the IO at
+ *                 the corresponding offset.  For chips with fewer than
+ *                 16 IO pins, high-end bits are ignored.
+ * @io_pulldn_ena: A bit-mask which enables-or disables the pull-down
+ *                 resistor for each IO line in the expander. Setting the
+ *                 bit at position n will enable the pull-down for the IO at
+ *                 the corresponding offset.  For chips with fewer than
+ *                 16 IO pins, high-end bits are ignored.
+ * @io_open_drain_ena: A bit-mask which enables-or disables open-drain
+ *                     operation for each IO line in the expander. Setting the
+ *                     bit at position n enables open-drain operation for
+ *                     the IO at the corresponding offset.  Clearing the bit
+ *                     enables regular push-pull operation for that IO.
+ *                     For chips with fewer than 16 IO pins, high-end bits
+ *                     are ignored.
+ * @io_polarity: A bit-mask which enables polarity inversion for each IO line
+ *               in the expander.  Setting the bit at position n inverts
+ *               the polarity of that IO line, while clearing it results
+ *               in normal polarity. For chips with fewer than 16 IO pins,
+ *               high-end bits are ignored.
+ * @irq_summary: The 'summary IRQ' line to which the GPIO expander's INT line
+ *               is connected, via which it reports interrupt events
+ *               across all GPIO lines.  This must be a real,
+ *               pre-existing IRQ line.
+ *               Setting this value < 0 disables the irq_chip functionality
+ *               of the driver.
+ * @irq_base: The first 'virtual IRQ' line at which our block of GPIO-based
+ *            IRQ lines will appear.  Similarly to gpio_base, the expander
+ *            will create a block of irqs beginning at this number.
+ *            This value is ignored if irq_summary is < 0.
+ */
+struct sx150x_platform_data {
+	unsigned gpio_base;
+	bool     oscio_is_gpo;
+	u16      io_pullup_ena;
+	u16      io_pulldn_ena;
+	u16      io_open_drain_ena;
+	u16      io_polarity;
+	int      irq_summary;
+	unsigned irq_base;
+};
+
+#endif /* __LINUX_I2C_SX150X_H */
...	...	@@ -195,6 +195,17 @@
195	195	This driver provides an in-kernel interface to those GPIOs using
196	196	platform-neutral GPIO calls.
197	197
	198	+config GPIO_SX150X
	199	+ bool "Semtech SX150x I2C GPIO expander"
	200	+ depends on I2C=y
	201	+ default n
	202	+ help
	203	+ Say yes here to provide support for Semtech SX150-series I2C
	204	+ GPIO expanders. Compatible models include:
	205	+
	206	+ 8 bits: sx1508q
	207	+ 16 bits: sx1509q
	208	+
198	209	config GPIO_TC35892
199	210	bool "TC35892 GPIOs"
200	211	depends on MFD_TC35892
...	...	@@ -35,4 +35,5 @@
35	35	obj-$(CONFIG_GPIO_SCH) += sch_gpio.o
36	36	obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o
37	37	obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
	38	+obj-$(CONFIG_GPIO_SX150X) += sx150x.o
	1	+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
	2	+ *
	3	+ * This program is free software; you can redistribute it and/or modify
	4	+ * it under the terms of the GNU General Public License version 2 and
	5	+ * only version 2 as published by the Free Software Foundation.
	6	+ *
	7	+ * This program is distributed in the hope that it will be useful,
	8	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	+ * GNU General Public License for more details.
	11	+ *
	12	+ * You should have received a copy of the GNU General Public License
	13	+ * along with this program; if not, write to the Free Software
	14	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	+ * 02110-1301, USA.
	16	+ */
	17	+#include <linux/gpio.h>
	18	+#include <linux/i2c.h>
	19	+#include <linux/init.h>
	20	+#include <linux/interrupt.h>
	21	+#include <linux/irq.h>
	22	+#include <linux/module.h>
	23	+#include <linux/mutex.h>
	24	+#include <linux/slab.h>
	25	+#include <linux/workqueue.h>
	26	+#include <linux/i2c/sx150x.h>
	27	+
	28	+struct sx150x_device_data {
	29	+ u8 reg_pullup;
	30	+ u8 reg_pulldn;
	31	+ u8 reg_drain;
	32	+ u8 reg_polarity;
	33	+ u8 reg_dir;
	34	+ u8 reg_data;
	35	+ u8 reg_irq_mask;
	36	+ u8 reg_irq_src;
	37	+ u8 reg_sense;
	38	+ u8 reg_clock;
	39	+ u8 reg_misc;
	40	+ u8 reg_reset;
	41	+ u8 ngpios;
	42	+};
	43	+
	44	+struct sx150x_chip {
	45	+ struct gpio_chip gpio_chip;
	46	+ struct i2c_client *client;
	47	+ const struct sx150x_device_data *dev_cfg;
	48	+ int irq_summary;
	49	+ int irq_base;
	50	+ u32 irq_sense;
	51	+ unsigned long irq_set_type_pending;
	52	+ struct irq_chip irq_chip;
	53	+ struct mutex lock;
	54	+};
	55	+
	56	+static const struct sx150x_device_data sx150x_devices[] = {
	57	+ [0] = { /* sx1508q */
	58	+ .reg_pullup = 0x03,
	59	+ .reg_pulldn = 0x04,
	60	+ .reg_drain = 0x05,
	61	+ .reg_polarity = 0x06,
	62	+ .reg_dir = 0x07,
	63	+ .reg_data = 0x08,
	64	+ .reg_irq_mask = 0x09,
	65	+ .reg_irq_src = 0x0c,
	66	+ .reg_sense = 0x0b,
	67	+ .reg_clock = 0x0f,
	68	+ .reg_misc = 0x10,
	69	+ .reg_reset = 0x7d,
	70	+ .ngpios = 8
	71	+ },
	72	+ [1] = { /* sx1509q */
	73	+ .reg_pullup = 0x07,
	74	+ .reg_pulldn = 0x09,
	75	+ .reg_drain = 0x0b,
	76	+ .reg_polarity = 0x0d,
	77	+ .reg_dir = 0x0f,
	78	+ .reg_data = 0x11,
	79	+ .reg_irq_mask = 0x13,
	80	+ .reg_irq_src = 0x19,
	81	+ .reg_sense = 0x17,
	82	+ .reg_clock = 0x1e,
	83	+ .reg_misc = 0x1f,
	84	+ .reg_reset = 0x7d,
	85	+ .ngpios = 16
	86	+ },
	87	+};
	88	+
	89	+static const struct i2c_device_id sx150x_id[] = {
	90	+ {"sx1508q", 0},
	91	+ {"sx1509q", 1},
	92	+ {}
	93	+};
	94	+MODULE_DEVICE_TABLE(i2c, sx150x_id);
	95	+
	96	+static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
	97	+{
	98	+ s32 err = i2c_smbus_write_byte_data(client, reg, val);
	99	+
	100	+ if (err < 0)
	101	+ dev_warn(&client->dev,
	102	+ "i2c write fail: can't write %02x to %02x: %d\n",
	103	+ val, reg, err);
	104	+ return err;
	105	+}
	106	+
	107	+static s32 sx150x_i2c_read(struct i2c_client client, u8 reg, u8 val)
	108	+{
	109	+ s32 err = i2c_smbus_read_byte_data(client, reg);
	110	+
	111	+ if (err >= 0)
	112	+ *val = err;
	113	+ else
	114	+ dev_warn(&client->dev,
	115	+ "i2c read fail: can't read from %02x: %d\n",
	116	+ reg, err);
	117	+ return err;
	118	+}
	119	+
	120	+static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
	121	+{
	122	+ return (chip->dev_cfg->ngpios == offset);
	123	+}
	124	+
	125	+/*
	126	+ * These utility functions solve the common problem of locating and setting
	127	+ * configuration bits. Configuration bits are grouped into registers
	128	+ * whose indexes increase downwards. For example, with eight-bit registers,
	129	+ * sixteen gpios would have their config bits grouped in the following order:
	130	+ * REGISTER N-1 [ f e d c b a 9 8 ]
	131	+ * N [ 7 6 5 4 3 2 1 0 ]
	132	+ *
	133	+ * For multi-bit configurations, the pattern gets wider:
	134	+ * REGISTER N-3 [ f f e e d d c c ]
	135	+ * N-2 [ b b a a 9 9 8 8 ]
	136	+ * N-1 [ 7 7 6 6 5 5 4 4 ]
	137	+ * N [ 3 3 2 2 1 1 0 0 ]
	138	+ *
	139	+ * Given the address of the starting register 'N', the index of the gpio
	140	+ * whose configuration we seek to change, and the width in bits of that
	141	+ * configuration, these functions allow us to locate the correct
	142	+ * register and mask the correct bits.
	143	+ */
	144	+static inline void sx150x_find_cfg(u8 offset, u8 width,
	145	+ u8 reg, u8 mask, u8 *shift)
	146	+{
	147	+ reg -= offset width / 8;
	148	+ *mask = (1 << width) - 1;
	149	+ shift = (offset width) % 8;
	150	+ mask <<= shift;
	151	+}
	152	+
	153	+static s32 sx150x_write_cfg(struct sx150x_chip *chip,
	154	+ u8 offset, u8 width, u8 reg, u8 val)
	155	+{
	156	+ u8 mask;
	157	+ u8 data;
	158	+ u8 shift;
	159	+ s32 err;
	160	+
	161	+ sx150x_find_cfg(offset, width, &reg, &mask, &shift);
	162	+ err = sx150x_i2c_read(chip->client, reg, &data);
	163	+ if (err < 0)
	164	+ return err;
	165	+
	166	+ data &= ~mask;
	167	+ data \|= (val << shift) & mask;
	168	+ return sx150x_i2c_write(chip->client, reg, data);
	169	+}
	170	+
	171	+static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
	172	+{
	173	+ u8 reg = chip->dev_cfg->reg_data;
	174	+ u8 mask;
	175	+ u8 data;
	176	+ u8 shift;
	177	+ s32 err;
	178	+
	179	+ sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
	180	+ err = sx150x_i2c_read(chip->client, reg, &data);
	181	+ if (err >= 0)
	182	+ err = (data & mask) != 0 ? 1 : 0;
	183	+
	184	+ return err;
	185	+}
	186	+
	187	+static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
	188	+{
	189	+ sx150x_i2c_write(chip->client,
	190	+ chip->dev_cfg->reg_clock,
	191	+ (val ? 0x1f : 0x10));
	192	+}
	193	+
	194	+static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
	195	+{
	196	+ sx150x_write_cfg(chip,
	197	+ offset,
	198	+ 1,
	199	+ chip->dev_cfg->reg_data,
	200	+ (val ? 1 : 0));
	201	+}
	202	+
	203	+static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
	204	+{
	205	+ return sx150x_write_cfg(chip,
	206	+ offset,
	207	+ 1,
	208	+ chip->dev_cfg->reg_dir,
	209	+ 1);
	210	+}
	211	+
	212	+static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
	213	+{
	214	+ int err;
	215	+
	216	+ err = sx150x_write_cfg(chip,
	217	+ offset,
	218	+ 1,
	219	+ chip->dev_cfg->reg_data,
	220	+ (val ? 1 : 0));
	221	+ if (err >= 0)
	222	+ err = sx150x_write_cfg(chip,
	223	+ offset,
	224	+ 1,
	225	+ chip->dev_cfg->reg_dir,
	226	+ 0);
	227	+ return err;
	228	+}
	229	+
	230	+static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
	231	+{
	232	+ struct sx150x_chip *chip;
	233	+ int status = -EINVAL;
	234	+
	235	+ chip = container_of(gc, struct sx150x_chip, gpio_chip);
	236	+
	237	+ if (!offset_is_oscio(chip, offset)) {
	238	+ mutex_lock(&chip->lock);
	239	+ status = sx150x_get_io(chip, offset);
	240	+ mutex_unlock(&chip->lock);
	241	+ }
	242	+
	243	+ return status;
	244	+}
	245	+
	246	+static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
	247	+{
	248	+ struct sx150x_chip *chip;
	249	+
	250	+ chip = container_of(gc, struct sx150x_chip, gpio_chip);
	251	+
	252	+ mutex_lock(&chip->lock);
	253	+ if (offset_is_oscio(chip, offset))
	254	+ sx150x_set_oscio(chip, val);
	255	+ else
	256	+ sx150x_set_io(chip, offset, val);
	257	+ mutex_unlock(&chip->lock);
	258	+}
	259	+
	260	+static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
	261	+{
	262	+ struct sx150x_chip *chip;
	263	+ int status = -EINVAL;
	264	+
	265	+ chip = container_of(gc, struct sx150x_chip, gpio_chip);
	266	+
	267	+ if (!offset_is_oscio(chip, offset)) {
	268	+ mutex_lock(&chip->lock);
	269	+ status = sx150x_io_input(chip, offset);
	270	+ mutex_unlock(&chip->lock);
	271	+ }
	272	+ return status;
	273	+}
	274	+
	275	+static int sx150x_gpio_direction_output(struct gpio_chip *gc,
	276	+ unsigned offset,
	277	+ int val)
	278	+{
	279	+ struct sx150x_chip *chip;
	280	+ int status = 0;
	281	+
	282	+ chip = container_of(gc, struct sx150x_chip, gpio_chip);
	283	+
	284	+ if (!offset_is_oscio(chip, offset)) {
	285	+ mutex_lock(&chip->lock);
	286	+ status = sx150x_io_output(chip, offset, val);
	287	+ mutex_unlock(&chip->lock);
	288	+ }
	289	+ return status;
	290	+}
	291	+
	292	+static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
	293	+{
	294	+ struct sx150x_chip *chip;
	295	+
	296	+ chip = container_of(gc, struct sx150x_chip, gpio_chip);
	297	+
	298	+ if (offset >= chip->dev_cfg->ngpios)
	299	+ return -EINVAL;
	300	+
	301	+ if (chip->irq_base < 0)
	302	+ return -EINVAL;
	303	+
	304	+ return chip->irq_base + offset;
	305	+}
	306	+
	307	+static void sx150x_irq_mask(unsigned int irq)
	308	+{
	309	+ struct irq_chip *ic = get_irq_chip(irq);
	310	+ struct sx150x_chip *chip;
	311	+ unsigned n;
	312	+
	313	+ chip = container_of(ic, struct sx150x_chip, irq_chip);
	314	+ n = irq - chip->irq_base;
	315	+
	316	+ sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
	317	+ sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
	318	+}
	319	+
	320	+static void sx150x_irq_unmask(unsigned int irq)
	321	+{
	322	+ struct irq_chip *ic = get_irq_chip(irq);
	323	+ struct sx150x_chip *chip;
	324	+ unsigned n;
	325	+
	326	+ chip = container_of(ic, struct sx150x_chip, irq_chip);
	327	+ n = irq - chip->irq_base;
	328	+
	329	+ sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
	330	+ sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
	331	+ chip->irq_sense >> (n * 2));
	332	+}
	333	+
	334	+static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type)
	335	+{
	336	+ struct irq_chip *ic = get_irq_chip(irq);
	337	+ struct sx150x_chip *chip;
	338	+ unsigned n, val = 0;
	339	+
	340	+ if (flow_type & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	341	+ return -EINVAL;
	342	+
	343	+ chip = container_of(ic, struct sx150x_chip, irq_chip);
	344	+ n = irq - chip->irq_base;
	345	+
	346	+ if (flow_type & IRQ_TYPE_EDGE_RISING)
	347	+ val \|= 0x1;
	348	+ if (flow_type & IRQ_TYPE_EDGE_FALLING)
	349	+ val \|= 0x2;
	350	+
	351	+ chip->irq_sense &= ~(3UL << (n * 2));
	352	+ chip->irq_sense \|= val << (n * 2);
	353	+ chip->irq_set_type_pending \|= BIT(n);
	354	+ return 0;
	355	+}
	356	+
	357	+static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
	358	+{
	359	+ struct sx150x_chip chip = (struct sx150x_chip )dev_id;
	360	+ unsigned nhandled = 0;
	361	+ unsigned sub_irq;
	362	+ unsigned n;
	363	+ s32 err;
	364	+ u8 val;
	365	+ int i;
	366	+
	367	+ for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
	368	+ err = sx150x_i2c_read(chip->client,
	369	+ chip->dev_cfg->reg_irq_src - i,
	370	+ &val);
	371	+ if (err < 0)
	372	+ continue;
	373	+
	374	+ sx150x_i2c_write(chip->client,
	375	+ chip->dev_cfg->reg_irq_src - i,
	376	+ val);
	377	+ for (n = 0; n < 8; ++n) {
	378	+ if (val & (1 << n)) {
	379	+ sub_irq = chip->irq_base + (i * 8) + n;
	380	+ handle_nested_irq(sub_irq);
	381	+ ++nhandled;
	382	+ }
	383	+ }
	384	+ }
	385	+
	386	+ return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
	387	+}
	388	+
	389	+static void sx150x_irq_bus_lock(unsigned int irq)
	390	+{
	391	+ struct irq_chip *ic = get_irq_chip(irq);
	392	+ struct sx150x_chip *chip;
	393	+
	394	+ chip = container_of(ic, struct sx150x_chip, irq_chip);
	395	+
	396	+ mutex_lock(&chip->lock);
	397	+}
	398	+
	399	+static void sx150x_irq_bus_sync_unlock(unsigned int irq)
	400	+{
	401	+ struct irq_chip *ic = get_irq_chip(irq);
	402	+ struct sx150x_chip *chip;
	403	+ unsigned n;
	404	+
	405	+ chip = container_of(ic, struct sx150x_chip, irq_chip);
	406	+
	407	+ while (chip->irq_set_type_pending) {
	408	+ n = __ffs(chip->irq_set_type_pending);
	409	+ chip->irq_set_type_pending &= ~BIT(n);
	410	+ if (!(irq_to_desc(n + chip->irq_base)->status & IRQ_MASKED))
	411	+ sx150x_write_cfg(chip, n, 2,
	412	+ chip->dev_cfg->reg_sense,
	413	+ chip->irq_sense >> (n * 2));
	414	+ }
	415	+
	416	+ mutex_unlock(&chip->lock);
	417	+}
	418	+
	419	+static void sx150x_init_chip(struct sx150x_chip *chip,
	420	+ struct i2c_client *client,
	421	+ kernel_ulong_t driver_data,
	422	+ struct sx150x_platform_data *pdata)
	423	+{
	424	+ mutex_init(&chip->lock);
	425	+
	426	+ chip->client = client;
	427	+ chip->dev_cfg = &sx150x_devices[driver_data];
	428	+ chip->gpio_chip.label = client->name;
	429	+ chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
	430	+ chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
	431	+ chip->gpio_chip.get = sx150x_gpio_get;
	432	+ chip->gpio_chip.set = sx150x_gpio_set;
	433	+ chip->gpio_chip.to_irq = sx150x_gpio_to_irq;
	434	+ chip->gpio_chip.base = pdata->gpio_base;
	435	+ chip->gpio_chip.can_sleep = 1;
	436	+ chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
	437	+ if (pdata->oscio_is_gpo)
	438	+ ++chip->gpio_chip.ngpio;
	439	+
	440	+ chip->irq_chip.name = client->name;
	441	+ chip->irq_chip.mask = sx150x_irq_mask;
	442	+ chip->irq_chip.unmask = sx150x_irq_unmask;
	443	+ chip->irq_chip.set_type = sx150x_irq_set_type;
	444	+ chip->irq_chip.bus_lock = sx150x_irq_bus_lock;
	445	+ chip->irq_chip.bus_sync_unlock = sx150x_irq_bus_sync_unlock;
	446	+ chip->irq_summary = -1;
	447	+ chip->irq_base = -1;
	448	+ chip->irq_sense = 0;
	449	+ chip->irq_set_type_pending = 0;
	450	+}
	451	+
	452	+static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
	453	+{
	454	+ int err = 0;
	455	+ unsigned n;
	456	+
	457	+ for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
	458	+ err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
	459	+ return err;
	460	+}
	461	+
	462	+static int sx150x_init_hw(struct sx150x_chip *chip,
	463	+ struct sx150x_platform_data *pdata)
	464	+{
	465	+ int err = 0;
	466	+
	467	+ err = i2c_smbus_write_word_data(chip->client,
	468	+ chip->dev_cfg->reg_reset,
	469	+ 0x3412);
	470	+ if (err < 0)
	471	+ return err;
	472	+
	473	+ err = sx150x_i2c_write(chip->client,
	474	+ chip->dev_cfg->reg_misc,
	475	+ 0x01);
	476	+ if (err < 0)
	477	+ return err;
	478	+
	479	+ err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
	480	+ pdata->io_pullup_ena);
	481	+ if (err < 0)
	482	+ return err;
	483	+
	484	+ err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
	485	+ pdata->io_pulldn_ena);
	486	+ if (err < 0)
	487	+ return err;
	488	+
	489	+ err = sx150x_init_io(chip, chip->dev_cfg->reg_drain,
	490	+ pdata->io_open_drain_ena);
	491	+ if (err < 0)
	492	+ return err;
	493	+
	494	+ err = sx150x_init_io(chip, chip->dev_cfg->reg_polarity,
	495	+ pdata->io_polarity);
	496	+ if (err < 0)
	497	+ return err;
	498	+
	499	+ if (pdata->oscio_is_gpo)
	500	+ sx150x_set_oscio(chip, 0);
	501	+
	502	+ return err;
	503	+}
	504	+
	505	+static int sx150x_install_irq_chip(struct sx150x_chip *chip,
	506	+ int irq_summary,
	507	+ int irq_base)
	508	+{
	509	+ int err;
	510	+ unsigned n;
	511	+ unsigned irq;
	512	+
	513	+ chip->irq_summary = irq_summary;
	514	+ chip->irq_base = irq_base;
	515	+
	516	+ for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
	517	+ irq = irq_base + n;
	518	+ set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
	519	+ set_irq_nested_thread(irq, 1);
	520	+#ifdef CONFIG_ARM
	521	+ set_irq_flags(irq, IRQF_VALID);
	522	+#else
	523	+ set_irq_noprobe(irq);
	524	+#endif
	525	+ }
	526	+
	527	+ err = request_threaded_irq(irq_summary,
	528	+ NULL,
	529	+ sx150x_irq_thread_fn,
	530	+ IRQF_SHARED \| IRQF_TRIGGER_FALLING,
	531	+ chip->irq_chip.name,
	532	+ chip);
	533	+ if (err < 0) {
	534	+ chip->irq_summary = -1;
	535	+ chip->irq_base = -1;
	536	+ }
	537	+
	538	+ return err;
	539	+}
	540	+
	541	+static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
	542	+{
	543	+ unsigned n;
	544	+ unsigned irq;
	545	+
	546	+ free_irq(chip->irq_summary, chip);
	547	+
	548	+ for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
	549	+ irq = chip->irq_base + n;
	550	+ set_irq_handler(irq, NULL);
	551	+ set_irq_chip(irq, NULL);
	552	+ }
	553	+}
	554	+
	555	+static int __devinit sx150x_probe(struct i2c_client *client,
	556	+ const struct i2c_device_id *id)
	557	+{
	558	+ static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA \|
	559	+ I2C_FUNC_SMBUS_WRITE_WORD_DATA;
	560	+ struct sx150x_platform_data *pdata;
	561	+ struct sx150x_chip *chip;
	562	+ int rc;
	563	+
	564	+ pdata = client->dev.platform_data;
	565	+ if (!pdata)
	566	+ return -EINVAL;
	567	+
	568	+ if (!i2c_check_functionality(client->adapter, i2c_funcs))
	569	+ return -ENOSYS;
	570	+
	571	+ chip = kzalloc(sizeof(struct sx150x_chip), GFP_KERNEL);
	572	+ if (!chip)
	573	+ return -ENOMEM;
	574	+
	575	+ sx150x_init_chip(chip, client, id->driver_data, pdata);
	576	+ rc = sx150x_init_hw(chip, pdata);
	577	+ if (rc < 0)
	578	+ goto probe_fail_pre_gpiochip_add;
	579	+
	580	+ rc = gpiochip_add(&chip->gpio_chip);
	581	+ if (rc < 0)
	582	+ goto probe_fail_pre_gpiochip_add;
	583	+
	584	+ if (pdata->irq_summary >= 0) {
	585	+ rc = sx150x_install_irq_chip(chip,
	586	+ pdata->irq_summary,
	587	+ pdata->irq_base);
	588	+ if (rc < 0)
	589	+ goto probe_fail_post_gpiochip_add;
	590	+ }
	591	+
	592	+ i2c_set_clientdata(client, chip);
	593	+
	594	+ return 0;
	595	+probe_fail_post_gpiochip_add:
	596	+ WARN_ON(gpiochip_remove(&chip->gpio_chip) < 0);
	597	+probe_fail_pre_gpiochip_add:
	598	+ kfree(chip);
	599	+ return rc;
	600	+}
	601	+
	602	+static int __devexit sx150x_remove(struct i2c_client *client)
	603	+{
	604	+ struct sx150x_chip *chip;
	605	+ int rc;
	606	+
	607	+ chip = i2c_get_clientdata(client);
	608	+ rc = gpiochip_remove(&chip->gpio_chip);
	609	+ if (rc < 0)
	610	+ return rc;
	611	+
	612	+ if (chip->irq_summary >= 0)
	613	+ sx150x_remove_irq_chip(chip);
	614	+
	615	+ kfree(chip);
	616	+
	617	+ return 0;
	618	+}
	619	+
	620	+static struct i2c_driver sx150x_driver = {
	621	+ .driver = {
	622	+ .name = "sx150x",
	623	+ .owner = THIS_MODULE
	624	+ },
	625	+ .probe = sx150x_probe,
	626	+ .remove = __devexit_p(sx150x_remove),
	627	+ .id_table = sx150x_id,
	628	+};
	629	+
	630	+static int __init sx150x_init(void)
	631	+{
	632	+ return i2c_add_driver(&sx150x_driver);
	633	+}
	634	+subsys_initcall(sx150x_init);
	635	+
	636	+static void __exit sx150x_exit(void)
	637	+{
	638	+ return i2c_del_driver(&sx150x_driver);
	639	+}
	640	+module_exit(sx150x_exit);
	641	+
	642	+MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
	643	+MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
	644	+MODULE_LICENSE("GPL v2");
	645	+MODULE_ALIAS("i2c:sx150x");
	1	+/*
	2	+ * Driver for the Semtech SX150x I2C GPIO Expanders
	3	+ *
	4	+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License version 2 and
	8	+ * only version 2 as published by the Free Software Foundation.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	18	+ * 02110-1301, USA.
	19	+ */
	20	+#ifndef __LINUX_I2C_SX150X_H
	21	+#define __LINUX_I2C_SX150X_H
	22	+
	23	+/**
	24	+ * struct sx150x_platform_data - config data for SX150x driver
	25	+ * @gpio_base: The index number of the first GPIO assigned to this
	26	+ * GPIO expander. The expander will create a block of
	27	+ * consecutively numbered gpios beginning at the given base,
	28	+ * with the size of the block depending on the model of the
	29	+ * expander chip.
	30	+ * @oscio_is_gpo: If set to true, the driver will configure OSCIO as a GPO
	31	+ * instead of as an oscillator, increasing the size of the
	32	+ * GP(I)O pool created by this expander by one. The
	33	+ * output-only GPO pin will be added at the end of the block.
	34	+ * @io_pullup_ena: A bit-mask which enables or disables the pull-up resistor
	35	+ * for each IO line in the expander. Setting the bit at
	36	+ * position n will enable the pull-up for the IO at
	37	+ * the corresponding offset. For chips with fewer than
	38	+ * 16 IO pins, high-end bits are ignored.
	39	+ * @io_pulldn_ena: A bit-mask which enables-or disables the pull-down
	40	+ * resistor for each IO line in the expander. Setting the
	41	+ * bit at position n will enable the pull-down for the IO at
	42	+ * the corresponding offset. For chips with fewer than
	43	+ * 16 IO pins, high-end bits are ignored.
	44	+ * @io_open_drain_ena: A bit-mask which enables-or disables open-drain
	45	+ * operation for each IO line in the expander. Setting the
	46	+ * bit at position n enables open-drain operation for
	47	+ * the IO at the corresponding offset. Clearing the bit
	48	+ * enables regular push-pull operation for that IO.
	49	+ * For chips with fewer than 16 IO pins, high-end bits
	50	+ * are ignored.
	51	+ * @io_polarity: A bit-mask which enables polarity inversion for each IO line
	52	+ * in the expander. Setting the bit at position n inverts
	53	+ * the polarity of that IO line, while clearing it results
	54	+ * in normal polarity. For chips with fewer than 16 IO pins,
	55	+ * high-end bits are ignored.
	56	+ * @irq_summary: The 'summary IRQ' line to which the GPIO expander's INT line
	57	+ * is connected, via which it reports interrupt events
	58	+ * across all GPIO lines. This must be a real,
	59	+ * pre-existing IRQ line.
	60	+ * Setting this value < 0 disables the irq_chip functionality
	61	+ * of the driver.
	62	+ * @irq_base: The first 'virtual IRQ' line at which our block of GPIO-based
	63	+ * IRQ lines will appear. Similarly to gpio_base, the expander
	64	+ * will create a block of irqs beginning at this number.
	65	+ * This value is ignored if irq_summary is < 0.
	66	+ */
	67	+struct sx150x_platform_data {
	68	+ unsigned gpio_base;
	69	+ bool oscio_is_gpo;
	70	+ u16 io_pullup_ena;
	71	+ u16 io_pulldn_ena;
	72	+ u16 io_open_drain_ena;
	73	+ u16 io_polarity;
	74	+ int irq_summary;
	75	+ unsigned irq_base;
	76	+};
	77	+
	78	+#endif /* __LINUX_I2C_SX150X_H */