PCI PM: PCIe PME root port service driver

PCIe native PME detection mechanism is based on interrupts generated by root ports or event collectors every time a PCIe device sends a PME message upstream. Once a PME message has been sent by an endpoint device and received by its root port (or event collector in the case of root complex integrated endpoints), the Requester ID from the message header is registered in the root port's Root Status register. At the same time, the PME Status bit of the Root Status register is set to indicate that there's a PME to handle. If PCIe PME interrupt is enabled for the root port, it generates an interrupt once the PME Status has been set. After receiving the interrupt, the kernel can identify the PCIe device that generated the PME using the Requester ID from the root port's Root Status register. [For details, see PCI Express Base Specification, Rev. 2.0.] Implement a driver for the PCIe PME root port service working in accordance with the above description. Based on a patch from Shaohua Li <shaohua.li@intel.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

PCI PM: PCIe PME root port service driver
PCIe native PME detection mechanism is based on interrupts generated by root ports or event collectors every time a PCIe device sends a PME message upstream. Once a PME message has been sent by an endpoint device and received by its root port (or event collector in the case of root complex integrated endpoints), the Requester ID from the message header is registered in the root port's Root Status register. At the same time, the PME Status bit of the Root Status register is set to indicate that there's a PME to handle. If PCIe PME interrupt is enabled for the root port, it generates an interrupt once the PME Status has been set. After receiving the interrupt, the kernel can identify the PCIe device that generated the PME using the Requester ID from the root port's Root Status register. [For details, see PCI Express Base Specification, Rev. 2.0.] Implement a driver for the PCIe PME root port service working in accordance with the above description. Based on a patch from Shaohua Li <shaohua.li@intel.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Rafael J. Wysocki · Jesse Barnes
1 parent 58ff463396
Showing 8 changed files with 596 additions and 0 deletions Side-by-side Diff
Documentation/kernel-parameters.txt
drivers/pci/pcie/Kconfig
drivers/pci/pcie/Makefile
drivers/pci/pcie/pme/Makefile
drivers/pci/pcie/pme/pcie_pme.c
drivers/pci/pcie/pme/pcie_pme.h
drivers/pci/pcie/pme/pcie_pme_acpi.c
include/linux/pci.h
@@ -1998,6 +1998,12 @@
 		force	Enable ASPM even on devices that claim not to support it.
 			WARNING: Forcing ASPM on may cause system lockups.
  
+	pcie_pme=	[PCIE,PM] Native PCIe PME signaling options:
+		off	Do not use native PCIe PME signaling.
+		force	Use native PCIe PME signaling even if the BIOS refuses
+			to allow the kernel to control the relevant PCIe config
+			registers.
+
 	pcmv=		[HW,PCMCIA] BadgePAD 4
  
 	pd.		[PARIDE]
@@ -46,4 +46,8 @@
 	help
 	  This enables PCI Express ASPM debug support. It will add per-device
 	  interface to control ASPM.
+
+config PCIE_PME
+	def_bool y
+	depends on PCIEPORTBUS && PM_RUNTIME && EXPERIMENTAL && ACPI
@@ -11,4 +11,6 @@
  
 # Build PCI Express AER if needed
 obj-$(CONFIG_PCIEAER)		+= aer/
+
+obj-$(CONFIG_PCIE_PME) += pme/
+#
+# Makefile for PCI-Express Root Port PME signaling driver
+#
+
+obj-$(CONFIG_PCIE_PME) += pmedriver.o
+
+pmedriver-objs := pcie_pme.o
+pmedriver-$(CONFIG_ACPI) += pcie_pme_acpi.o
+/*
+ * PCIe Native PME support
+ *
+ * Copyright (C) 2007 - 2009 Intel Corp
+ * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License V2.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/pcieport_if.h>
+#include <linux/acpi.h>
+#include <linux/pci-acpi.h>
+#include <linux/pm_runtime.h>
+
+#include "../../pci.h"
+#include "pcie_pme.h"
+
+#define PCI_EXP_RTSTA_PME	0x10000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING	0x20000 /* PME pending */
+
+/*
+ * If set, this switch will prevent the PCIe root port PME service driver from
+ * being registered.  Consequently, the interrupt-based PCIe PME signaling will
+ * not be used by any PCIe root ports in that case.
+ */
+static bool pcie_pme_disabled;
+
+/*
+ * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
+ * "In order to maintain compatibility with non-PCI Express-aware system
+ * software, system power management logic must be configured by firmware to use
+ * the legacy mechanism of signaling PME by default.  PCI Express-aware system
+ * software must notify the firmware prior to enabling native, interrupt-based
+ * PME signaling."  However, if the platform doesn't provide us with a suitable
+ * notification mechanism or the notification fails, it is not clear whether or
+ * not we are supposed to use the interrupt-based PCIe PME signaling.  The
+ * switch below can be used to indicate the desired behaviour.  When set, it
+ * will make the kernel use the interrupt-based PCIe PME signaling regardless of
+ * the platform notification status, although the kernel will attempt to notify
+ * the platform anyway.  When unset, it will prevent the kernel from using the
+ * the interrupt-based PCIe PME signaling if the platform notification fails,
+ * which is the default.
+ */
+static bool pcie_pme_force_enable;
+
+static int __init pcie_pme_setup(char *str)
+{
+	if (!strcmp(str, "off"))
+		pcie_pme_disabled = true;
+	else if (!strcmp(str, "force"))
+		pcie_pme_force_enable = true;
+	return 1;
+}
+__setup("pcie_pme=", pcie_pme_setup);
+
+/**
+ * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
+ * @srv: PCIe PME root port service to use for carrying out the check.
+ *
+ * Notify the platform that the native PCIe PME is going to be used and return
+ * 'true' if the control of the PCIe PME registers has been acquired from the
+ * platform.
+ */
+static bool pcie_pme_platform_setup(struct pcie_device *srv)
+{
+	return !pcie_pme_platform_notify(srv) || pcie_pme_force_enable;
+}
+
+struct pcie_pme_service_data {
+	spinlock_t lock;
+	struct pcie_device *srv;
+	struct work_struct work;
+	bool noirq; /* Don't enable the PME interrupt used by this service. */
+};
+
+/**
+ * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
+ * @dev: PCIe root port or event collector.
+ * @enable: Enable or disable the interrupt.
+ */
+static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
+{
+	int rtctl_pos;
+	u16 rtctl;
+
+	rtctl_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTCTL;
+
+	pci_read_config_word(dev, rtctl_pos, &rtctl);
+	if (enable)
+		rtctl |= PCI_EXP_RTCTL_PMEIE;
+	else
+		rtctl &= ~PCI_EXP_RTCTL_PMEIE;
+	pci_write_config_word(dev, rtctl_pos, rtctl);
+}
+
+/**
+ * pcie_pme_clear_status - Clear root port PME interrupt status.
+ * @dev: PCIe root port or event collector.
+ */
+static void pcie_pme_clear_status(struct pci_dev *dev)
+{
+	int rtsta_pos;
+	u32 rtsta;
+
+	rtsta_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
+
+	pci_read_config_dword(dev, rtsta_pos, &rtsta);
+	rtsta |= PCI_EXP_RTSTA_PME;
+	pci_write_config_dword(dev, rtsta_pos, rtsta);
+}
+
+/**
+ * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
+ * @bus: PCI bus to scan.
+ *
+ * Scan given PCI bus and all buses under it for devices asserting PME#.
+ */
+static bool pcie_pme_walk_bus(struct pci_bus *bus)
+{
+	struct pci_dev *dev;
+	bool ret = false;
+
+	list_for_each_entry(dev, &bus->devices, bus_list) {
+		/* Skip PCIe devices in case we started from a root port. */
+		if (!dev->is_pcie && pci_check_pme_status(dev)) {
+			pm_request_resume(&dev->dev);
+			ret = true;
+		}
+
+		if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
+			ret = true;
+	}
+
+	return ret;
+}
+
+/**
+ * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
+ * @bus: Secondary bus of the bridge.
+ * @devfn: Device/function number to check.
+ *
+ * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
+ * PCIe PME message.  In such that case the bridge should use the Requester ID
+ * of device/function number 0 on its secondary bus.
+ */
+static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
+{
+	struct pci_dev *dev;
+	bool found = false;
+
+	if (devfn)
+		return false;
+
+	dev = pci_dev_get(bus->self);
+	if (!dev)
+		return false;
+
+	if (dev->is_pcie && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+		down_read(&pci_bus_sem);
+		if (pcie_pme_walk_bus(bus))
+			found = true;
+		up_read(&pci_bus_sem);
+	}
+
+	pci_dev_put(dev);
+	return found;
+}
+
+/**
+ * pcie_pme_handle_request - Find device that generated PME and handle it.
+ * @port: Root port or event collector that generated the PME interrupt.
+ * @req_id: PCIe Requester ID of the device that generated the PME.
+ */
+static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
+{
+	u8 busnr = req_id >> 8, devfn = req_id & 0xff;
+	struct pci_bus *bus;
+	struct pci_dev *dev;
+	bool found = false;
+
+	/* First, check if the PME is from the root port itself. */
+	if (port->devfn == devfn && port->bus->number == busnr) {
+		if (pci_check_pme_status(port)) {
+			pm_request_resume(&port->dev);
+			found = true;
+		} else {
+			/*
+			 * Apparently, the root port generated the PME on behalf
+			 * of a non-PCIe device downstream.  If this is done by
+			 * a root port, the Requester ID field in its status
+			 * register may contain either the root port's, or the
+			 * source device's information (PCI Express Base
+			 * Specification, Rev. 2.0, Section 6.1.9).
+			 */
+			down_read(&pci_bus_sem);
+			found = pcie_pme_walk_bus(port->subordinate);
+			up_read(&pci_bus_sem);
+		}
+		goto out;
+	}
+
+	/* Second, find the bus the source device is on. */
+	bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
+	if (!bus)
+		goto out;
+
+	/* Next, check if the PME is from a PCIe-PCI bridge. */
+	found = pcie_pme_from_pci_bridge(bus, devfn);
+	if (found)
+		goto out;
+
+	/* Finally, try to find the PME source on the bus. */
+	down_read(&pci_bus_sem);
+	list_for_each_entry(dev, &bus->devices, bus_list) {
+		pci_dev_get(dev);
+		if (dev->devfn == devfn) {
+			found = true;
+			break;
+		}
+		pci_dev_put(dev);
+	}
+	up_read(&pci_bus_sem);
+
+	if (found) {
+		/* The device is there, but we have to check its PME status. */
+		found = pci_check_pme_status(dev);
+		if (found)
+			pm_request_resume(&dev->dev);
+		pci_dev_put(dev);
+	} else if (devfn) {
+		/*
+		 * The device is not there, but we can still try to recover by
+		 * assuming that the PME was reported by a PCIe-PCI bridge that
+		 * used devfn different from zero.
+		 */
+		dev_dbg(&port->dev, "PME interrupt generated for "
+			"non-existent device %02x:%02x.%d\n",
+			busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
+		found = pcie_pme_from_pci_bridge(bus, 0);
+	}
+
+ out:
+	if (!found)
+		dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
+}
+
+/**
+ * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
+ * @work: Work structure giving access to service data.
+ */
+static void pcie_pme_work_fn(struct work_struct *work)
+{
+	struct pcie_pme_service_data *data =
+			container_of(work, struct pcie_pme_service_data, work);
+	struct pci_dev *port = data->srv->port;
+	int rtsta_pos;
+	u32 rtsta;
+
+	rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
+
+	spin_lock_irq(&data->lock);
+
+	for (;;) {
+		if (data->noirq)
+			break;
+
+		pci_read_config_dword(port, rtsta_pos, &rtsta);
+		if (rtsta & PCI_EXP_RTSTA_PME) {
+			/*
+			 * Clear PME status of the port.  If there are other
+			 * pending PMEs, the status will be set again.
+			 */
+			pcie_pme_clear_status(port);
+
+			spin_unlock_irq(&data->lock);
+			pcie_pme_handle_request(port, rtsta & 0xffff);
+			spin_lock_irq(&data->lock);
+
+			continue;
+		}
+
+		/* No need to loop if there are no more PMEs pending. */
+		if (!(rtsta & PCI_EXP_RTSTA_PENDING))
+			break;
+
+		spin_unlock_irq(&data->lock);
+		cpu_relax();
+		spin_lock_irq(&data->lock);
+	}
+
+	if (!data->noirq)
+		pcie_pme_interrupt_enable(port, true);
+
+	spin_unlock_irq(&data->lock);
+}
+
+/**
+ * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
+ * @irq: Interrupt vector.
+ * @context: Interrupt context pointer.
+ */
+static irqreturn_t pcie_pme_irq(int irq, void *context)
+{
+	struct pci_dev *port;
+	struct pcie_pme_service_data *data;
+	int rtsta_pos;
+	u32 rtsta;
+	unsigned long flags;
+
+	port = ((struct pcie_device *)context)->port;
+	data = get_service_data((struct pcie_device *)context);
+
+	rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
+
+	spin_lock_irqsave(&data->lock, flags);
+	pci_read_config_dword(port, rtsta_pos, &rtsta);
+
+	if (!(rtsta & PCI_EXP_RTSTA_PME)) {
+		spin_unlock_irqrestore(&data->lock, flags);
+		return IRQ_NONE;
+	}
+
+	pcie_pme_interrupt_enable(port, false);
+	spin_unlock_irqrestore(&data->lock, flags);
+
+	/* We don't use pm_wq, because it's freezable. */
+	schedule_work(&data->work);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * pcie_pme_set_native - Set the PME interrupt flag for given device.
+ * @dev: PCI device to handle.
+ * @ign: Ignored.
+ */
+static int pcie_pme_set_native(struct pci_dev *dev, void *ign)
+{
+	dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
+
+	device_set_run_wake(&dev->dev, true);
+	dev->pme_interrupt = true;
+	return 0;
+}
+
+/**
+ * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
+ * @port: PCIe root port or event collector to handle.
+ *
+ * For each device below given root port, including the port itself (or for each
+ * root complex integrated endpoint if @port is a root complex event collector)
+ * set the flag indicating that it can signal run-time wake-up events via PCIe
+ * PME interrupts.
+ */
+static void pcie_pme_mark_devices(struct pci_dev *port)
+{
+	pcie_pme_set_native(port, NULL);
+	if (port->subordinate) {
+		pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
+	} else {
+		struct pci_bus *bus = port->bus;
+		struct pci_dev *dev;
+
+		/* Check if this is a root port event collector. */
+		if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
+			return;
+
+		down_read(&pci_bus_sem);
+		list_for_each_entry(dev, &bus->devices, bus_list)
+			if (dev->is_pcie
+			    && dev->pcie_type == PCI_EXP_TYPE_RC_END)
+				pcie_pme_set_native(dev, NULL);
+		up_read(&pci_bus_sem);
+	}
+}
+
+/**
+ * pcie_pme_probe - Initialize PCIe PME service for given root port.
+ * @srv: PCIe service to initialize.
+ */
+static int pcie_pme_probe(struct pcie_device *srv)
+{
+	struct pci_dev *port;
+	struct pcie_pme_service_data *data;
+	int ret;
+
+	if (!pcie_pme_platform_setup(srv))
+		return -EACCES;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	spin_lock_init(&data->lock);
+	INIT_WORK(&data->work, pcie_pme_work_fn);
+	data->srv = srv;
+	set_service_data(srv, data);
+
+	port = srv->port;
+	pcie_pme_interrupt_enable(port, false);
+	pcie_pme_clear_status(port);
+
+	ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
+	if (ret) {
+		kfree(data);
+	} else {
+		pcie_pme_mark_devices(port);
+		pcie_pme_interrupt_enable(port, true);
+	}
+
+	return ret;
+}
+
+/**
+ * pcie_pme_suspend - Suspend PCIe PME service device.
+ * @srv: PCIe service device to suspend.
+ */
+static int pcie_pme_suspend(struct pcie_device *srv)
+{
+	struct pcie_pme_service_data *data = get_service_data(srv);
+	struct pci_dev *port = srv->port;
+
+	spin_lock_irq(&data->lock);
+	pcie_pme_interrupt_enable(port, false);
+	pcie_pme_clear_status(port);
+	data->noirq = true;
+	spin_unlock_irq(&data->lock);
+
+	synchronize_irq(srv->irq);
+
+	return 0;
+}
+
+/**
+ * pcie_pme_resume - Resume PCIe PME service device.
+ * @srv - PCIe service device to resume.
+ */
+static int pcie_pme_resume(struct pcie_device *srv)
+{
+	struct pcie_pme_service_data *data = get_service_data(srv);
+	struct pci_dev *port = srv->port;
+
+	spin_lock_irq(&data->lock);
+	data->noirq = false;
+	pcie_pme_clear_status(port);
+	pcie_pme_interrupt_enable(port, true);
+	spin_unlock_irq(&data->lock);
+
+	return 0;
+}
+
+/**
+ * pcie_pme_remove - Prepare PCIe PME service device for removal.
+ * @srv - PCIe service device to resume.
+ */
+static void pcie_pme_remove(struct pcie_device *srv)
+{
+	pcie_pme_suspend(srv);
+	free_irq(srv->irq, srv);
+	kfree(get_service_data(srv));
+}
+
+static struct pcie_port_service_driver pcie_pme_driver = {
+	.name		= "pcie_pme",
+	.port_type 	= PCI_EXP_TYPE_ROOT_PORT,
+	.service 	= PCIE_PORT_SERVICE_PME,
+
+	.probe		= pcie_pme_probe,
+	.suspend	= pcie_pme_suspend,
+	.resume		= pcie_pme_resume,
+	.remove		= pcie_pme_remove,
+};
+
+/**
+ * pcie_pme_service_init - Register the PCIe PME service driver.
+ */
+static int __init pcie_pme_service_init(void)
+{
+	return pcie_pme_disabled ?
+		-ENODEV : pcie_port_service_register(&pcie_pme_driver);
+}
+
+module_init(pcie_pme_service_init);
+/*
+ * drivers/pci/pcie/pme/pcie_pme.h
+ *
+ * PCI Express Root Port PME signaling support
+ *
+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
+ */
+
+#ifndef _PCIE_PME_H_
+#define _PCIE_PME_H_
+
+struct pcie_device;
+
+#ifdef CONFIG_ACPI
+extern int pcie_pme_acpi_setup(struct pcie_device *srv);
+
+static inline int pcie_pme_platform_notify(struct pcie_device *srv)
+{
+	return pcie_pme_acpi_setup(srv);
+}
+#else /* !CONFIG_ACPI */
+static inline int pcie_pme_platform_notify(struct pcie_device *srv)
+{
+	return 0;
+}
+#endif /* !CONFIG_ACPI */
+
+#endif
+/*
+ * PCIe Native PME support, ACPI-related part
+ *
+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License V2.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/acpi.h>
+#include <linux/pci-acpi.h>
+#include <linux/pcieport_if.h>
+
+/**
+ * pcie_pme_acpi_setup - Request the ACPI BIOS to release control over PCIe PME.
+ * @srv - PCIe PME service for a root port or event collector.
+ *
+ * Invoked when the PCIe bus type loads PCIe PME service driver.  To avoid
+ * conflict with the BIOS PCIe support requires the BIOS to yield PCIe PME
+ * control to the kernel.
+ */
+int pcie_pme_acpi_setup(struct pcie_device *srv)
+{
+	acpi_status status = AE_NOT_FOUND;
+	struct pci_dev *port = srv->port;
+	acpi_handle handle;
+	int error = 0;
+
+	if (acpi_pci_disabled)
+		return -ENOSYS;
+
+	dev_info(&port->dev, "Requesting control of PCIe PME from ACPI BIOS\n");
+
+	handle = acpi_find_root_bridge_handle(port);
+	if (!handle)
+		return -EINVAL;
+
+	status = acpi_pci_osc_control_set(handle,
+			OSC_PCI_EXPRESS_PME_CONTROL |
+			OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
+	if (ACPI_FAILURE(status)) {
+		dev_info(&port->dev,
+			"Failed to receive control of PCIe PME service: %s\n",
+			(status == AE_SUPPORT || status == AE_NOT_FOUND) ?
+			"no _OSC support" : "ACPI _OSC failed");
+		error = -ENODEV;
+	}
+
+	return error;
+}
@@ -266,6 +266,7 @@
 					   configuration space */
 	unsigned int	pme_support:5;	/* Bitmask of states from which PME#
 					   can be generated */
+	unsigned int	pme_interrupt:1;
 	unsigned int	d1_support:1;	/* Low power state D1 is supported */
 	unsigned int	d2_support:1;	/* Low power state D2 is supported */
 	unsigned int	no_d1d2:1;	/* Only allow D0 and D3 */
...	...	@@ -1998,6 +1998,12 @@
1998	1998	force Enable ASPM even on devices that claim not to support it.
1999	1999	WARNING: Forcing ASPM on may cause system lockups.
2000	2000
	2001	+ pcie_pme= [PCIE,PM] Native PCIe PME signaling options:
	2002	+ off Do not use native PCIe PME signaling.
	2003	+ force Use native PCIe PME signaling even if the BIOS refuses
	2004	+ to allow the kernel to control the relevant PCIe config
	2005	+ registers.
	2006	+
2001	2007	pcmv= [HW,PCMCIA] BadgePAD 4
2002	2008
2003	2009	pd. [PARIDE]
...	...	@@ -46,4 +46,8 @@
46	46	help
47	47	This enables PCI Express ASPM debug support. It will add per-device
48	48	interface to control ASPM.
	49	+
	50	+config PCIE_PME
	51	+ def_bool y
	52	+ depends on PCIEPORTBUS && PM_RUNTIME && EXPERIMENTAL && ACPI
...	...	@@ -11,4 +11,6 @@
11	11
12	12	# Build PCI Express AER if needed
13	13	obj-$(CONFIG_PCIEAER) += aer/
	14	+
	15	+obj-$(CONFIG_PCIE_PME) += pme/
	1	+#
	2	+# Makefile for PCI-Express Root Port PME signaling driver
	3	+#
	4	+
	5	+obj-$(CONFIG_PCIE_PME) += pmedriver.o
	6	+
	7	+pmedriver-objs := pcie_pme.o
	8	+pmedriver-$(CONFIG_ACPI) += pcie_pme_acpi.o
	1	+/*
	2	+ * PCIe Native PME support
	3	+ *
	4	+ * Copyright (C) 2007 - 2009 Intel Corp
	5	+ * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
	6	+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
	7	+ *
	8	+ * This file is subject to the terms and conditions of the GNU General Public
	9	+ * License V2. See the file "COPYING" in the main directory of this archive
	10	+ * for more details.
	11	+ */
	12	+
	13	+#include <linux/module.h>
	14	+#include <linux/pci.h>
	15	+#include <linux/kernel.h>
	16	+#include <linux/errno.h>
	17	+#include <linux/init.h>
	18	+#include <linux/interrupt.h>
	19	+#include <linux/device.h>
	20	+#include <linux/pcieport_if.h>
	21	+#include <linux/acpi.h>
	22	+#include <linux/pci-acpi.h>
	23	+#include <linux/pm_runtime.h>
	24	+
	25	+#include "../../pci.h"
	26	+#include "pcie_pme.h"
	27	+
	28	+#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
	29	+#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
	30	+
	31	+/*
	32	+ * If set, this switch will prevent the PCIe root port PME service driver from
	33	+ * being registered. Consequently, the interrupt-based PCIe PME signaling will
	34	+ * not be used by any PCIe root ports in that case.
	35	+ */
	36	+static bool pcie_pme_disabled;
	37	+
	38	+/*
	39	+ * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
	40	+ * "In order to maintain compatibility with non-PCI Express-aware system
	41	+ * software, system power management logic must be configured by firmware to use
	42	+ * the legacy mechanism of signaling PME by default. PCI Express-aware system
	43	+ * software must notify the firmware prior to enabling native, interrupt-based
	44	+ * PME signaling." However, if the platform doesn't provide us with a suitable
	45	+ * notification mechanism or the notification fails, it is not clear whether or
	46	+ * not we are supposed to use the interrupt-based PCIe PME signaling. The
	47	+ * switch below can be used to indicate the desired behaviour. When set, it
	48	+ * will make the kernel use the interrupt-based PCIe PME signaling regardless of
	49	+ * the platform notification status, although the kernel will attempt to notify
	50	+ * the platform anyway. When unset, it will prevent the kernel from using the
	51	+ * the interrupt-based PCIe PME signaling if the platform notification fails,
	52	+ * which is the default.
	53	+ */
	54	+static bool pcie_pme_force_enable;
	55	+
	56	+static int __init pcie_pme_setup(char *str)
	57	+{
	58	+ if (!strcmp(str, "off"))
	59	+ pcie_pme_disabled = true;
	60	+ else if (!strcmp(str, "force"))
	61	+ pcie_pme_force_enable = true;
	62	+ return 1;
	63	+}
	64	+__setup("pcie_pme=", pcie_pme_setup);
	65	+
	66	+/**
	67	+ * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
	68	+ * @srv: PCIe PME root port service to use for carrying out the check.
	69	+ *
	70	+ * Notify the platform that the native PCIe PME is going to be used and return
	71	+ * 'true' if the control of the PCIe PME registers has been acquired from the
	72	+ * platform.
	73	+ */
	74	+static bool pcie_pme_platform_setup(struct pcie_device *srv)
	75	+{
	76	+ return !pcie_pme_platform_notify(srv) \|\| pcie_pme_force_enable;
	77	+}
	78	+
	79	+struct pcie_pme_service_data {
	80	+ spinlock_t lock;
	81	+ struct pcie_device *srv;
	82	+ struct work_struct work;
	83	+ bool noirq; /* Don't enable the PME interrupt used by this service. */
	84	+};
	85	+
	86	+/**
	87	+ * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
	88	+ * @dev: PCIe root port or event collector.
	89	+ * @enable: Enable or disable the interrupt.
	90	+ */
	91	+static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
	92	+{
	93	+ int rtctl_pos;
	94	+ u16 rtctl;
	95	+
	96	+ rtctl_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTCTL;
	97	+
	98	+ pci_read_config_word(dev, rtctl_pos, &rtctl);
	99	+ if (enable)
	100	+ rtctl \|= PCI_EXP_RTCTL_PMEIE;
	101	+ else
	102	+ rtctl &= ~PCI_EXP_RTCTL_PMEIE;
	103	+ pci_write_config_word(dev, rtctl_pos, rtctl);
	104	+}
	105	+
	106	+/**
	107	+ * pcie_pme_clear_status - Clear root port PME interrupt status.
	108	+ * @dev: PCIe root port or event collector.
	109	+ */
	110	+static void pcie_pme_clear_status(struct pci_dev *dev)
	111	+{
	112	+ int rtsta_pos;
	113	+ u32 rtsta;
	114	+
	115	+ rtsta_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
	116	+
	117	+ pci_read_config_dword(dev, rtsta_pos, &rtsta);
	118	+ rtsta \|= PCI_EXP_RTSTA_PME;
	119	+ pci_write_config_dword(dev, rtsta_pos, rtsta);
	120	+}
	121	+
	122	+/**
	123	+ * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
	124	+ * @bus: PCI bus to scan.
	125	+ *
	126	+ * Scan given PCI bus and all buses under it for devices asserting PME#.
	127	+ */
	128	+static bool pcie_pme_walk_bus(struct pci_bus *bus)
	129	+{
	130	+ struct pci_dev *dev;
	131	+ bool ret = false;
	132	+
	133	+ list_for_each_entry(dev, &bus->devices, bus_list) {
	134	+ /* Skip PCIe devices in case we started from a root port. */
	135	+ if (!dev->is_pcie && pci_check_pme_status(dev)) {
	136	+ pm_request_resume(&dev->dev);
	137	+ ret = true;
	138	+ }
	139	+
	140	+ if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
	141	+ ret = true;
	142	+ }
	143	+
	144	+ return ret;
	145	+}
	146	+
	147	+/**
	148	+ * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
	149	+ * @bus: Secondary bus of the bridge.
	150	+ * @devfn: Device/function number to check.
	151	+ *
	152	+ * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
	153	+ * PCIe PME message. In such that case the bridge should use the Requester ID
	154	+ * of device/function number 0 on its secondary bus.
	155	+ */
	156	+static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
	157	+{
	158	+ struct pci_dev *dev;
	159	+ bool found = false;
	160	+
	161	+ if (devfn)
	162	+ return false;
	163	+
	164	+ dev = pci_dev_get(bus->self);
	165	+ if (!dev)
	166	+ return false;
	167	+
	168	+ if (dev->is_pcie && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
	169	+ down_read(&pci_bus_sem);
	170	+ if (pcie_pme_walk_bus(bus))
	171	+ found = true;
	172	+ up_read(&pci_bus_sem);
	173	+ }
	174	+
	175	+ pci_dev_put(dev);
	176	+ return found;
	177	+}
	178	+
	179	+/**
	180	+ * pcie_pme_handle_request - Find device that generated PME and handle it.
	181	+ * @port: Root port or event collector that generated the PME interrupt.
	182	+ * @req_id: PCIe Requester ID of the device that generated the PME.
	183	+ */
	184	+static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
	185	+{
	186	+ u8 busnr = req_id >> 8, devfn = req_id & 0xff;
	187	+ struct pci_bus *bus;
	188	+ struct pci_dev *dev;
	189	+ bool found = false;
	190	+
	191	+ /* First, check if the PME is from the root port itself. */
	192	+ if (port->devfn == devfn && port->bus->number == busnr) {
	193	+ if (pci_check_pme_status(port)) {
	194	+ pm_request_resume(&port->dev);
	195	+ found = true;
	196	+ } else {
	197	+ /*
	198	+ * Apparently, the root port generated the PME on behalf
	199	+ * of a non-PCIe device downstream. If this is done by
	200	+ * a root port, the Requester ID field in its status
	201	+ * register may contain either the root port's, or the
	202	+ * source device's information (PCI Express Base
	203	+ * Specification, Rev. 2.0, Section 6.1.9).
	204	+ */
	205	+ down_read(&pci_bus_sem);
	206	+ found = pcie_pme_walk_bus(port->subordinate);
	207	+ up_read(&pci_bus_sem);
	208	+ }
	209	+ goto out;
	210	+ }
	211	+
	212	+ /* Second, find the bus the source device is on. */
	213	+ bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
	214	+ if (!bus)
	215	+ goto out;
	216	+
	217	+ /* Next, check if the PME is from a PCIe-PCI bridge. */
	218	+ found = pcie_pme_from_pci_bridge(bus, devfn);
	219	+ if (found)
	220	+ goto out;
	221	+
	222	+ /* Finally, try to find the PME source on the bus. */
	223	+ down_read(&pci_bus_sem);
	224	+ list_for_each_entry(dev, &bus->devices, bus_list) {
	225	+ pci_dev_get(dev);
	226	+ if (dev->devfn == devfn) {
	227	+ found = true;
	228	+ break;
	229	+ }
	230	+ pci_dev_put(dev);
	231	+ }
	232	+ up_read(&pci_bus_sem);
	233	+
	234	+ if (found) {
	235	+ /* The device is there, but we have to check its PME status. */
	236	+ found = pci_check_pme_status(dev);
	237	+ if (found)
	238	+ pm_request_resume(&dev->dev);
	239	+ pci_dev_put(dev);
	240	+ } else if (devfn) {
	241	+ /*
	242	+ * The device is not there, but we can still try to recover by
	243	+ * assuming that the PME was reported by a PCIe-PCI bridge that
	244	+ * used devfn different from zero.
	245	+ */
	246	+ dev_dbg(&port->dev, "PME interrupt generated for "
	247	+ "non-existent device %02x:%02x.%d\n",
	248	+ busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
	249	+ found = pcie_pme_from_pci_bridge(bus, 0);
	250	+ }
	251	+
	252	+ out:
	253	+ if (!found)
	254	+ dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
	255	+}
	256	+
	257	+/**
	258	+ * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
	259	+ * @work: Work structure giving access to service data.
	260	+ */
	261	+static void pcie_pme_work_fn(struct work_struct *work)
	262	+{
	263	+ struct pcie_pme_service_data *data =
	264	+ container_of(work, struct pcie_pme_service_data, work);
	265	+ struct pci_dev *port = data->srv->port;
	266	+ int rtsta_pos;
	267	+ u32 rtsta;
	268	+
	269	+ rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
	270	+
	271	+ spin_lock_irq(&data->lock);
	272	+
	273	+ for (;;) {
	274	+ if (data->noirq)
	275	+ break;
	276	+
	277	+ pci_read_config_dword(port, rtsta_pos, &rtsta);
	278	+ if (rtsta & PCI_EXP_RTSTA_PME) {
	279	+ /*
	280	+ * Clear PME status of the port. If there are other
	281	+ * pending PMEs, the status will be set again.
	282	+ */
	283	+ pcie_pme_clear_status(port);
	284	+
	285	+ spin_unlock_irq(&data->lock);
	286	+ pcie_pme_handle_request(port, rtsta & 0xffff);
	287	+ spin_lock_irq(&data->lock);
	288	+
	289	+ continue;
	290	+ }
	291	+
	292	+ /* No need to loop if there are no more PMEs pending. */
	293	+ if (!(rtsta & PCI_EXP_RTSTA_PENDING))
	294	+ break;
	295	+
	296	+ spin_unlock_irq(&data->lock);
	297	+ cpu_relax();
	298	+ spin_lock_irq(&data->lock);
	299	+ }
	300	+
	301	+ if (!data->noirq)
	302	+ pcie_pme_interrupt_enable(port, true);
	303	+
	304	+ spin_unlock_irq(&data->lock);
	305	+}
	306	+
	307	+/**
	308	+ * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
	309	+ * @irq: Interrupt vector.
	310	+ * @context: Interrupt context pointer.
	311	+ */
	312	+static irqreturn_t pcie_pme_irq(int irq, void *context)
	313	+{
	314	+ struct pci_dev *port;
	315	+ struct pcie_pme_service_data *data;
	316	+ int rtsta_pos;
	317	+ u32 rtsta;
	318	+ unsigned long flags;
	319	+
	320	+ port = ((struct pcie_device *)context)->port;
	321	+ data = get_service_data((struct pcie_device *)context);
	322	+
	323	+ rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
	324	+
	325	+ spin_lock_irqsave(&data->lock, flags);
	326	+ pci_read_config_dword(port, rtsta_pos, &rtsta);
	327	+
	328	+ if (!(rtsta & PCI_EXP_RTSTA_PME)) {
	329	+ spin_unlock_irqrestore(&data->lock, flags);
	330	+ return IRQ_NONE;
	331	+ }
	332	+
	333	+ pcie_pme_interrupt_enable(port, false);
	334	+ spin_unlock_irqrestore(&data->lock, flags);
	335	+
	336	+ /* We don't use pm_wq, because it's freezable. */
	337	+ schedule_work(&data->work);
	338	+
	339	+ return IRQ_HANDLED;
	340	+}
	341	+
	342	+/**
	343	+ * pcie_pme_set_native - Set the PME interrupt flag for given device.
	344	+ * @dev: PCI device to handle.
	345	+ * @ign: Ignored.
	346	+ */
	347	+static int pcie_pme_set_native(struct pci_dev dev, void ign)
	348	+{
	349	+ dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
	350	+
	351	+ device_set_run_wake(&dev->dev, true);
	352	+ dev->pme_interrupt = true;
	353	+ return 0;
	354	+}
	355	+
	356	+/**
	357	+ * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
	358	+ * @port: PCIe root port or event collector to handle.
	359	+ *
	360	+ * For each device below given root port, including the port itself (or for each
	361	+ * root complex integrated endpoint if @port is a root complex event collector)
	362	+ * set the flag indicating that it can signal run-time wake-up events via PCIe
	363	+ * PME interrupts.
	364	+ */
	365	+static void pcie_pme_mark_devices(struct pci_dev *port)
	366	+{
	367	+ pcie_pme_set_native(port, NULL);
	368	+ if (port->subordinate) {
	369	+ pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
	370	+ } else {
	371	+ struct pci_bus *bus = port->bus;
	372	+ struct pci_dev *dev;
	373	+
	374	+ /* Check if this is a root port event collector. */
	375	+ if (port->pcie_type != PCI_EXP_TYPE_RC_EC \|\| !bus)
	376	+ return;
	377	+
	378	+ down_read(&pci_bus_sem);
	379	+ list_for_each_entry(dev, &bus->devices, bus_list)
	380	+ if (dev->is_pcie
	381	+ && dev->pcie_type == PCI_EXP_TYPE_RC_END)
	382	+ pcie_pme_set_native(dev, NULL);
	383	+ up_read(&pci_bus_sem);
	384	+ }
	385	+}
	386	+
	387	+/**
	388	+ * pcie_pme_probe - Initialize PCIe PME service for given root port.
	389	+ * @srv: PCIe service to initialize.
	390	+ */
	391	+static int pcie_pme_probe(struct pcie_device *srv)
	392	+{
	393	+ struct pci_dev *port;
	394	+ struct pcie_pme_service_data *data;
	395	+ int ret;
	396	+
	397	+ if (!pcie_pme_platform_setup(srv))
	398	+ return -EACCES;
	399	+
	400	+ data = kzalloc(sizeof(*data), GFP_KERNEL);
	401	+ if (!data)
	402	+ return -ENOMEM;
	403	+
	404	+ spin_lock_init(&data->lock);
	405	+ INIT_WORK(&data->work, pcie_pme_work_fn);
	406	+ data->srv = srv;
	407	+ set_service_data(srv, data);
	408	+
	409	+ port = srv->port;
	410	+ pcie_pme_interrupt_enable(port, false);
	411	+ pcie_pme_clear_status(port);
	412	+
	413	+ ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
	414	+ if (ret) {
	415	+ kfree(data);
	416	+ } else {
	417	+ pcie_pme_mark_devices(port);
	418	+ pcie_pme_interrupt_enable(port, true);
	419	+ }
	420	+
	421	+ return ret;
	422	+}
	423	+
	424	+/**
	425	+ * pcie_pme_suspend - Suspend PCIe PME service device.
	426	+ * @srv: PCIe service device to suspend.
	427	+ */
	428	+static int pcie_pme_suspend(struct pcie_device *srv)
	429	+{
	430	+ struct pcie_pme_service_data *data = get_service_data(srv);
	431	+ struct pci_dev *port = srv->port;
	432	+
	433	+ spin_lock_irq(&data->lock);
	434	+ pcie_pme_interrupt_enable(port, false);
	435	+ pcie_pme_clear_status(port);
	436	+ data->noirq = true;
	437	+ spin_unlock_irq(&data->lock);
	438	+
	439	+ synchronize_irq(srv->irq);
	440	+
	441	+ return 0;
	442	+}
	443	+
	444	+/**
	445	+ * pcie_pme_resume - Resume PCIe PME service device.
	446	+ * @srv - PCIe service device to resume.
	447	+ */
	448	+static int pcie_pme_resume(struct pcie_device *srv)
	449	+{
	450	+ struct pcie_pme_service_data *data = get_service_data(srv);
	451	+ struct pci_dev *port = srv->port;
	452	+
	453	+ spin_lock_irq(&data->lock);
	454	+ data->noirq = false;
	455	+ pcie_pme_clear_status(port);
	456	+ pcie_pme_interrupt_enable(port, true);
	457	+ spin_unlock_irq(&data->lock);
	458	+
	459	+ return 0;
	460	+}
	461	+
	462	+/**
	463	+ * pcie_pme_remove - Prepare PCIe PME service device for removal.
	464	+ * @srv - PCIe service device to resume.
	465	+ */
	466	+static void pcie_pme_remove(struct pcie_device *srv)
	467	+{
	468	+ pcie_pme_suspend(srv);
	469	+ free_irq(srv->irq, srv);
	470	+ kfree(get_service_data(srv));
	471	+}
	472	+
	473	+static struct pcie_port_service_driver pcie_pme_driver = {
	474	+ .name = "pcie_pme",
	475	+ .port_type = PCI_EXP_TYPE_ROOT_PORT,
	476	+ .service = PCIE_PORT_SERVICE_PME,
	477	+
	478	+ .probe = pcie_pme_probe,
	479	+ .suspend = pcie_pme_suspend,
	480	+ .resume = pcie_pme_resume,
	481	+ .remove = pcie_pme_remove,
	482	+};
	483	+
	484	+/**
	485	+ * pcie_pme_service_init - Register the PCIe PME service driver.
	486	+ */
	487	+static int __init pcie_pme_service_init(void)
	488	+{
	489	+ return pcie_pme_disabled ?
	490	+ -ENODEV : pcie_port_service_register(&pcie_pme_driver);
	491	+}
	492	+
	493	+module_init(pcie_pme_service_init);
	1	+/*
	2	+ * drivers/pci/pcie/pme/pcie_pme.h
	3	+ *
	4	+ * PCI Express Root Port PME signaling support
	5	+ *
	6	+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
	7	+ */
	8	+
	9	+#ifndef _PCIE_PME_H_
	10	+#define _PCIE_PME_H_
	11	+
	12	+struct pcie_device;
	13	+
	14	+#ifdef CONFIG_ACPI
	15	+extern int pcie_pme_acpi_setup(struct pcie_device *srv);
	16	+
	17	+static inline int pcie_pme_platform_notify(struct pcie_device *srv)
	18	+{
	19	+ return pcie_pme_acpi_setup(srv);
	20	+}
	21	+#else /* !CONFIG_ACPI */
	22	+static inline int pcie_pme_platform_notify(struct pcie_device *srv)
	23	+{
	24	+ return 0;
	25	+}
	26	+#endif /* !CONFIG_ACPI */
	27	+
	28	+#endif
	1	+/*
	2	+ * PCIe Native PME support, ACPI-related part
	3	+ *
	4	+ * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
	5	+ *
	6	+ * This file is subject to the terms and conditions of the GNU General Public
	7	+ * License V2. See the file "COPYING" in the main directory of this archive
	8	+ * for more details.
	9	+ */
	10	+
	11	+#include <linux/pci.h>
	12	+#include <linux/kernel.h>
	13	+#include <linux/errno.h>
	14	+#include <linux/acpi.h>
	15	+#include <linux/pci-acpi.h>
	16	+#include <linux/pcieport_if.h>
	17	+
	18	+/**
	19	+ * pcie_pme_acpi_setup - Request the ACPI BIOS to release control over PCIe PME.
	20	+ * @srv - PCIe PME service for a root port or event collector.
	21	+ *
	22	+ * Invoked when the PCIe bus type loads PCIe PME service driver. To avoid
	23	+ * conflict with the BIOS PCIe support requires the BIOS to yield PCIe PME
	24	+ * control to the kernel.
	25	+ */
	26	+int pcie_pme_acpi_setup(struct pcie_device *srv)
	27	+{
	28	+ acpi_status status = AE_NOT_FOUND;
	29	+ struct pci_dev *port = srv->port;
	30	+ acpi_handle handle;
	31	+ int error = 0;
	32	+
	33	+ if (acpi_pci_disabled)
	34	+ return -ENOSYS;
	35	+
	36	+ dev_info(&port->dev, "Requesting control of PCIe PME from ACPI BIOS\n");
	37	+
	38	+ handle = acpi_find_root_bridge_handle(port);
	39	+ if (!handle)
	40	+ return -EINVAL;
	41	+
	42	+ status = acpi_pci_osc_control_set(handle,
	43	+ OSC_PCI_EXPRESS_PME_CONTROL \|
	44	+ OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
	45	+ if (ACPI_FAILURE(status)) {
	46	+ dev_info(&port->dev,
	47	+ "Failed to receive control of PCIe PME service: %s\n",
	48	+ (status == AE_SUPPORT \|\| status == AE_NOT_FOUND) ?
	49	+ "no _OSC support" : "ACPI _OSC failed");
	50	+ error = -ENODEV;
	51	+ }
	52	+
	53	+ return error;
	54	+}
...	...	@@ -266,6 +266,7 @@
266	266	configuration space */
267	267	unsigned int pme_support:5; /* Bitmask of states from which PME#
268	268	can be generated */
	269	+ unsigned int pme_interrupt:1;
269	270	unsigned int d1_support:1; /* Low power state D1 is supported */
270	271	unsigned int d2_support:1; /* Low power state D2 is supported */
271	272	unsigned int no_d1d2:1; /* Only allow D0 and D3 */