wl1271: ref_clock cosmetic changes

Cosmetic cleanup for ref_clock code while configured by board. Signed-off-by: Gery Kahn <geryk@ti.com> Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com>

wl1271: ref_clock cosmetic changes
Cosmetic cleanup for ref_clock code while configured by board. Signed-off-by: Gery Kahn <geryk@ti.com> Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com>
Gery Kahn · John W. Linville
1 parent 34d59c07e9
Showing 2 changed files with 12 additions and 6 deletions Side-by-side Diff
drivers/net/wireless/wl12xx/wl1271_boot.c
include/linux/wl12xx.h
@@ -471,20 +471,19 @@
 {
 	int ret = 0;
 	u32 tmp, clk, pause;
-	int ref_clock = wl->ref_clock;
  
 	wl1271_boot_hw_version(wl);
  
-	if (ref_clock == 0 || ref_clock == 2 || ref_clock == 4)
+	if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
 		/* ref clk: 19.2/38.4/38.4-XTAL */
 		clk = 0x3;
-	else if (ref_clock == 1 || ref_clock == 3)
+	else if (wl->ref_clock == 1 || wl->ref_clock == 3)
 		/* ref clk: 26/52 */
 		clk = 0x5;
 	else
 		return -EINVAL;
  
-	if (ref_clock != 0) {
+	if (wl->ref_clock != 0) {
 		u16 val;
 		/* Set clock type (open drain) */
 		val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
@@ -529,8 +528,7 @@
  
 	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
  
-	/* 2 */
-	clk |= (ref_clock << 1) << 4;
+	clk |= (wl->ref_clock << 1) << 4;
 	wl1271_write32(wl, DRPW_SCRATCH_START, clk);
  
 	wl1271_set_partition(wl, &part_table[PART_WORK]);
@@ -24,6 +24,14 @@
 #ifndef _LINUX_WL12XX_H
 #define _LINUX_WL12XX_H
  
+/* The board reference clock values */
+enum {
+	WL12XX_REFCLOCK_19 = 0,	/* 19.2 MHz */
+	WL12XX_REFCLOCK_26 = 1,	/* 26 MHz */
+	WL12XX_REFCLOCK_38 = 2,	/* 38.4 MHz */
+	WL12XX_REFCLOCK_54 = 3,	/* 54 MHz */
+};
+
 struct wl12xx_platform_data {
 	void (*set_power)(bool enable);
 	/* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
...	...	@@ -471,20 +471,19 @@
471	471	{
472	472	int ret = 0;
473	473	u32 tmp, clk, pause;
474		- int ref_clock = wl->ref_clock;
475	474
476	475	wl1271_boot_hw_version(wl);
477	476
478		- if (ref_clock == 0 \|\| ref_clock == 2 \|\| ref_clock == 4)
	477	+ if (wl->ref_clock == 0 \|\| wl->ref_clock == 2 \|\| wl->ref_clock == 4)
479	478	/* ref clk: 19.2/38.4/38.4-XTAL */
480	479	clk = 0x3;
481		- else if (ref_clock == 1 \|\| ref_clock == 3)
	480	+ else if (wl->ref_clock == 1 \|\| wl->ref_clock == 3)
482	481	/* ref clk: 26/52 */
483	482	clk = 0x5;
484	483	else
485	484	return -EINVAL;
486	485
487		- if (ref_clock != 0) {
	486	+ if (wl->ref_clock != 0) {
488	487	u16 val;
489	488	/* Set clock type (open drain) */
490	489	val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
...	...	@@ -529,8 +528,7 @@
529	528
530	529	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
531	530
532		- /* 2 */
533		- clk \|= (ref_clock << 1) << 4;
	531	+ clk \|= (wl->ref_clock << 1) << 4;
534	532	wl1271_write32(wl, DRPW_SCRATCH_START, clk);
535	533
536	534	wl1271_set_partition(wl, &part_table[PART_WORK]);
...	...	@@ -24,6 +24,14 @@
24	24	#ifndef _LINUX_WL12XX_H
25	25	#define _LINUX_WL12XX_H
26	26
	27	+/* The board reference clock values */
	28	+enum {
	29	+ WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
	30	+ WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
	31	+ WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
	32	+ WL12XX_REFCLOCK_54 = 3, /* 54 MHz */
	33	+};
	34	+
27	35	struct wl12xx_platform_data {
28	36	void (*set_power)(bool enable);
29	37	/* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */