Eric Lee / linux-smarc-t335x-v3.2

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Commit d13780d439d08a57c87c1a07b6e76ddde61da1aa

Authored by Len Brown
1 parent 815c4163b6
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

intel_idle: add initial Sandy Bridge support 

Signed-off-by: Len Brown <len.brown@intel.com>

Showing 1 changed file with 43 additions and 1 deletions Side-by-side Diff

drivers/idle/intel_idle.c
Diff comments   View file @ d13780d
... ... @@ -83,7 +83,7 @@
83 83 static int (*choose_substate)(int);
84 84  
85 85 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
86   -static unsigned int lapic_timer_reliable_states;
  86 +static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
87 87  
88 88 static struct cpuidle_device *intel_idle_cpuidle_devices;
89 89 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
... ... @@ -126,6 +126,42 @@
126 126 .enter = &intel_idle },
127 127 };
128 128  
  129 +static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
  130 + { /* MWAIT C0 */ },
  131 + { /* MWAIT C1 */
  132 + .name = "SNB-C1",
  133 + .desc = "MWAIT 0x00",
  134 + .driver_data = (void *) 0x00,
  135 + .flags = CPUIDLE_FLAG_TIME_VALID,
  136 + .exit_latency = 1,
  137 + .target_residency = 4,
  138 + .enter = &intel_idle },
  139 + { /* MWAIT C2 */
  140 + .name = "SNB-C3",
  141 + .desc = "MWAIT 0x10",
  142 + .driver_data = (void *) 0x10,
  143 + .flags = CPUIDLE_FLAG_TIME_VALID,
  144 + .exit_latency = 80,
  145 + .target_residency = 160,
  146 + .enter = &intel_idle },
  147 + { /* MWAIT C3 */
  148 + .name = "SNB-C6",
  149 + .desc = "MWAIT 0x20",
  150 + .driver_data = (void *) 0x20,
  151 + .flags = CPUIDLE_FLAG_TIME_VALID,
  152 + .exit_latency = 104,
  153 + .target_residency = 208,
  154 + .enter = &intel_idle },
  155 + { /* MWAIT C4 */
  156 + .name = "SNB-C7",
  157 + .desc = "MWAIT 0x30",
  158 + .driver_data = (void *) 0x30,
  159 + .flags = CPUIDLE_FLAG_TIME_VALID,
  160 + .exit_latency = 109,
  161 + .target_residency = 300,
  162 + .enter = &intel_idle },
  163 +};
  164 +
129 165 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
130 166 { /* MWAIT C0 */ },
131 167 { /* MWAIT C1 */
... ... @@ -310,6 +346,12 @@
310 346 case 0x1C: /* 28 - Atom Processor */
311 347 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
312 348 cpuidle_state_table = atom_cstates;
  349 + choose_substate = choose_zero_substate;
  350 + break;
  351 +
  352 + case 0x2A: /* SNB */
  353 + case 0x2D: /* SNB Xeon */
  354 + cpuidle_state_table = snb_cstates;
313 355 choose_substate = choose_zero_substate;
314 356 break;
315 357 #ifdef FUTURE_USE