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Commit d198b514bd9e94930ee0b9ca1cad0a51f5e29608

Authored by Paul Walmsley
1 parent f5f9d132d1
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

OMAP4: PRCM: reorganize existing OMAP4 PRCM header files 

Split the existing cm44xx.h file into cm1_44xx.h and cm2_44xx.h files
so they match their underlying OMAP hardware modules.  Add clockdomain
offset information.

Add header files for the MPU local PRCM, prcm_mpu44xx.h, and for the
SCRM, scrm44xx.h.  SCRM register offsets still need to be added; TI
should do this.

Move the "_MOD" macros out of the prcm-common.h header file, into the
header file of the hardware module that they belong to.  For example,
OMAP4430_PRM_*_MOD macros have been moved into the prm44xx.h header.

Adjust #includes of all files that used the old PRCM header file names
to point to the new filenames.

The autogeneration scripts have been updated accordingly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Showing 17 changed files with 929 additions and 803 deletions Side-by-side Diff

arch/arm/mach-omap2/clock44xx_data.c
Diff comments   View file @ d198b51
... ... @@ -30,9 +30,11 @@
30 30  
31 31 #include "clock.h"
32 32 #include "clock44xx.h"
33   -#include "cm.h"
  33 +#include "cm1_44xx.h"
  34 +#include "cm2_44xx.h"
34 35 #include "cm-regbits-44xx.h"
35 36 #include "prm.h"
  37 +#include "prm44xx.h"
36 38 #include "prm-regbits-44xx.h"
37 39 #include "control.h"
38 40  
arch/arm/mach-omap2/clockdomains44xx_data.c
Diff comments   View file @ d198b51
... ... @@ -28,10 +28,12 @@
28 28  
29 29 #include <plat/clockdomain.h>
30 30  
31   -#include "cm44xx.h"
32   -#include "prm44xx.h"
  31 +#include "cm1_44xx.h"
  32 +#include "cm2_44xx.h"
33 33 #include "cm-regbits-44xx.h"
34   -#include "prm-regbits-44xx.h"
  34 +#include "prm44xx.h"
  35 +#include "prcm_mpu44xx.h"
  36 +
35 37  
36 38 static struct clockdomain l4_cefuse_44xx_clkdm = {
37 39 .name = "l4_cefuse_clkdm",
arch/arm/mach-omap2/cm.h
Diff comments   View file @ d198b51
... ... @@ -22,10 +22,7 @@
22 22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23 23 #define OMAP34XX_CM_REGADDR(module, reg) \
24 24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
25   -#define OMAP44XX_CM1_REGADDR(module, reg) \
26   - OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
27   -#define OMAP44XX_CM2_REGADDR(module, reg) \
28   - OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
  25 +
29 26  
30 27 #include "cm44xx.h"
31 28  
arch/arm/mach-omap2/cm1_44xx.h
Diff comments   View file @ d198b51
  1 +/*
  2 + * OMAP44xx CM1 instance offset macros
  3 + *
  4 + * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5 + * Copyright (C) 2009-2010 Nokia Corporation
  6 + *
  7 + * Paul Walmsley (paul@pwsan.com)
  8 + * Rajendra Nayak (rnayak@ti.com)
  9 + * Benoit Cousson (b-cousson@ti.com)
  10 + *
  11 + * This file is automatically generated from the OMAP hardware databases.
  12 + * We respectfully ask that any modifications to this file be coordinated
  13 + * with the public linux-omap@vger.kernel.org mailing list and the
  14 + * authors above to ensure that the autogeneration scripts are kept
  15 + * up-to-date with the file contents.
  16 + *
  17 + * This program is free software; you can redistribute it and/or modify
  18 + * it under the terms of the GNU General Public License version 2 as
  19 + * published by the Free Software Foundation.
  20 + *
  21 + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22 + * or "OMAP4430".
  23 + */
  24 +
  25 +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  26 +#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  27 +
  28 +/* CM1 base address */
  29 +#define OMAP4430_CM1_BASE 0x4a004000
  30 +
  31 +#define OMAP44XX_CM1_REGADDR(module, reg) \
  32 + OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
  33 +
  34 +/* CM1 instances */
  35 +#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
  36 +#define OMAP4430_CM1_CKGEN_MOD 0x0100
  37 +#define OMAP4430_CM1_MPU_MOD 0x0300
  38 +#define OMAP4430_CM1_TESLA_MOD 0x0400
  39 +#define OMAP4430_CM1_ABE_MOD 0x0500
  40 +#define OMAP4430_CM1_RESTORE_MOD 0x0e00
  41 +#define OMAP4430_CM1_INSTR_MOD 0x0f00
  42 +
  43 +/* CM1 */
  44 +
  45 +/* CM1.OCP_SOCKET_CM1 register offsets */
  46 +#define OMAP4_REVISION_CM1_OFFSET 0x0000
  47 +#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
  48 +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
  49 +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
  50 +
  51 +/* CM1.CKGEN_CM1 register offsets */
  52 +#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
  53 +#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
  54 +#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
  55 +#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
  56 +#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
  57 +#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
  58 +#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
  59 +#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
  60 +#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
  61 +#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
  62 +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
  63 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
  64 +#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
  65 +#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
  66 +#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
  67 +#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
  68 +#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
  69 +#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
  70 +#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
  71 +#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
  72 +#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
  73 +#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
  74 +#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
  75 +#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
  76 +#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
  77 +#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
  78 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
  79 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
  80 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
  81 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
  82 +#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
  83 +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
  84 +#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
  85 +#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
  86 +#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
  87 +#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
  88 +#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
  89 +#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
  90 +#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
  91 +#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
  92 +#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
  93 +#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
  94 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
  95 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
  96 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
  97 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
  98 +#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
  99 +#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
  100 +#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
  101 +#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
  102 +#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
  103 +#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
  104 +#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
  105 +#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
  106 +#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
  107 +#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
  108 +#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
  109 +#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
  110 +#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
  111 +#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
  112 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
  113 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
  114 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
  115 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
  116 +#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
  117 +#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
  118 +#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
  119 +#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
  120 +#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
  121 +#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
  122 +#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
  123 +#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
  124 +#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
  125 +#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
  126 +#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
  127 +#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
  128 +#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
  129 +#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
  130 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
  131 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
  132 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
  133 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
  134 +#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
  135 +#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
  136 +#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
  137 +#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
  138 +#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
  139 +#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
  140 +#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
  141 +#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
  142 +#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
  143 +#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
  144 +#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
  145 +#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
  146 +#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
  147 +#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
  148 +#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
  149 +#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
  150 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
  151 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
  152 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
  153 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
  154 +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
  155 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
  156 +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
  157 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
  158 +#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
  159 +#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
  160 +#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
  161 +#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
  162 +
  163 +/* CM1.MPU_CM1 register offsets */
  164 +#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
  165 +#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
  166 +#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
  167 +#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
  168 +#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
  169 +#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
  170 +#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
  171 +#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
  172 +
  173 +/* CM1.TESLA_CM1 register offsets */
  174 +#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
  175 +#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
  176 +#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
  177 +#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
  178 +#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
  179 +#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
  180 +#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
  181 +#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
  182 +
  183 +/* CM1.ABE_CM1 register offsets */
  184 +#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
  185 +#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
  186 +#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
  187 +#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
  188 +#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
  189 +#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
  190 +#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
  191 +#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
  192 +#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
  193 +#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
  194 +#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
  195 +#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
  196 +#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
  197 +#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
  198 +#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
  199 +#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
  200 +#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
  201 +#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
  202 +#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
  203 +#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
  204 +#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
  205 +#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
  206 +#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
  207 +#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
  208 +#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
  209 +#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
  210 +#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
  211 +#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
  212 +#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
  213 +#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
  214 +
  215 +/* CM1.RESTORE_CM1 register offsets */
  216 +#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
  217 +#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
  218 +#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
  219 +#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
  220 +#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
  221 +#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
  222 +#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
  223 +#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
  224 +#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
  225 +#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
  226 +#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
  227 +#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
  228 +#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
  229 +#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
  230 +#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
  231 +#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
  232 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
  233 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
  234 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
  235 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
  236 +#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
  237 +#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
  238 +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
  239 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
  240 +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
  241 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
  242 +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
  243 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
  244 +#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
  245 +#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
  246 +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
  247 +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
  248 +#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
  249 +#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
  250 +
  251 +/* Function prototypes */
  252 +extern u32 omap4_cm1_read_mod_reg(s16 module, u16 idx);
  253 +extern void omap4_cm1_write_mod_reg(u32 val, s16 module, u16 idx);
  254 +extern u32 omap4_cm1_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
  255 +
  256 +#endif
arch/arm/mach-omap2/cm2_44xx.h
Diff comments   View file @ d198b51
  1 +/*
  2 + * OMAP44xx CM2 instance offset macros
  3 + *
  4 + * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5 + * Copyright (C) 2009-2010 Nokia Corporation
  6 + *
  7 + * Paul Walmsley (paul@pwsan.com)
  8 + * Rajendra Nayak (rnayak@ti.com)
  9 + * Benoit Cousson (b-cousson@ti.com)
  10 + *
  11 + * This file is automatically generated from the OMAP hardware databases.
  12 + * We respectfully ask that any modifications to this file be coordinated
  13 + * with the public linux-omap@vger.kernel.org mailing list and the
  14 + * authors above to ensure that the autogeneration scripts are kept
  15 + * up-to-date with the file contents.
  16 + *
  17 + * This program is free software; you can redistribute it and/or modify
  18 + * it under the terms of the GNU General Public License version 2 as
  19 + * published by the Free Software Foundation.
  20 + *
  21 + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22 + * or "OMAP4430".
  23 + */
  24 +
  25 +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
  26 +#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
  27 +
  28 +/* CM2 base address */
  29 +#define OMAP4430_CM2_BASE 0x4a008000
  30 +
  31 +#define OMAP44XX_CM2_REGADDR(module, reg) \
  32 + OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
  33 +
  34 +/* CM2 instances */
  35 +#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
  36 +#define OMAP4430_CM2_CKGEN_MOD 0x0100
  37 +#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
  38 +#define OMAP4430_CM2_CORE_MOD 0x0700
  39 +#define OMAP4430_CM2_IVAHD_MOD 0x0f00
  40 +#define OMAP4430_CM2_CAM_MOD 0x1000
  41 +#define OMAP4430_CM2_DSS_MOD 0x1100
  42 +#define OMAP4430_CM2_GFX_MOD 0x1200
  43 +#define OMAP4430_CM2_L3INIT_MOD 0x1300
  44 +#define OMAP4430_CM2_L4PER_MOD 0x1400
  45 +#define OMAP4430_CM2_CEFUSE_MOD 0x1600
  46 +#define OMAP4430_CM2_RESTORE_MOD 0x1e00
  47 +#define OMAP4430_CM2_INSTR_MOD 0x1f00
  48 +
  49 +
  50 +/* CM2 */
  51 +
  52 +/* CM2.OCP_SOCKET_CM2 register offsets */
  53 +#define OMAP4_REVISION_CM2_OFFSET 0x0000
  54 +#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
  55 +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
  56 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
  57 +
  58 +/* CM2.CKGEN_CM2 register offsets */
  59 +#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
  60 +#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
  61 +#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
  62 +#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
  63 +#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
  64 +#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
  65 +#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
  66 +#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
  67 +#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
  68 +#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
  69 +#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
  70 +#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
  71 +#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
  72 +#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
  73 +#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
  74 +#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
  75 +#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
  76 +#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
  77 +#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
  78 +#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
  79 +#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
  80 +#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
  81 +#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
  82 +#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
  83 +#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
  84 +#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
  85 +#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
  86 +#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
  87 +#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
  88 +#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
  89 +#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
  90 +#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
  91 +#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
  92 +#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
  93 +#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
  94 +#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
  95 +#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
  96 +#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
  97 +#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
  98 +#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
  99 +#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
  100 +#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
  101 +#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
  102 +#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
  103 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
  104 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
  105 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
  106 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
  107 +#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
  108 +#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
  109 +#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
  110 +#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
  111 +#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
  112 +#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
  113 +#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
  114 +#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
  115 +#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
  116 +#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
  117 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
  118 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
  119 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
  120 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
  121 +#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
  122 +#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
  123 +#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
  124 +#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
  125 +#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
  126 +#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
  127 +#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
  128 +#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
  129 +#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
  130 +#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
  131 +#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
  132 +#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
  133 +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
  134 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
  135 +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
  136 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
  137 +
  138 +/* CM2.ALWAYS_ON_CM2 register offsets */
  139 +#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
  140 +#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
  141 +#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
  142 +#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
  143 +#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
  144 +#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
  145 +#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
  146 +#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
  147 +#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
  148 +#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
  149 +#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
  150 +#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
  151 +
  152 +/* CM2.CORE_CM2 register offsets */
  153 +#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
  154 +#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
  155 +#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
  156 +#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
  157 +#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
  158 +#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
  159 +#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
  160 +#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
  161 +#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
  162 +#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
  163 +#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
  164 +#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
  165 +#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
  166 +#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
  167 +#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
  168 +#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
  169 +#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
  170 +#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
  171 +#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
  172 +#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
  173 +#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
  174 +#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
  175 +#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
  176 +#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
  177 +#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
  178 +#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
  179 +#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
  180 +#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
  181 +#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
  182 +#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
  183 +#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
  184 +#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
  185 +#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
  186 +#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
  187 +#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
  188 +#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
  189 +#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
  190 +#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
  191 +#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
  192 +#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
  193 +#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
  194 +#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
  195 +#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
  196 +#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
  197 +#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
  198 +#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
  199 +#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
  200 +#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
  201 +#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
  202 +#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
  203 +#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
  204 +#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
  205 +#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
  206 +#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
  207 +#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
  208 +#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
  209 +#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
  210 +#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
  211 +#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
  212 +#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
  213 +#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
  214 +#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
  215 +#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
  216 +#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
  217 +#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
  218 +#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
  219 +#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
  220 +#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
  221 +#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
  222 +#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
  223 +#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
  224 +#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
  225 +#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
  226 +#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
  227 +#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
  228 +#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
  229 +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
  230 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
  231 +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
  232 +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
  233 +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
  234 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
  235 +
  236 +/* CM2.IVAHD_CM2 register offsets */
  237 +#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
  238 +#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
  239 +#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
  240 +#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
  241 +#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
  242 +#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
  243 +#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
  244 +#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
  245 +#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
  246 +#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
  247 +
  248 +/* CM2.CAM_CM2 register offsets */
  249 +#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
  250 +#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
  251 +#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
  252 +#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
  253 +#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
  254 +#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
  255 +#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
  256 +#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
  257 +#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
  258 +#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
  259 +
  260 +/* CM2.DSS_CM2 register offsets */
  261 +#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
  262 +#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
  263 +#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
  264 +#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
  265 +#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
  266 +#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
  267 +#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
  268 +#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
  269 +#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
  270 +#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
  271 +
  272 +/* CM2.GFX_CM2 register offsets */
  273 +#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
  274 +#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
  275 +#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
  276 +#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
  277 +#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
  278 +#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
  279 +#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
  280 +#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
  281 +
  282 +/* CM2.L3INIT_CM2 register offsets */
  283 +#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
  284 +#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
  285 +#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
  286 +#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
  287 +#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
  288 +#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
  289 +#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
  290 +#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
  291 +#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
  292 +#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
  293 +#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
  294 +#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
  295 +#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
  296 +#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
  297 +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
  298 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
  299 +#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
  300 +#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
  301 +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
  302 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
  303 +#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
  304 +#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
  305 +#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
  306 +#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
  307 +#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
  308 +#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
  309 +#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
  310 +#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
  311 +#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
  312 +#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
  313 +#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
  314 +#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
  315 +#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
  316 +#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
  317 +#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
  318 +#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
  319 +#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
  320 +#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
  321 +#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
  322 +#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
  323 +
  324 +/* CM2.L4PER_CM2 register offsets */
  325 +#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
  326 +#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
  327 +#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
  328 +#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
  329 +#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
  330 +#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
  331 +#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
  332 +#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
  333 +#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
  334 +#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
  335 +#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
  336 +#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
  337 +#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
  338 +#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
  339 +#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
  340 +#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
  341 +#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
  342 +#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
  343 +#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
  344 +#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
  345 +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
  346 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
  347 +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
  348 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
  349 +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
  350 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
  351 +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
  352 +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
  353 +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
  354 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
  355 +#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
  356 +#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
  357 +#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
  358 +#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
  359 +#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
  360 +#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
  361 +#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
  362 +#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
  363 +#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
  364 +#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
  365 +#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
  366 +#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
  367 +#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
  368 +#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
  369 +#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
  370 +#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
  371 +#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
  372 +#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
  373 +#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
  374 +#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
  375 +#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
  376 +#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
  377 +#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
  378 +#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
  379 +#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
  380 +#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
  381 +#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
  382 +#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
  383 +#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
  384 +#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
  385 +#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
  386 +#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
  387 +#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
  388 +#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
  389 +#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
  390 +#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
  391 +#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
  392 +#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
  393 +#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
  394 +#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
  395 +#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
  396 +#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
  397 +#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
  398 +#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
  399 +#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
  400 +#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
  401 +#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
  402 +#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
  403 +#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
  404 +#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
  405 +#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
  406 +#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
  407 +#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
  408 +#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
  409 +#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
  410 +#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
  411 +#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
  412 +#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
  413 +#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
  414 +#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
  415 +#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
  416 +#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
  417 +#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
  418 +#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
  419 +#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
  420 +#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
  421 +#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
  422 +#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
  423 +#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
  424 +#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
  425 +#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
  426 +#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
  427 +
  428 +/* CM2.CEFUSE_CM2 register offsets */
  429 +#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
  430 +#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
  431 +#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
  432 +#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
  433 +
  434 +/* CM2.RESTORE_CM2 register offsets */
  435 +#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
  436 +#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
  437 +#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
  438 +#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
  439 +#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
  440 +#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
  441 +#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
  442 +#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
  443 +#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
  444 +#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
  445 +#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
  446 +#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
  447 +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
  448 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
  449 +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
  450 +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
  451 +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
  452 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
  453 +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
  454 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
  455 +#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
  456 +#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
  457 +#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
  458 +#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
  459 +#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
  460 +#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
  461 +#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
  462 +#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
  463 +#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
  464 +#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
  465 +#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
  466 +#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
  467 +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
  468 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
  469 +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
  470 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
  471 +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
  472 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
  473 +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
  474 +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
  475 +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
  476 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
  477 +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
  478 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
  479 +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
  480 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
  481 +#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
  482 +#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
  483 +#endif
arch/arm/mach-omap2/cm44xx.h
Diff comments   View file @ d198b51
1 1 /*
2   - * OMAP44xx CM1 & CM2 instance offset macros
  2 + * OMAP4 Clock Management (CM) definitions
3 3 *
4   - * Copyright (C) 2009-2010 Texas Instruments, Inc.
5   - * Copyright (C) 2009-2010 Nokia Corporation
  4 + * Copyright (C) 2007-2009 Texas Instruments, Inc.
  5 + * Copyright (C) 2007-2009 Nokia Corporation
6 6 *
7   - * Paul Walmsley (paul@pwsan.com)
8   - * Rajendra Nayak (rnayak@ti.com)
9   - * Benoit Cousson (b-cousson@ti.com)
  7 + * Written by Paul Walmsley
10 8 *
11   - * This file is automatically generated from the OMAP hardware databases.
12   - * We respectfully ask that any modifications to this file be coordinated
13   - * with the public linux-omap@vger.kernel.org mailing list and the
14   - * authors above to ensure that the autogeneration scripts are kept
15   - * up-to-date with the file contents.
16   - *
17 9 * This program is free software; you can redistribute it and/or modify
18 10 * it under the terms of the GNU General Public License version 2 as
19 11 * published by the Free Software Foundation.
  12 + *
  13 + * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
  14 + * macros and function prototypes that are applicable to both.
20 15 */
  16 +#ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
  17 +#define __ARCH_ASM_MACH_OMAP2_CM44XX_H
21 18  
22   -#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
23   -#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
24 19  
  20 +#include "prcm-common.h"
25 21  
26   -/* CM1 */
  22 +#define OMAP4_CM_CLKSTCTRL 0x0000
27 23  
28   -/* CM1.OCP_SOCKET_CM1 register offsets */
29   -#define OMAP4_REVISION_CM1_OFFSET 0x0000
30   -#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
31   -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
32   -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
  24 +/* Function prototypes */
  25 +# ifndef __ASSEMBLER__
33 26  
34   -/* CM1.CKGEN_CM1 register offsets */
35   -#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
36   -#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
37   -#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
38   -#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
39   -#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
40   -#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
41   -#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
42   -#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
43   -#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
44   -#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
45   -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
46   -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
47   -#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
48   -#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
49   -#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
50   -#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
51   -#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
52   -#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
53   -#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
54   -#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
55   -#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
56   -#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
57   -#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
58   -#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
59   -#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
60   -#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
61   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
62   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
63   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
64   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
65   -#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
66   -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
67   -#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
68   -#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
69   -#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
70   -#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
71   -#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
72   -#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
73   -#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
74   -#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
75   -#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
76   -#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
77   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
78   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
79   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
80   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
81   -#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
82   -#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
83   -#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
84   -#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
85   -#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
86   -#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
87   -#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
88   -#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
89   -#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
90   -#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
91   -#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
92   -#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
93   -#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
94   -#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
95   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
96   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
97   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
98   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
99   -#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
100   -#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
101   -#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
102   -#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
103   -#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
104   -#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
105   -#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
106   -#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
107   -#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
108   -#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
109   -#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
110   -#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
111   -#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
112   -#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
113   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
114   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
115   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
116   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
117   -#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
118   -#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
119   -#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
120   -#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
121   -#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
122   -#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
123   -#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
124   -#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
125   -#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
126   -#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
127   -#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
128   -#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
129   -#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
130   -#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
131   -#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
132   -#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
133   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
134   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
135   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
136   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
137   -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
138   -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
139   -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
140   -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
141   -#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
142   -#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
143   -#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
144   -#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
  27 +extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
145 28  
146   -/* CM1.MPU_CM1 register offsets */
147   -#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
148   -#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
149   -#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
150   -#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
151   -#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
152   -#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
153   -#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
154   -#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
155   -
156   -/* CM1.TESLA_CM1 register offsets */
157   -#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
158   -#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
159   -#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
160   -#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
161   -#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
162   -#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
163   -#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
164   -#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
165   -
166   -/* CM1.ABE_CM1 register offsets */
167   -#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
168   -#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
169   -#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
170   -#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
171   -#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
172   -#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
173   -#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
174   -#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
175   -#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
176   -#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
177   -#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
178   -#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
179   -#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
180   -#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
181   -#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
182   -#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
183   -#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
184   -#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
185   -#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
186   -#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
187   -#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
188   -#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
189   -#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
190   -#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
191   -#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
192   -#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
193   -#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
194   -#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
195   -#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
196   -#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
197   -
198   -/* CM1.RESTORE_CM1 register offsets */
199   -#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
200   -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
201   -#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
202   -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
203   -#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
204   -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
205   -#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
206   -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
207   -#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
208   -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
209   -#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
210   -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
211   -#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
212   -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
213   -#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
214   -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
215   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
216   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
217   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
218   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
219   -#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
220   -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
221   -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
222   -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
223   -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
224   -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
225   -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
226   -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
227   -#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
228   -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
229   -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
230   -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
231   -#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
232   -#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
233   -
234   -/* CM2 */
235   -
236   -/* CM2.OCP_SOCKET_CM2 register offsets */
237   -#define OMAP4_REVISION_CM2_OFFSET 0x0000
238   -#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
239   -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
240   -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
241   -
242   -/* CM2.CKGEN_CM2 register offsets */
243   -#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
244   -#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
245   -#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
246   -#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
247   -#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
248   -#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
249   -#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
250   -#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
251   -#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
252   -#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
253   -#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
254   -#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
255   -#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
256   -#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
257   -#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
258   -#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
259   -#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
260   -#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
261   -#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
262   -#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
263   -#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
264   -#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
265   -#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
266   -#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
267   -#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
268   -#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
269   -#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
270   -#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
271   -#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
272   -#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
273   -#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
274   -#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
275   -#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
276   -#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
277   -#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
278   -#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
279   -#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
280   -#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
281   -#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
282   -#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
283   -#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
284   -#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
285   -#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
286   -#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
287   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
288   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
289   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
290   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
291   -#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
292   -#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
293   -#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
294   -#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
295   -#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
296   -#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
297   -#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
298   -#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
299   -#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
300   -#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
301   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
302   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
303   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
304   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
305   -#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
306   -#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
307   -#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
308   -#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
309   -#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
310   -#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
311   -#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
312   -#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
313   -#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
314   -#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
315   -#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
316   -#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
317   -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
318   -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
319   -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
320   -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
321   -
322   -/* CM2.ALWAYS_ON_CM2 register offsets */
323   -#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
324   -#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
325   -#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
326   -#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
327   -#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
328   -#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
329   -#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
330   -#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
331   -#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
332   -#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
333   -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
334   -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
335   -
336   -/* CM2.CORE_CM2 register offsets */
337   -#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
338   -#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
339   -#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
340   -#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
341   -#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
342   -#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
343   -#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
344   -#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
345   -#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
346   -#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
347   -#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
348   -#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
349   -#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
350   -#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
351   -#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
352   -#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
353   -#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
354   -#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
355   -#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
356   -#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
357   -#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
358   -#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
359   -#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
360   -#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
361   -#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
362   -#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
363   -#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
364   -#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
365   -#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
366   -#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
367   -#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
368   -#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
369   -#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
370   -#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
371   -#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
372   -#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
373   -#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
374   -#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
375   -#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
376   -#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
377   -#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
378   -#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
379   -#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
380   -#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
381   -#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
382   -#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
383   -#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
384   -#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
385   -#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
386   -#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
387   -#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
388   -#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
389   -#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
390   -#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
391   -#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
392   -#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
393   -#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
394   -#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
395   -#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
396   -#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
397   -#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
398   -#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
399   -#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
400   -#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
401   -#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
402   -#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
403   -#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
404   -#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
405   -#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
406   -#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
407   -#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
408   -#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
409   -#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
410   -#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
411   -#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
412   -#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
413   -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
414   -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
415   -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
416   -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
417   -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
418   -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
419   -
420   -/* CM2.IVAHD_CM2 register offsets */
421   -#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
422   -#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
423   -#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
424   -#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
425   -#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
426   -#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
427   -#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
428   -#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
429   -#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
430   -#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
431   -
432   -/* CM2.CAM_CM2 register offsets */
433   -#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
434   -#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
435   -#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
436   -#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
437   -#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
438   -#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
439   -#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
440   -#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
441   -#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
442   -#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
443   -
444   -/* CM2.DSS_CM2 register offsets */
445   -#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
446   -#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
447   -#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
448   -#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
449   -#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
450   -#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
451   -#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
452   -#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
453   -#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
454   -#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
455   -
456   -/* CM2.GFX_CM2 register offsets */
457   -#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
458   -#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
459   -#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
460   -#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
461   -#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
462   -#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
463   -#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
464   -#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
465   -
466   -/* CM2.L3INIT_CM2 register offsets */
467   -#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
468   -#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
469   -#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
470   -#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
471   -#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
472   -#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
473   -#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
474   -#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
475   -#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
476   -#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
477   -#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
478   -#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
479   -#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
480   -#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
481   -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
482   -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
483   -#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
484   -#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
485   -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
486   -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
487   -#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
488   -#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
489   -#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
490   -#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
491   -#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
492   -#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
493   -#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
494   -#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
495   -#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
496   -#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
497   -#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
498   -#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
499   -#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
500   -#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
501   -#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
502   -#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
503   -#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
504   -#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
505   -#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
506   -#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
507   -
508   -/* CM2.L4PER_CM2 register offsets */
509   -#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
510   -#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
511   -#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
512   -#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
513   -#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
514   -#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
515   -#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
516   -#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
517   -#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
518   -#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
519   -#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
520   -#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
521   -#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
522   -#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
523   -#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
524   -#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
525   -#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
526   -#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
527   -#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
528   -#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
529   -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
530   -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
531   -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
532   -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
533   -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
534   -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
535   -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
536   -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
537   -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
538   -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
539   -#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
540   -#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
541   -#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
542   -#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
543   -#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
544   -#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
545   -#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
546   -#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
547   -#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
548   -#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
549   -#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
550   -#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
551   -#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
552   -#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
553   -#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
554   -#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
555   -#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
556   -#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
557   -#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
558   -#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
559   -#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
560   -#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
561   -#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
562   -#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
563   -#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
564   -#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
565   -#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
566   -#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
567   -#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
568   -#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
569   -#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
570   -#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
571   -#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
572   -#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
573   -#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
574   -#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
575   -#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
576   -#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
577   -#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
578   -#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
579   -#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
580   -#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
581   -#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
582   -#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
583   -#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
584   -#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
585   -#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
586   -#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
587   -#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
588   -#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
589   -#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
590   -#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
591   -#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
592   -#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
593   -#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
594   -#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
595   -#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
596   -#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
597   -#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
598   -#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
599   -#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
600   -#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
601   -#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
602   -#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
603   -#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
604   -#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
605   -#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
606   -#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
607   -#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
608   -#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
609   -#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
610   -#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
611   -
612   -/* CM2.CEFUSE_CM2 register offsets */
613   -#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
614   -#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
615   -#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
616   -#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
617   -
618   -/* CM2.RESTORE_CM2 register offsets */
619   -#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
620   -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
621   -#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
622   -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
623   -#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
624   -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
625   -#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
626   -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
627   -#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
628   -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
629   -#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
630   -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
631   -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
632   -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
633   -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
634   -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
635   -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
636   -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
637   -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
638   -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
639   -#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
640   -#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
641   -#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
642   -#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
643   -#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
644   -#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
645   -#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
646   -#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
647   -#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
648   -#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
649   -#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
650   -#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
651   -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
652   -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
653   -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
654   -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
655   -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
656   -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
657   -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
658   -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
659   -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
660   -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
661   -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
662   -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
663   -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
664   -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
665   -#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
666   -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
  29 +# endif
667 30 #endif
arch/arm/mach-omap2/omap_hwmod.c
Diff comments   View file @ d198b51
... ... @@ -147,6 +147,7 @@
147 147  
148 148 #include "cm.h"
149 149 #include "prm.h"
  150 +#include "prm44xx.h"
150 151  
151 152 /* Maximum microseconds to wait for OMAP module to softreset */
152 153 #define MAX_MODULE_SOFTRESET_WAIT 10000
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
Diff comments   View file @ d198b51
... ... @@ -27,7 +27,9 @@
27 27  
28 28 #include "omap_hwmod_common_data.h"
29 29  
30   -#include "cm.h"
  30 +#include "cm1_44xx.h"
  31 +#include "cm2_44xx.h"
  32 +#include "prm44xx.h"
31 33 #include "prm-regbits-44xx.h"
32 34 #include "wd_timer.h"
33 35  
arch/arm/mach-omap2/powerdomain.c
Diff comments   View file @ d198b51
... ... @@ -19,6 +19,7 @@
19 19 #include <linux/list.h>
20 20 #include <linux/errno.h>
21 21 #include <linux/string.h>
  22 +#include "prm44xx.h"
22 23  
23 24 #include <plat/cpu.h>
24 25 #include <plat/powerdomain.h>
arch/arm/mach-omap2/powerdomain44xx.c
Diff comments   View file @ d198b51
... ... @@ -18,7 +18,7 @@
18 18  
19 19 #include <plat/powerdomain.h>
20 20 #include <plat/prcm.h>
21   -#include "prm.h"
  21 +#include "prm44xx.h"
22 22 #include "prm-regbits-44xx.h"
23 23 #include "powerdomains.h"
24 24  
arch/arm/mach-omap2/powerdomains44xx_data.c
Diff comments   View file @ d198b51
... ... @@ -26,10 +26,10 @@
26 26 #include "powerdomains.h"
27 27  
28 28 #include "prcm-common.h"
29   -#include "cm.h"
30   -#include "cm-regbits-44xx.h"
31 29 #include "prm.h"
32 30 #include "prm-regbits-44xx.h"
  31 +#include "prm44xx.h"
  32 +#include "prcm_mpu44xx.h"
33 33  
34 34 /* core_44xx_pwrdm: CORE power domain */
35 35 static struct powerdomain core_44xx_pwrdm = {
arch/arm/mach-omap2/prcm-common.h
Diff comments   View file @ d198b51
... ... @@ -8,15 +8,12 @@
8 8 * Copyright (C) 2007-2009 Nokia Corporation
9 9 *
10 10 * Written by Paul Walmsley
11   - * OMAP4 defines in this file are automatically generated from the OMAP hardware
12   - * databases.
13 11 *
14 12 * This program is free software; you can redistribute it and/or modify
15 13 * it under the terms of the GNU General Public License version 2 as
16 14 * published by the Free Software Foundation.
17 15 */
18 16  
19   -
20 17 /* Module offsets from both CM_BASE & PRM_BASE */
21 18  
22 19 /*
... ... @@ -51,75 +48,6 @@
51 48 #define OMAP3430_NEON_MOD 0xb00
52 49 #define OMAP3430ES2_USBHOST_MOD 0xc00
53 50  
54   -#define BITS(n_bit) \
55   - (((1 << n_bit) - 1) | (1 << n_bit))
56   -
57   -#define BITFIELD(l_bit, u_bit) \
58   - (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
59   -
60   -/* OMAP44XX specific module offsets */
61   -
62   -/* CM1 instances */
63   -
64   -#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
65   -#define OMAP4430_CM1_CKGEN_MOD 0x0100
66   -#define OMAP4430_CM1_MPU_MOD 0x0300
67   -#define OMAP4430_CM1_TESLA_MOD 0x0400
68   -#define OMAP4430_CM1_ABE_MOD 0x0500
69   -#define OMAP4430_CM1_RESTORE_MOD 0x0e00
70   -#define OMAP4430_CM1_INSTR_MOD 0x0f00
71   -
72   -/* CM2 instances */
73   -
74   -#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
75   -#define OMAP4430_CM2_CKGEN_MOD 0x0100
76   -#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
77   -#define OMAP4430_CM2_CORE_MOD 0x0700
78   -#define OMAP4430_CM2_IVAHD_MOD 0x0f00
79   -#define OMAP4430_CM2_CAM_MOD 0x1000
80   -#define OMAP4430_CM2_DSS_MOD 0x1100
81   -#define OMAP4430_CM2_GFX_MOD 0x1200
82   -#define OMAP4430_CM2_L3INIT_MOD 0x1300
83   -#define OMAP4430_CM2_L4PER_MOD 0x1400
84   -#define OMAP4430_CM2_CEFUSE_MOD 0x1600
85   -#define OMAP4430_CM2_RESTORE_MOD 0x1e00
86   -#define OMAP4430_CM2_INSTR_MOD 0x1f00
87   -
88   -/* PRM instances */
89   -
90   -#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
91   -#define OMAP4430_PRM_CKGEN_MOD 0x0100
92   -#define OMAP4430_PRM_MPU_MOD 0x0300
93   -#define OMAP4430_PRM_TESLA_MOD 0x0400
94   -#define OMAP4430_PRM_ABE_MOD 0x0500
95   -#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
96   -#define OMAP4430_PRM_CORE_MOD 0x0700
97   -#define OMAP4430_PRM_IVAHD_MOD 0x0f00
98   -#define OMAP4430_PRM_CAM_MOD 0x1000
99   -#define OMAP4430_PRM_DSS_MOD 0x1100
100   -#define OMAP4430_PRM_GFX_MOD 0x1200
101   -#define OMAP4430_PRM_L3INIT_MOD 0x1300
102   -#define OMAP4430_PRM_L4PER_MOD 0x1400
103   -#define OMAP4430_PRM_CEFUSE_MOD 0x1600
104   -#define OMAP4430_PRM_WKUP_MOD 0x1700
105   -#define OMAP4430_PRM_WKUP_CM_MOD 0x1800
106   -#define OMAP4430_PRM_EMU_MOD 0x1900
107   -#define OMAP4430_PRM_EMU_CM_MOD 0x1a00
108   -#define OMAP4430_PRM_DEVICE_MOD 0x1b00
109   -#define OMAP4430_PRM_INSTR_MOD 0x1f00
110   -
111   -/* SCRM instances */
112   -
113   -#define OMAP4430_SCRM_SCRM_MOD 0x0000
114   -
115   -/* PRCM_MPU instances */
116   -
117   -#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000
118   -#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200
119   -#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400
120   -#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800
121   -
122   -
123 51 /* 24XX register bits shared between CM & PRM registers */
124 52  
125 53 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
... ... @@ -460,6 +388,13 @@
460 388 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
461 389 #define OMAP3430_EN_CORE_SHIFT 0
462 390 #define OMAP3430_EN_CORE_MASK (1 << 0)
  391 +
  392 +
  393 +/*
  394 + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
  395 + * submodule to exit hardreset
  396 + */
  397 +#define MAX_MODULE_HARDRESET_WAIT 10000
463 398  
464 399 #endif
arch/arm/mach-omap2/prcm.c
Diff comments   View file @ d198b51
... ... @@ -31,6 +31,7 @@
31 31 #include "clock2xxx.h"
32 32 #include "cm.h"
33 33 #include "prm.h"
  34 +#include "prm44xx.h"
34 35 #include "prm-regbits-24xx.h"
35 36 #include "prm-regbits-44xx.h"
36 37 #include "control.h"
arch/arm/mach-omap2/prcm_mpu44xx.h
Diff comments   View file @ d198b51
  1 +/*
  2 + * OMAP44xx PRCM MPU instance offset macros
  3 + *
  4 + * Copyright (C) 2010 Texas Instruments, Inc.
  5 + * Copyright (C) 2010 Nokia Corporation
  6 + *
  7 + * Paul Walmsley (paul@pwsan.com)
  8 + * Rajendra Nayak (rnayak@ti.com)
  9 + * Benoit Cousson (b-cousson@ti.com)
  10 + *
  11 + * This file is automatically generated from the OMAP hardware databases.
  12 + * We respectfully ask that any modifications to this file be coordinated
  13 + * with the public linux-omap@vger.kernel.org mailing list and the
  14 + * authors above to ensure that the autogeneration scripts are kept
  15 + * up-to-date with the file contents.
  16 + *
  17 + * This program is free software; you can redistribute it and/or modify
  18 + * it under the terms of the GNU General Public License version 2 as
  19 + * published by the Free Software Foundation.
  20 + *
  21 + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22 + * or "OMAP4430".
  23 + */
  24 +
  25 +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
  26 +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
  27 +
  28 +#define OMAP4430_PRCM_MPU_BASE 0x48243000
  29 +
  30 +#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \
  31 + OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
  32 +
  33 +/* PRCM_MPU instances */
  34 +
  35 +#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000
  36 +#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200
  37 +#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400
  38 +#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800
  39 +
  40 +/*
  41 + * PRCM_MPU
  42 + *
  43 + * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
  44 + * point of view the PRCM_MPU is a single entity. It shares the same
  45 + * programming model as the global PRCM and thus can be assimilate as two new
  46 + * MOD inside the PRCM
  47 + */
  48 +
  49 +/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
  50 +#define OMAP4_REVISION_PRCM_OFFSET 0x0000
  51 +#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
  52 +
  53 +/* PRCM_MPU.DEVICE_PRM register offsets */
  54 +#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
  55 +#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
  56 +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
  57 +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
  58 +
  59 +/* PRCM_MPU.CPU0 register offsets */
  60 +#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
  61 +#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
  62 +#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
  63 +#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
  64 +#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
  65 +#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
  66 +#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
  67 +#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
  68 +#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
  69 +#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
  70 +#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
  71 +#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
  72 +#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
  73 +#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
  74 +
  75 +/* PRCM_MPU.CPU1 register offsets */
  76 +#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
  77 +#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
  78 +#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
  79 +#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
  80 +#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
  81 +#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
  82 +#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
  83 +#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
  84 +#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
  85 +#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
  86 +#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
  87 +#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
  88 +#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
  89 +#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
  90 +
  91 +#endif
arch/arm/mach-omap2/prm.h
Diff comments   View file @ d198b51
... ... @@ -22,13 +22,7 @@
22 22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23 23 #define OMAP34XX_PRM_REGADDR(module, reg) \
24 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25   -#define OMAP44XX_PRM_REGADDR(module, reg) \
26   - OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27   -#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \
28   - OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
29 25  
30   -#include "prm44xx.h"
31   -
32 26 /*
33 27 * Architecture-specific global PRM registers
34 28 * Use __raw_{read,write}l() with these registers.
35 29  
... ... @@ -220,14 +214,7 @@
220 214 #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
221 215 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
222 216  
223   -/* Omap4 specific registers */
224   -#define OMAP4_RM_RSTCTRL 0x0000
225   -#define OMAP4_RM_RSTTIME 0x0004
226   -#define OMAP4_RM_RSTST 0x0008
227   -#define OMAP4_PM_PWSTCTRL 0x0000
228   -#define OMAP4_PM_PWSTST 0x0004
229 217  
230   -
231 218 #ifndef __ASSEMBLER__
232 219  
233 220 /* Power/reset management domain register get/set */
... ... @@ -250,10 +237,6 @@
250 237 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
251 238 int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
252 239 int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
253   -
254   -int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
255   -int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
256   -int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
257 240  
258 241 #endif
259 242  
arch/arm/mach-omap2/prm44xx.c
Diff comments   View file @ d198b51
... ... @@ -20,7 +20,7 @@
20 20 #include <plat/cpu.h>
21 21 #include <plat/prcm.h>
22 22  
23   -#include "prm.h"
  23 +#include "prm44xx.h"
24 24 #include "prm-regbits-44xx.h"
25 25  
26 26 /*
arch/arm/mach-omap2/prm44xx.h
Diff comments   View file @ d198b51
... ... @@ -17,12 +17,53 @@
17 17 * This program is free software; you can redistribute it and/or modify
18 18 * it under the terms of the GNU General Public License version 2 as
19 19 * published by the Free Software Foundation.
  20 + *
  21 + * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22 + * or "OMAP4430".
20 23 */
21 24  
22 25 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
23 26 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
24 27  
  28 +#include "prcm-common.h"
25 29  
  30 +#define OMAP4430_PRM_BASE 0x4a306000
  31 +
  32 +#define OMAP44XX_PRM_REGADDR(module, reg) \
  33 + OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
  34 +
  35 +
  36 +/* PRM instances */
  37 +#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
  38 +#define OMAP4430_PRM_CKGEN_MOD 0x0100
  39 +#define OMAP4430_PRM_MPU_MOD 0x0300
  40 +#define OMAP4430_PRM_TESLA_MOD 0x0400
  41 +#define OMAP4430_PRM_ABE_MOD 0x0500
  42 +#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
  43 +#define OMAP4430_PRM_CORE_MOD 0x0700
  44 +#define OMAP4430_PRM_IVAHD_MOD 0x0f00
  45 +#define OMAP4430_PRM_CAM_MOD 0x1000
  46 +#define OMAP4430_PRM_DSS_MOD 0x1100
  47 +#define OMAP4430_PRM_GFX_MOD 0x1200
  48 +#define OMAP4430_PRM_L3INIT_MOD 0x1300
  49 +#define OMAP4430_PRM_L4PER_MOD 0x1400
  50 +#define OMAP4430_PRM_CEFUSE_MOD 0x1600
  51 +#define OMAP4430_PRM_WKUP_MOD 0x1700
  52 +#define OMAP4430_PRM_WKUP_CM_MOD 0x1800
  53 +#define OMAP4430_PRM_EMU_MOD 0x1900
  54 +#define OMAP4430_PRM_EMU_CM_MOD 0x1a00
  55 +#define OMAP4430_PRM_DEVICE_MOD 0x1b00
  56 +#define OMAP4430_PRM_INSTR_MOD 0x1f00
  57 +
  58 +
  59 +/* OMAP4 specific register offsets */
  60 +#define OMAP4_RM_RSTCTRL 0x0000
  61 +#define OMAP4_RM_RSTTIME 0x0004
  62 +#define OMAP4_RM_RSTST 0x0008
  63 +#define OMAP4_PM_PWSTCTRL 0x0000
  64 +#define OMAP4_PM_PWSTST 0x0004
  65 +
  66 +
26 67 /* PRM */
27 68  
28 69 /* PRM.OCP_SOCKET_PRM register offsets */
29 70  
30 71  
31 72  
32 73  
... ... @@ -699,55 +740,23 @@
699 740 #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
700 741 #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
701 742  
702   -/*
703   - * PRCM_MPU
704   - *
705   - * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
706   - * point of view the PRCM_MPU is a single entity. It shares the same
707   - * programming model as the global PRCM and thus can be assimilate as two new
708   - * MOD inside the PRCM
709   - */
  743 +/* Function prototypes */
  744 +# ifndef __ASSEMBLER__
710 745  
711   -/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
712   -#define OMAP4_REVISION_PRCM_OFFSET 0x0000
713   -#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
  746 +extern u32 omap4_prm_read_mod_reg(s16 module, u16 idx);
  747 +extern void omap4_prm_write_mod_reg(u32 val, s16 module, u16 idx);
  748 +extern u32 omap4_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
  749 +extern u32 omap4_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
  750 +extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
  751 +extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
  752 +extern u32 omap4_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
  753 +extern u32 omap4_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
714 754  
715   -/* PRCM_MPU.DEVICE_PRM register offsets */
716   -#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
717   -#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
718   -#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
719   -#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
  755 +extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
  756 +extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
  757 +extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
720 758  
721   -/* PRCM_MPU.CPU0 register offsets */
722   -#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
723   -#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
724   -#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
725   -#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
726   -#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
727   -#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
728   -#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
729   -#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
730   -#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
731   -#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
732   -#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
733   -#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
734   -#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
735   -#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
  759 +# endif
736 760  
737   -/* PRCM_MPU.CPU1 register offsets */
738   -#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
739   -#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
740   -#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
741   -#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
742   -#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
743   -#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
744   -#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
745   -#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
746   -#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
747   -#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
748   -#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
749   -#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
750   -#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
751   -#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
752 761 #endif