OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory

Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This is to prevent the ARM from evicting existing cache lines to SDRAM while code is executing from the SRAM. Necessary since one of the primary uses for the SRAM is to hold the code and data for the CORE DPLL M2 divider reprogramming code, which must execute while the SDRC is idled. If the ARM attempts to write cache lines back to the while the SRAM code is running, the ARM will stall[2]. TI deals with this problem in the CDP kernel by marking the SRAM as Strongly-ordered memory. Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of this patch - thanks Tero. ... 1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Richard Woodruff <r-woodruff2@ti.com>

OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory
Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This is to prevent the ARM from evicting existing cache lines to SDRAM while code is executing from the SRAM. Necessary since one of the primary uses for the SRAM is to hold the code and data for the CORE DPLL M2 divider reprogramming code, which must execute while the SDRC is idled. If the ARM attempts to write cache lines back to the while the SRAM code is running, the ARM will stall[2]. TI deals with this problem in the CDP kernel by marking the SRAM as Strongly-ordered memory. Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of this patch - thanks Tero. ... 1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley · paul
1 parent 1d80cac0fe
Showing 1 changed file with 9 additions and 0 deletions Side-by-side Diff
arch/arm/plat-omap/sram.c
@@ -201,6 +201,15 @@
 		base = OMAP3_SRAM_PA;
 		base = ROUND_DOWN(base, PAGE_SIZE);
 		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+		/*
+		 * SRAM must be marked as non-cached on OMAP3 since the
+		 * CORE DPLL M2 divider change code (in SRAM) runs with the
+		 * SDRAM controller disabled, and if it is marked cached,
+		 * the ARM may attempt to write cache lines back to SDRAM
+		 * which will cause the system to hang.
+		 */
+		omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 	}
  
 	omap_sram_io_desc[0].length = 1024 * 1024;	/* Use section desc */
...	...	@@ -201,6 +201,15 @@
201	201	base = OMAP3_SRAM_PA;
202	202	base = ROUND_DOWN(base, PAGE_SIZE);
203	203	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	204	+
	205	+ /*
	206	+ * SRAM must be marked as non-cached on OMAP3 since the
	207	+ * CORE DPLL M2 divider change code (in SRAM) runs with the
	208	+ * SDRAM controller disabled, and if it is marked cached,
	209	+ * the ARM may attempt to write cache lines back to SDRAM
	210	+ * which will cause the system to hang.
	211	+ */
	212	+ omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
204	213	}
205	214
206	215	omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */