Commit dac9a77120e2724e22696f06f3ecb4838da1e3e4
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OMAP4: PRCM: move global reset function for OMAP4 to an OMAP4-specific file
Move the OMAP4 global software reset function to the OMAP4-specific prm44xx.c file, where it belongs. Part of the long-term process of moving all of the direct PRCM register writes into lower-layer code. Also add OCP barriers on OMAP2/3/4 to reduce the chance that the MPU will continue executing while the system is supposed to be resetting itself. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com>
Showing 3 changed files with 24 additions and 9 deletions Side-by-side Diff
arch/arm/mach-omap2/prcm.c
| ... | ... | @@ -68,17 +68,16 @@ |
| 68 | 68 | } else if (cpu_is_omap34xx()) { |
| 69 | 69 | prcm_offs = OMAP3430_GR_MOD; |
| 70 | 70 | omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); |
| 71 | - } else if (cpu_is_omap44xx()) | |
| 72 | - prcm_offs = OMAP4430_PRM_DEVICE_INST; | |
| 73 | - else | |
| 71 | + } else if (cpu_is_omap44xx()) { | |
| 72 | + omap4_prm_global_warm_sw_reset(); /* never returns */ | |
| 73 | + } else { | |
| 74 | 74 | WARN_ON(1); |
| 75 | + } | |
| 75 | 76 | |
| 76 | - if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
| 77 | - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, | |
| 78 | - OMAP2_RM_RSTCTRL); | |
| 79 | - if (cpu_is_omap44xx()) | |
| 80 | - prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, | |
| 81 | - prcm_offs, OMAP4_RM_RSTCTRL); | |
| 77 | + /* XXX should be moved to some OMAP2/3 specific code */ | |
| 78 | + prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, | |
| 79 | + OMAP2_RM_RSTCTRL); | |
| 80 | + prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ | |
| 82 | 81 | } |
| 83 | 82 | |
| 84 | 83 | /** |
arch/arm/mach-omap2/prm44xx.c
| ... | ... | @@ -178,4 +178,19 @@ |
| 178 | 178 | |
| 179 | 179 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; |
| 180 | 180 | } |
| 181 | + | |
| 182 | +void omap4_prm_global_warm_sw_reset(void) | |
| 183 | +{ | |
| 184 | + u32 v; | |
| 185 | + | |
| 186 | + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | |
| 187 | + OMAP4_RM_RSTCTRL); | |
| 188 | + v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; | |
| 189 | + omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST, | |
| 190 | + OMAP4_RM_RSTCTRL); | |
| 191 | + | |
| 192 | + /* OCP barrier */ | |
| 193 | + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | |
| 194 | + OMAP4_RM_RSTCTRL); | |
| 195 | +} |
arch/arm/mach-omap2/prm44xx.h
| ... | ... | @@ -756,6 +756,8 @@ |
| 756 | 756 | extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); |
| 757 | 757 | extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); |
| 758 | 758 | |
| 759 | +extern void omap4_prm_global_warm_sw_reset(void); | |
| 760 | + | |
| 759 | 761 | # endif |
| 760 | 762 | |
| 761 | 763 | #endif |