Commit dce7c33de026e3fa032cbc8ffdde535ed3ab429b
1 parent
3da199c9e4
Exists in
master
arch:arm:omap:Remove duplicate macros from DPLL state
Irrespective of cpu-type, aren't ee supposed to do
same thing for any bypass cases (LPBYPASS/FRBYPASS/MNBYPASS),
- dpll clock reparenting
- get dpll rate
This patch cleans up the code and removes the
unneccessary cpu check.
Showing 2 changed files with 4 additions and 15 deletions Side-by-side Diff
arch/arm/mach-omap2/clkt_dpll.c
| ... | ... | @@ -187,13 +187,9 @@ |
| 187 | 187 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || |
| 188 | 188 | v == OMAP2XXX_EN_DPLL_FRBYPASS) |
| 189 | 189 | clk_reparent(clk, dd->clk_bypass); |
| 190 | - } else if (cpu_is_omap34xx()) { | |
| 190 | + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
| 191 | 191 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
| 192 | - v == OMAP3XXX_EN_DPLL_FRBYPASS) | |
| 193 | - clk_reparent(clk, dd->clk_bypass); | |
| 194 | - } else if (cpu_is_omap44xx()) { | |
| 195 | - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | |
| 196 | - v == OMAP4XXX_EN_DPLL_FRBYPASS || | |
| 192 | + v == OMAP3XXX_EN_DPLL_FRBYPASS || | |
| 197 | 193 | v == OMAP4XXX_EN_DPLL_MNBYPASS) |
| 198 | 194 | clk_reparent(clk, dd->clk_bypass); |
| 199 | 195 | } |
| 200 | 196 | |
| ... | ... | @@ -233,13 +229,9 @@ |
| 233 | 229 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || |
| 234 | 230 | v == OMAP2XXX_EN_DPLL_FRBYPASS) |
| 235 | 231 | return dd->clk_bypass->rate; |
| 236 | - } else if (cpu_is_omap34xx()) { | |
| 232 | + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
| 237 | 233 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
| 238 | - v == OMAP3XXX_EN_DPLL_FRBYPASS) | |
| 239 | - return dd->clk_bypass->rate; | |
| 240 | - } else if (cpu_is_omap44xx()) { | |
| 241 | - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | |
| 242 | - v == OMAP4XXX_EN_DPLL_FRBYPASS || | |
| 234 | + v == OMAP3XXX_EN_DPLL_FRBYPASS || | |
| 243 | 235 | v == OMAP4XXX_EN_DPLL_MNBYPASS) |
| 244 | 236 | return dd->clk_bypass->rate; |
| 245 | 237 | } |
arch/arm/mach-omap2/clock.h
| ... | ... | @@ -37,9 +37,6 @@ |
| 37 | 37 | |
| 38 | 38 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 39 | 39 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 |
| 40 | -#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | |
| 41 | -#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | |
| 42 | -#define OMAP4XXX_EN_DPLL_LOCKED 0x7 | |
| 43 | 40 | |
| 44 | 41 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 45 | 42 | #define DPLL_LOW_POWER_STOP 0x1 |