OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros

The RSTCTRL register was accessed using an absolute address. The usage of hardcoded macros to calculate virtual address from physical one should be avoided as much as possible. The usage of an offset will allow future improvement like migration from the current architecture code toward a module driver. Update prm_xxx accessors, move definition to the proper header file and update copyrights. Change the s16 register offset parameter to u16. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: use '_prminst_' in function names that are part of the prminst44xx.c file] Signed-off-by: Paul Walmsley <paul@pwsan.com>

OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros
The RSTCTRL register was accessed using an absolute address. The usage of hardcoded macros to calculate virtual address from physical one should be avoided as much as possible. The usage of an offset will allow future improvement like migration from the current architecture code toward a module driver. Update prm_xxx accessors, move definition to the proper header file and update copyrights. Change the s16 register offset parameter to u16. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: use '_prminst_' in function names that are part of the prminst44xx.c file] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Benoit Cousson · Paul Walmsley
1 parent 11b10341bd
Showing 7 changed files with 125 additions and 113 deletions Side-by-side Diff
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-omap2/prm44xx.h
arch/arm/mach-omap2/prminst44xx.c
arch/arm/mach-omap2/prminst44xx.h
arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -149,6 +149,7 @@
 #include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prminst44xx.h"
 #include "mux.h"
  
 /* Maximum microseconds to wait for OMAP module to softreset */
@@ -1187,8 +1188,10 @@
 		return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
 						  ohri.rst_shift);
 	else if (cpu_is_omap44xx())
-		return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
-						  ohri.rst_shift);
+		return omap4_prminst_assert_hardreset(ohri.rst_shift,
+				  oh->clkdm->pwrdm.ptr->prcm_partition,
+				  oh->clkdm->pwrdm.ptr->prcm_offs,
+				  oh->prcm.omap4.rstctrl_offs);
 	else
 		return -EINVAL;
 }
@@ -1223,8 +1226,10 @@
 		if (ohri.st_shift)
 			pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
 			       oh->name, name);
-		ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
-						   ohri.rst_shift);
+		ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
+				  oh->clkdm->pwrdm.ptr->prcm_partition,
+				  oh->clkdm->pwrdm.ptr->prcm_offs,
+				  oh->prcm.omap4.rstctrl_offs);
 	} else {
 		return -EINVAL;
 	}
@@ -1259,8 +1264,10 @@
 		return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
 						       ohri.st_shift);
 	} else if (cpu_is_omap44xx()) {
-		return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
-						       ohri.rst_shift);
+		return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
+				  oh->clkdm->pwrdm.ptr->prcm_partition,
+				  oh->clkdm->pwrdm.ptr->prcm_offs,
+				  oh->prcm.omap4.rstctrl_offs);
 	} else {
 		return -EINVAL;
 	}
@@ -1144,7 +1144,7 @@
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_c0_resets),
 	.prcm = {
 		.omap4 = {
-			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 		},
 	},
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1161,7 +1161,7 @@
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
-			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 		},
 	},
 	.slaves		= omap44xx_dsp_slaves,
@@ -2526,7 +2526,7 @@
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c0_resets),
 	.prcm = {
 		.omap4 = {
-			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
 		},
 	},
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2542,7 +2542,7 @@
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c1_resets),
 	.prcm = {
 		.omap4 = {
-			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
 		},
 	},
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2559,7 +2559,7 @@
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
-			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
 		},
 	},
 	.slaves		= omap44xx_ipu_slaves,
@@ -2726,7 +2726,7 @@
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq0_resets),
 	.prcm = {
 		.omap4 = {
-			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 		},
 	},
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2742,7 +2742,7 @@
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq1_resets),
 	.prcm = {
 		.omap4 = {
-			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 		},
 	},
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2759,7 +2759,7 @@
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
-			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 		},
 	},
 	.slaves		= omap44xx_iva_slaves,
 /*
  * OMAP4 PRM module functions
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Copyright (C) 2010 Nokia Corporation
  * Benoît Cousson
  * Paul Walmsley
@@ -24,12 +24,6 @@
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
  
-/*
- * Address offset (in bytes) between the reset control and the reset
- * status registers: 4 bytes on OMAP4
- */
-#define OMAP4_RST_CTRL_ST_OFFSET		4
-
 /* PRM low-level functions */
  
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -92,91 +86,6 @@
 u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
 {
 	return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
-}
-
-/**
- * omap4_prm_is_hardreset_asserted - read the HW reset line state of
- * submodules contained in the hwmod module
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to check
- *
- * Returns 1 if the (sub)module hardreset line is currently asserted,
- * 0 if the (sub)module hardreset line is not currently asserted, or
- * -EINVAL upon parameter error.
- */
-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
-{
-	if (!cpu_is_omap44xx() || !rstctrl_reg)
-		return -EINVAL;
-
-	return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
-}
-
-/**
- * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to assert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP.  These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block.  This function will
- * place the submodule into reset.  Returns 0 upon success or -EINVAL
- * upon an argument error.
- */
-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
-	u32 mask;
-
-	if (!cpu_is_omap44xx() || !rstctrl_reg)
-		return -EINVAL;
-
-	mask = 1 << shift;
-	omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
-
-	return 0;
-}
-
-/**
- * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to deassert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP.  These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block.  This function will
- * take the submodule out of reset and wait until the PRCM indicates
- * that the reset has completed before returning.  Returns 0 upon success or
- * -EINVAL upon an argument error, -EEXIST if the submodule was already out
- * of reset, or -EBUSY if the submodule did not exit reset promptly.
- */
-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
-	u32 mask;
-	void __iomem *rstst_reg;
-	int c;
-
-	if (!cpu_is_omap44xx() || !rstctrl_reg)
-		return -EINVAL;
-
-	rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
-
-	mask = 1 << shift;
-
-	/* Check the current status to avoid de-asserting the line twice */
-	if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
-		return -EEXIST;
-
-	/* Clear the reset status by writing 1 to the status bit */
-	omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
-	/* de-assert the reset control line */
-	omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
-	/* wait the status to be set */
-	omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
-			  MAX_MODULE_HARDRESET_WAIT, c);
-
-	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
  
 void omap4_prm_global_warm_sw_reset(void)
@@ -755,10 +755,6 @@
 extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
 extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
  
-extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-
 extern void omap4_prm_global_warm_sw_reset(void);
  
 # endif
@@ -2,6 +2,7 @@
  * OMAP4 PRM instance functions
  *
  * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -53,7 +54,7 @@
  
 /* Read-modify-write a register in PRM. Caller must lock */
 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
-				   s16 idx)
+				    u16 idx)
 {
 	u32 v;
  
@@ -63,5 +64,95 @@
 	omap4_prminst_write_inst_reg(v, part, inst, idx);
  
 	return v;
+}
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET		4
+
+/**
+ * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+					u16 rstctrl_offs)
+{
+	u32 v;
+
+	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
+	v &= 1 << shift;
+	v >>= shift;
+
+	return v;
+}
+
+/**
+ * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+				   u16 rstctrl_offs)
+{
+	u32 mask = 1 << shift;
+
+	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
+
+	return 0;
+}
+
+/**
+ * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+				     u16 rstctrl_offs)
+{
+	int c;
+	u32 mask = 1 << shift;
+	u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
+
+	/* Check the current status to avoid de-asserting the line twice */
+	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
+						rstctrl_offs) == 0)
+		return -EEXIST;
+
+	/* Clear the reset status by writing 1 to the status bit */
+	omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
+					rstst_offs);
+	/* de-assert the reset control line */
+	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
+	/* wait the status to be set */
+	omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
+							      rstst_offs),
+			  MAX_MODULE_HARDRESET_WAIT, c);
+
+	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
@@ -2,6 +2,7 @@
  * OMAP4 Power/Reset Management (PRM) function prototypes
  *
  * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  
@@ -18,9 +19,16 @@
 extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
 extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
 extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-					   s16 inst, s16 idx);
+					   s16 inst, u16 idx);
  
 extern void omap4_prm_global_warm_sw_reset(void);
+
+extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+					   u16 rstctrl_offs);
+extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+				      u16 rstctrl_offs);
+extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+					u16 rstctrl_offs);
  
 #endif
@@ -2,6 +2,7 @@
  * omap_hwmod macros, structures
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -361,7 +362,7 @@
  */
 struct omap_hwmod_omap4_prcm {
 	u16		clkctrl_offs;
-	void __iomem	*rstctrl_reg;
+	u16		rstctrl_offs;
 	u8		submodule_wkdep_bit;
 };
...	...	@@ -149,6 +149,7 @@
149	149	#include "cminst44xx.h"
150	150	#include "prm2xxx_3xxx.h"
151	151	#include "prm44xx.h"
	152	+#include "prminst44xx.h"
152	153	#include "mux.h"
153	154
154	155	/* Maximum microseconds to wait for OMAP module to softreset */
...	...	@@ -1187,8 +1188,10 @@
1187	1188	return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
1188	1189	ohri.rst_shift);
1189	1190	else if (cpu_is_omap44xx())
1190		- return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
1191		- ohri.rst_shift);
	1191	+ return omap4_prminst_assert_hardreset(ohri.rst_shift,
	1192	+ oh->clkdm->pwrdm.ptr->prcm_partition,
	1193	+ oh->clkdm->pwrdm.ptr->prcm_offs,
	1194	+ oh->prcm.omap4.rstctrl_offs);
1192	1195	else
1193	1196	return -EINVAL;
1194	1197	}
...	...	@@ -1223,8 +1226,10 @@
1223	1226	if (ohri.st_shift)
1224	1227	pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
1225	1228	oh->name, name);
1226		- ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
1227		- ohri.rst_shift);
	1229	+ ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
	1230	+ oh->clkdm->pwrdm.ptr->prcm_partition,
	1231	+ oh->clkdm->pwrdm.ptr->prcm_offs,
	1232	+ oh->prcm.omap4.rstctrl_offs);
1228	1233	} else {
1229	1234	return -EINVAL;
1230	1235	}
...	...	@@ -1259,8 +1264,10 @@
1259	1264	return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1260	1265	ohri.st_shift);
1261	1266	} else if (cpu_is_omap44xx()) {
1262		- return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
1263		- ohri.rst_shift);
	1267	+ return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
	1268	+ oh->clkdm->pwrdm.ptr->prcm_partition,
	1269	+ oh->clkdm->pwrdm.ptr->prcm_offs,
	1270	+ oh->prcm.omap4.rstctrl_offs);
1264	1271	} else {
1265	1272	return -EINVAL;
1266	1273	}
...	...	@@ -1144,7 +1144,7 @@
1144	1144	.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1145	1145	.prcm = {
1146	1146	.omap4 = {
1147		- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
	1147	+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1148	1148	},
1149	1149	},
1150	1150	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
...	...	@@ -1161,7 +1161,7 @@
1161	1161	.prcm = {
1162	1162	.omap4 = {
1163	1163	.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1164		- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
	1164	+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1165	1165	},
1166	1166	},
1167	1167	.slaves = omap44xx_dsp_slaves,
...	...	@@ -2526,7 +2526,7 @@
2526	2526	.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2527	2527	.prcm = {
2528	2528	.omap4 = {
2529		- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
	2529	+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2530	2530	},
2531	2531	},
2532	2532	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
...	...	@@ -2542,7 +2542,7 @@
2542	2542	.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2543	2543	.prcm = {
2544	2544	.omap4 = {
2545		- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
	2545	+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2546	2546	},
2547	2547	},
2548	2548	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
...	...	@@ -2559,7 +2559,7 @@
2559	2559	.prcm = {
2560	2560	.omap4 = {
2561	2561	.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2562		- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
	2562	+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563	2563	},
2564	2564	},
2565	2565	.slaves = omap44xx_ipu_slaves,
...	...	@@ -2726,7 +2726,7 @@
2726	2726	.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2727	2727	.prcm = {
2728	2728	.omap4 = {
2729		- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
	2729	+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2730	2730	},
2731	2731	},
2732	2732	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
...	...	@@ -2742,7 +2742,7 @@
2742	2742	.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2743	2743	.prcm = {
2744	2744	.omap4 = {
2745		- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
	2745	+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2746	2746	},
2747	2747	},
2748	2748	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
...	...	@@ -2759,7 +2759,7 @@
2759	2759	.prcm = {
2760	2760	.omap4 = {
2761	2761	.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2762		- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
	2762	+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2763	2763	},
2764	2764	},
2765	2765	.slaves = omap44xx_iva_slaves,
1	1	/*
2	2	* OMAP4 PRM module functions
3	3	*
4		- * Copyright (C) 2010 Texas Instruments, Inc.
	4	+ * Copyright (C) 2011 Texas Instruments, Inc.
5	5	* Copyright (C) 2010 Nokia Corporation
6	6	* Benoît Cousson
7	7	* Paul Walmsley
...	...	@@ -24,12 +24,6 @@
24	24	#include "prm44xx.h"
25	25	#include "prm-regbits-44xx.h"
26	26
27		-/*
28		- * Address offset (in bytes) between the reset control and the reset
29		- * status registers: 4 bytes on OMAP4
30		- */
31		-#define OMAP4_RST_CTRL_ST_OFFSET 4
32		-
33	27	/* PRM low-level functions */
34	28
35	29	/* Read a register in a CM/PRM instance in the PRM module */
...	...	@@ -92,91 +86,6 @@
92	86	u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
93	87	{
94	88	return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
95		-}
96		-
97		-/**
98		- * omap4_prm_is_hardreset_asserted - read the HW reset line state of
99		- * submodules contained in the hwmod module
100		- * @rstctrl_reg: RM_RSTCTRL register address for this module
101		- * @shift: register bit shift corresponding to the reset line to check
102		- *
103		- * Returns 1 if the (sub)module hardreset line is currently asserted,
104		- * 0 if the (sub)module hardreset line is not currently asserted, or
105		- * -EINVAL upon parameter error.
106		- */
107		-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
108		-{
109		- if (!cpu_is_omap44xx() \|\| !rstctrl_reg)
110		- return -EINVAL;
111		-
112		- return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
113		-}
114		-
115		-/**
116		- * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
117		- * @rstctrl_reg: RM_RSTCTRL register address for this module
118		- * @shift: register bit shift corresponding to the reset line to assert
119		- *
120		- * Some IPs like dsp, ipu or iva contain processors that require an HW
121		- * reset line to be asserted / deasserted in order to fully enable the
122		- * IP. These modules may have multiple hard-reset lines that reset
123		- * different 'submodules' inside the IP block. This function will
124		- * place the submodule into reset. Returns 0 upon success or -EINVAL
125		- * upon an argument error.
126		- */
127		-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
128		-{
129		- u32 mask;
130		-
131		- if (!cpu_is_omap44xx() \|\| !rstctrl_reg)
132		- return -EINVAL;
133		-
134		- mask = 1 << shift;
135		- omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
136		-
137		- return 0;
138		-}
139		-
140		-/**
141		- * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
142		- * @rstctrl_reg: RM_RSTCTRL register address for this module
143		- * @shift: register bit shift corresponding to the reset line to deassert
144		- *
145		- * Some IPs like dsp, ipu or iva contain processors that require an HW
146		- * reset line to be asserted / deasserted in order to fully enable the
147		- * IP. These modules may have multiple hard-reset lines that reset
148		- * different 'submodules' inside the IP block. This function will
149		- * take the submodule out of reset and wait until the PRCM indicates
150		- * that the reset has completed before returning. Returns 0 upon success or
151		- * -EINVAL upon an argument error, -EEXIST if the submodule was already out
152		- * of reset, or -EBUSY if the submodule did not exit reset promptly.
153		- */
154		-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
155		-{
156		- u32 mask;
157		- void __iomem *rstst_reg;
158		- int c;
159		-
160		- if (!cpu_is_omap44xx() \|\| !rstctrl_reg)
161		- return -EINVAL;
162		-
163		- rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
164		-
165		- mask = 1 << shift;
166		-
167		- /* Check the current status to avoid de-asserting the line twice */
168		- if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
169		- return -EEXIST;
170		-
171		- /* Clear the reset status by writing 1 to the status bit */
172		- omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
173		- /* de-assert the reset control line */
174		- omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
175		- /* wait the status to be set */
176		- omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
177		- MAX_MODULE_HARDRESET_WAIT, c);
178		-
179		- return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
180	89	}
181	90
182	91	void omap4_prm_global_warm_sw_reset(void)
...	...	@@ -755,10 +755,6 @@
755	755	extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
756	756	extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
757	757
758		-extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
759		-extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
760		-extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
761		-
762	758	extern void omap4_prm_global_warm_sw_reset(void);
763	759
764	760	# endif
...	...	@@ -2,6 +2,7 @@
2	2	* OMAP4 PRM instance functions
3	3	*
4	4	* Copyright (C) 2009 Nokia Corporation
	5	+ * Copyright (C) 2011 Texas Instruments, Inc.
5	6	* Paul Walmsley
6	7	*
7	8	* This program is free software; you can redistribute it and/or modify
...	...	@@ -53,7 +54,7 @@
53	54
54	55	/* Read-modify-write a register in PRM. Caller must lock */
55	56	u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
56		- s16 idx)
	57	+ u16 idx)
57	58	{
58	59	u32 v;
59	60
...	...	@@ -63,5 +64,95 @@
63	64	omap4_prminst_write_inst_reg(v, part, inst, idx);
64	65
65	66	return v;
	67	+}
	68	+
	69	+/*
	70	+ * Address offset (in bytes) between the reset control and the reset
	71	+ * status registers: 4 bytes on OMAP4
	72	+ */
	73	+#define OMAP4_RST_CTRL_ST_OFFSET 4
	74	+
	75	+/**
	76	+ * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
	77	+ * submodules contained in the hwmod module
	78	+ * @rstctrl_reg: RM_RSTCTRL register address for this module
	79	+ * @shift: register bit shift corresponding to the reset line to check
	80	+ *
	81	+ * Returns 1 if the (sub)module hardreset line is currently asserted,
	82	+ * 0 if the (sub)module hardreset line is not currently asserted, or
	83	+ * -EINVAL upon parameter error.
	84	+ */
	85	+int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
	86	+ u16 rstctrl_offs)
	87	+{
	88	+ u32 v;
	89	+
	90	+ v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
	91	+ v &= 1 << shift;
	92	+ v >>= shift;
	93	+
	94	+ return v;
	95	+}
	96	+
	97	+/**
	98	+ * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
	99	+ * @rstctrl_reg: RM_RSTCTRL register address for this module
	100	+ * @shift: register bit shift corresponding to the reset line to assert
	101	+ *
	102	+ * Some IPs like dsp, ipu or iva contain processors that require an HW
	103	+ * reset line to be asserted / deasserted in order to fully enable the
	104	+ * IP. These modules may have multiple hard-reset lines that reset
	105	+ * different 'submodules' inside the IP block. This function will
	106	+ * place the submodule into reset. Returns 0 upon success or -EINVAL
	107	+ * upon an argument error.
	108	+ */
	109	+int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
	110	+ u16 rstctrl_offs)
	111	+{
	112	+ u32 mask = 1 << shift;
	113	+
	114	+ omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
	115	+
	116	+ return 0;
	117	+}
	118	+
	119	+/**
	120	+ * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
	121	+ * wait
	122	+ * @rstctrl_reg: RM_RSTCTRL register address for this module
	123	+ * @shift: register bit shift corresponding to the reset line to deassert
	124	+ *
	125	+ * Some IPs like dsp, ipu or iva contain processors that require an HW
	126	+ * reset line to be asserted / deasserted in order to fully enable the
	127	+ * IP. These modules may have multiple hard-reset lines that reset
	128	+ * different 'submodules' inside the IP block. This function will
	129	+ * take the submodule out of reset and wait until the PRCM indicates
	130	+ * that the reset has completed before returning. Returns 0 upon success or
	131	+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
	132	+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
	133	+ */
	134	+int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
	135	+ u16 rstctrl_offs)
	136	+{
	137	+ int c;
	138	+ u32 mask = 1 << shift;
	139	+ u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
	140	+
	141	+ /* Check the current status to avoid de-asserting the line twice */
	142	+ if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
	143	+ rstctrl_offs) == 0)
	144	+ return -EEXIST;
	145	+
	146	+ /* Clear the reset status by writing 1 to the status bit */
	147	+ omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
	148	+ rstst_offs);
	149	+ /* de-assert the reset control line */
	150	+ omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
	151	+ /* wait the status to be set */
	152	+ omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
	153	+ rstst_offs),
	154	+ MAX_MODULE_HARDRESET_WAIT, c);
	155	+
	156	+ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
66	157	}
...	...	@@ -2,6 +2,7 @@
2	2	* OMAP4 Power/Reset Management (PRM) function prototypes
3	3	*
4	4	* Copyright (C) 2010 Nokia Corporation
	5	+ * Copyright (C) 2011 Texas Instruments, Inc.
5	6	* Paul Walmsley
6	7	*
7	8	* This program is free software; you can redistribute it and/or modify
8	9
...	...	@@ -18,9 +19,16 @@
18	19	extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
19	20	extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
20	21	extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
21		- s16 inst, s16 idx);
	22	+ s16 inst, u16 idx);
22	23
23	24	extern void omap4_prm_global_warm_sw_reset(void);
	25	+
	26	+extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
	27	+ u16 rstctrl_offs);
	28	+extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
	29	+ u16 rstctrl_offs);
	30	+extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
	31	+ u16 rstctrl_offs);
24	32
25	33	#endif
...	...	@@ -2,6 +2,7 @@
2	2	* omap_hwmod macros, structures
3	3	*
4	4	* Copyright (C) 2009-2011 Nokia Corporation
	5	+ * Copyright (C) 2011 Texas Instruments, Inc.
5	6	* Paul Walmsley
6	7	*
7	8	* Created in collaboration with (alphabetical order): Benoît Cousson,
...	...	@@ -361,7 +362,7 @@
361	362	*/
362	363	struct omap_hwmod_omap4_prcm {
363	364	u16 clkctrl_offs;
364		- void __iomem *rstctrl_reg;
	365	+ u16 rstctrl_offs;
365	366	u8 submodule_wkdep_bit;
366	367	};
367	368