Commit ed5b9fa0d1c5ad1e01ff56b9acd3ff52bc783f66
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IXP4xx: Extend PCI MMIO indirect address space to 1 GB.
IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using the non-prefetch registers). Previously the available space depended on the CPU variant, since one of the IXP43x platforms needed more than the usual 128 MB. 1 GB should be enough for everyone, and if not, we can trivially increase it. Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Showing 4 changed files with 29 additions and 29 deletions Side-by-side Diff
arch/arm/mach-ixp4xx/Kconfig
| ... | ... | @@ -179,21 +179,21 @@ |
| 179 | 179 | help |
| 180 | 180 | IXP4xx provides two methods of accessing PCI memory space: |
| 181 | 181 | |
| 182 | - 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
| 182 | + 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). | |
| 183 | 183 | To access PCI via this space, we simply ioremap() the BAR |
| 184 | 184 | into the kernel and we can use the standard read[bwl]/write[bwl] |
| 185 | 185 | macros. This is the preferred method due to speed but it |
| 186 | - limits the system to just 64MB of PCI memory. This can be | |
| 186 | + limits the system to just 64MB of PCI memory. This can be | |
| 187 | 187 | problematic if using video cards and other memory-heavy devices. |
| 188 | - | |
| 189 | - 2) If > 64MB of memory space is required, the IXP4xx can be | |
| 190 | - configured to use indirect registers to access PCI This allows | |
| 191 | - for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. | |
| 192 | - The disadvantage of this is that every PCI access requires | |
| 193 | - three local register accesses plus a spinlock, but in some | |
| 194 | - cases the performance hit is acceptable. In addition, you cannot | |
| 195 | - mmap() PCI devices in this case due to the indirect nature | |
| 196 | - of the PCI window. | |
| 188 | + | |
| 189 | + 2) If > 64MB of memory space is required, the IXP4xx can be | |
| 190 | + configured to use indirect registers to access the whole PCI | |
| 191 | + memory space. This currently allows for up to 1 GB (0x10000000 | |
| 192 | + to 0x4FFFFFFF) of memory on the bus. The disadvantage of this | |
| 193 | + is that every PCI access requires three local register accesses | |
| 194 | + plus a spinlock, but in some cases the performance hit is | |
| 195 | + acceptable. In addition, you cannot mmap() PCI devices in this | |
| 196 | + case due to the indirect nature of the PCI window. | |
| 197 | 197 | |
| 198 | 198 | By default, the direct method is used. Choose this option if you |
| 199 | 199 | need to use the indirect method instead. If you don't know |
arch/arm/mach-ixp4xx/common-pci.c
| ... | ... | @@ -481,11 +481,7 @@ |
| 481 | 481 | |
| 482 | 482 | res[1].name = "PCI Memory Space"; |
| 483 | 483 | res[1].start = PCIBIOS_MIN_MEM; |
| 484 | -#ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
| 485 | - res[1].end = 0x4bffffff; | |
| 486 | -#else | |
| 487 | - res[1].end = 0x4fffffff; | |
| 488 | -#endif | |
| 484 | + res[1].end = PCIBIOS_MAX_MEM; | |
| 489 | 485 | res[1].flags = IORESOURCE_MEM; |
| 490 | 486 | |
| 491 | 487 | request_resource(&ioport_resource, &res[0]); |
arch/arm/mach-ixp4xx/include/mach/hardware.h
| ... | ... | @@ -18,7 +18,13 @@ |
| 18 | 18 | #define __ASM_ARCH_HARDWARE_H__ |
| 19 | 19 | |
| 20 | 20 | #define PCIBIOS_MIN_IO 0x00001000 |
| 21 | -#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) | |
| 21 | +#ifdef CONFIG_IXP4XX_INDIRECT_PCI | |
| 22 | +#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */ | |
| 23 | +#define PCIBIOS_MAX_MEM 0x4FFFFFFF | |
| 24 | +#else | |
| 25 | +#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */ | |
| 26 | +#define PCIBIOS_MAX_MEM 0x4BFFFFFF | |
| 27 | +#endif | |
| 22 | 28 | |
| 23 | 29 | /* |
| 24 | 30 | * We override the standard dma-mask routines for bouncing. |
arch/arm/mach-ixp4xx/include/mach/io.h
| ... | ... | @@ -26,22 +26,20 @@ |
| 26 | 26 | /* |
| 27 | 27 | * IXP4xx provides two methods of accessing PCI memory space: |
| 28 | 28 | * |
| 29 | - * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
| 29 | + * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). | |
| 30 | 30 | * To access PCI via this space, we simply ioremap() the BAR |
| 31 | 31 | * into the kernel and we can use the standard read[bwl]/write[bwl] |
| 32 | 32 | * macros. This is the preffered method due to speed but it |
| 33 | - * limits the system to just 64MB of PCI memory. This can be | |
| 34 | - * problamatic if using video cards and other memory-heavy | |
| 35 | - * targets. | |
| 33 | + * limits the system to just 64MB of PCI memory. This can be | |
| 34 | + * problematic if using video cards and other memory-heavy targets. | |
| 36 | 35 | * |
| 37 | - * 2) If > 64MB of memory space is required, the IXP4xx can be configured | |
| 38 | - * to use indirect registers to access PCI (as we do below for I/O | |
| 39 | - * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | |
| 40 | - * of memory on the bus. The disadvantage of this is that every | |
| 41 | - * PCI access requires three local register accesses plus a spinlock, | |
| 42 | - * but in some cases the performance hit is acceptable. In addition, | |
| 43 | - * you cannot mmap() PCI devices in this case. | |
| 44 | - * | |
| 36 | + * 2) If > 64MB of memory space is required, the IXP4xx can use indirect | |
| 37 | + * registers to access the whole 4 GB of PCI memory space (as we do below | |
| 38 | + * for I/O transactions). This allows currently for up to 1 GB (0x10000000 | |
| 39 | + * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that | |
| 40 | + * every PCI access requires three local register accesses plus a spinlock, | |
| 41 | + * but in some cases the performance hit is acceptable. In addition, you | |
| 42 | + * cannot mmap() PCI devices in this case. | |
| 45 | 43 | */ |
| 46 | 44 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 47 | 45 |