Eric Lee / linux-smarc-t335x-v3.2

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Commit ee89cbc2d48150c7c0e9f2aaac00afde99af098c

Authored by Stephane Eranian
Committed by Ingo Molnar
1 parent cd8a38d33e
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

perf_events: Add Intel Sandy Bridge offcore_response low-level support 

This patch adds Intel Sandy Bridge offcore_response support by
providing the low-level constraint table for those events.

On Sandy Bridge, there are two offcore_response events. Each uses
its own dedictated extra register. But those registers are NOT shared
between sibling CPUs when HT is on unlike Nehalem/Westmere. They are
always private to each CPU. But they still need to be controlled within
an event group. All events within an event group must use the same
value for the extra MSR. That's not controlled by the second patch in
this series.

Furthermore on Sandy Bridge, the offcore_response events have NO
counter constraints contrary to what the official documentation
indicates, so drop the events from the contraint table.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20110606145712.GA7304@quad
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 2 changed files with 11 additions and 3 deletions Side-by-side Diff

arch/x86/kernel/cpu/perf_event.c
Diff comments   View file @ ee89cbc
... ... @@ -327,6 +327,7 @@
327 327 * Extra registers for events
328 328 */
329 329 struct extra_reg *extra_regs;
  330 + bool regs_no_ht_sharing;
330 331 };
331 332  
332 333 static struct x86_pmu x86_pmu __read_mostly;
arch/x86/kernel/cpu/perf_event_intel.c
Diff comments   View file @ ee89cbc
... ... @@ -100,8 +100,6 @@
100 100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 101 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
102 102 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
103   - INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */
104   - INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */
105 103 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
106 104 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
107 105 EVENT_CONSTRAINT_END
... ... @@ -122,6 +120,12 @@
122 120 EVENT_CONSTRAINT_END
123 121 };
124 122  
  123 +static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
  124 + INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
  125 + INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
  126 + EVENT_EXTRA_END
  127 +};
  128 +
125 129 static u64 intel_pmu_event_map(int hw_event)
126 130 {
127 131 return intel_perfmon_event_map[hw_event];
... ... @@ -1260,7 +1264,7 @@
1260 1264 */
1261 1265 intel_pmu_lbr_reset();
1262 1266  
1263   - if (!cpuc->shared_regs)
  1267 + if (!cpuc->shared_regs || x86_pmu.regs_no_ht_sharing)
1264 1268 return;
1265 1269  
1266 1270 for_each_cpu(i, topology_thread_cpumask(cpu)) {
... ... @@ -1502,6 +1506,9 @@
1502 1506  
1503 1507 x86_pmu.event_constraints = intel_snb_event_constraints;
1504 1508 x86_pmu.pebs_constraints = intel_snb_pebs_events;
  1509 + x86_pmu.extra_regs = intel_snb_extra_regs;
  1510 + /* all extra regs are per-cpu when HT is on */
  1511 + x86_pmu.regs_no_ht_sharing = true;
1505 1512  
1506 1513 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1507 1514 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;