Eric Lee / linux-smarc-t335x-v3.2

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Commit f40aac940aa83645ec2218ccce90cc1c6881b74c

Authored by Russell King
Committed by Russell King
2 parents 7063c88c72 3c82e229f0
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

Merge branch 'omap_fixes_31' of git://git.pwsan.com/linux-2.6

Showing 31 changed files Side-by-side Diff

arch/arm/mach-omap2/board-2430sdp.c
Diff comments   View file @ f40aac9
... ... @@ -141,7 +141,7 @@
141 141  
142 142 static void __init omap_2430sdp_init_irq(void)
143 143 {
144   - omap2_init_common_hw(NULL);
  144 + omap2_init_common_hw(NULL, NULL);
145 145 omap_init_irq();
146 146 omap_gpio_init();
147 147 }
arch/arm/mach-omap2/board-3430sdp.c
Diff comments   View file @ f40aac9
... ... @@ -169,7 +169,7 @@
169 169  
170 170 static void __init omap_3430sdp_init_irq(void)
171 171 {
172   - omap2_init_common_hw(hyb18m512160af6_sdrc_params);
  172 + omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
173 173 omap_init_irq();
174 174 omap_gpio_init();
175 175 }
arch/arm/mach-omap2/board-4430sdp.c
Diff comments   View file @ f40aac9
... ... @@ -59,7 +59,7 @@
59 59  
60 60 static void __init omap_4430sdp_init_irq(void)
61 61 {
62   - omap2_init_common_hw(NULL);
  62 + omap2_init_common_hw(NULL, NULL);
63 63 #ifdef CONFIG_OMAP_32K_TIMER
64 64 omap2_gp_clockevent_set_gptimer(1);
65 65 #endif
arch/arm/mach-omap2/board-apollon.c
Diff comments   View file @ f40aac9
... ... @@ -250,7 +250,7 @@
250 250  
251 251 static void __init omap_apollon_init_irq(void)
252 252 {
253   - omap2_init_common_hw(NULL);
  253 + omap2_init_common_hw(NULL, NULL);
254 254 omap_init_irq();
255 255 omap_gpio_init();
256 256 apollon_init_smc91x();
arch/arm/mach-omap2/board-generic.c
Diff comments   View file @ f40aac9
... ... @@ -33,7 +33,7 @@
33 33  
34 34 static void __init omap_generic_init_irq(void)
35 35 {
36   - omap2_init_common_hw(NULL);
  36 + omap2_init_common_hw(NULL, NULL);
37 37 omap_init_irq();
38 38 }
39 39  
arch/arm/mach-omap2/board-h4.c
Diff comments   View file @ f40aac9
... ... @@ -270,7 +270,7 @@
270 270  
271 271 static void __init omap_h4_init_irq(void)
272 272 {
273   - omap2_init_common_hw(NULL);
  273 + omap2_init_common_hw(NULL, NULL);
274 274 omap_init_irq();
275 275 omap_gpio_init();
276 276 h4_init_flash();
arch/arm/mach-omap2/board-ldp.c
Diff comments   View file @ f40aac9
... ... @@ -270,7 +270,7 @@
270 270  
271 271 static void __init omap_ldp_init_irq(void)
272 272 {
273   - omap2_init_common_hw(NULL);
  273 + omap2_init_common_hw(NULL, NULL);
274 274 omap_init_irq();
275 275 omap_gpio_init();
276 276 ldp_init_smsc911x();
arch/arm/mach-omap2/board-omap3beagle.c
Diff comments   View file @ f40aac9
... ... @@ -282,7 +282,8 @@
282 282  
283 283 static void __init omap3_beagle_init_irq(void)
284 284 {
285   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  285 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  286 + mt46h32m32lf6_sdrc_params);
286 287 omap_init_irq();
287 288 #ifdef CONFIG_OMAP_32K_TIMER
288 289 omap2_gp_clockevent_set_gptimer(12);
... ... @@ -408,6 +409,10 @@
408 409  
409 410 usb_musb_init();
410 411 omap3beagle_flash_init();
  412 +
  413 + /* Ensure SDRC pins are mux'd for self-refresh */
  414 + omap_cfg_reg(H16_34XX_SDRC_CKE0);
  415 + omap_cfg_reg(H17_34XX_SDRC_CKE1);
411 416 }
412 417  
413 418 static void __init omap3_beagle_map_io(void)
arch/arm/mach-omap2/board-omap3evm.c
Diff comments   View file @ f40aac9
... ... @@ -280,7 +280,7 @@
280 280  
281 281 static void __init omap3_evm_init_irq(void)
282 282 {
283   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  283 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
284 284 omap_init_irq();
285 285 omap_gpio_init();
286 286 omap3evm_init_smc911x();
arch/arm/mach-omap2/board-omap3pandora.c
Diff comments   View file @ f40aac9
... ... @@ -40,6 +40,7 @@
40 40 #include <mach/mcspi.h>
41 41 #include <mach/usb.h>
42 42 #include <mach/keypad.h>
  43 +#include <mach/mux.h>
43 44  
44 45 #include "sdram-micron-mt46h32m32lf-6.h"
45 46 #include "mmc-twl4030.h"
... ... @@ -310,7 +311,8 @@
310 311  
311 312 static void __init omap3pandora_init_irq(void)
312 313 {
313   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  314 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  315 + mt46h32m32lf6_sdrc_params);
314 316 omap_init_irq();
315 317 omap_gpio_init();
316 318 }
... ... @@ -397,6 +399,10 @@
397 399 omap3pandora_ads7846_init();
398 400 pandora_keys_gpio_init();
399 401 usb_musb_init();
  402 +
  403 + /* Ensure SDRC pins are mux'd for self-refresh */
  404 + omap_cfg_reg(H16_34XX_SDRC_CKE0);
  405 + omap_cfg_reg(H17_34XX_SDRC_CKE1);
400 406 }
401 407  
402 408 static void __init omap3pandora_map_io(void)
arch/arm/mach-omap2/board-overo.c
Diff comments   View file @ f40aac9
... ... @@ -44,6 +44,7 @@
44 44 #include <mach/gpmc.h>
45 45 #include <mach/hardware.h>
46 46 #include <mach/nand.h>
  47 +#include <mach/mux.h>
47 48 #include <mach/usb.h>
48 49  
49 50 #include "sdram-micron-mt46h32m32lf-6.h"
... ... @@ -360,7 +361,8 @@
360 361  
361 362 static void __init overo_init_irq(void)
362 363 {
363   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  364 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  365 + mt46h32m32lf6_sdrc_params);
364 366 omap_init_irq();
365 367 omap_gpio_init();
366 368 }
... ... @@ -394,6 +396,10 @@
394 396 usb_musb_init();
395 397 overo_ads7846_init();
396 398 overo_init_smsc911x();
  399 +
  400 + /* Ensure SDRC pins are mux'd for self-refresh */
  401 + omap_cfg_reg(H16_34XX_SDRC_CKE0);
  402 + omap_cfg_reg(H17_34XX_SDRC_CKE1);
397 403  
398 404 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
399 405 "OVERO_GPIO_W2W_NRESET") == 0) &&
arch/arm/mach-omap2/board-rx51.c
Diff comments   View file @ f40aac9
... ... @@ -61,7 +61,7 @@
61 61  
62 62 static void __init rx51_init_irq(void)
63 63 {
64   - omap2_init_common_hw(NULL);
  64 + omap2_init_common_hw(NULL, NULL);
65 65 omap_init_irq();
66 66 omap_gpio_init();
67 67 }
... ... @@ -75,6 +75,10 @@
75 75 omap_serial_init();
76 76 usb_musb_init();
77 77 rx51_peripherals_init();
  78 +
  79 + /* Ensure SDRC pins are mux'd for self-refresh */
  80 + omap_cfg_reg(H16_34XX_SDRC_CKE0);
  81 + omap_cfg_reg(H17_34XX_SDRC_CKE1);
78 82 }
79 83  
80 84 static void __init rx51_map_io(void)
arch/arm/mach-omap2/board-zoom2.c
Diff comments   View file @ f40aac9
... ... @@ -25,7 +25,7 @@
25 25  
26 26 static void __init omap_zoom2_init_irq(void)
27 27 {
28   - omap2_init_common_hw(NULL);
  28 + omap2_init_common_hw(NULL, NULL);
29 29 omap_init_irq();
30 30 omap_gpio_init();
31 31 }
arch/arm/mach-omap2/clock.c
Diff comments   View file @ f40aac9
... ... @@ -27,6 +27,7 @@
27 27 #include <mach/clock.h>
28 28 #include <mach/clockdomain.h>
29 29 #include <mach/cpu.h>
  30 +#include <mach/prcm.h>
30 31 #include <asm/div64.h>
31 32  
32 33 #include <mach/sdrc.h>
... ... @@ -38,8 +39,6 @@
38 39 #include "cm-regbits-24xx.h"
39 40 #include "cm-regbits-34xx.h"
40 41  
41   -#define MAX_CLOCK_ENABLE_WAIT 100000
42   -
43 42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
44 43 #define DPLL_MIN_MULTIPLIER 1
45 44 #define DPLL_MIN_DIVIDER 1
46 45  
47 46  
48 47  
49 48  
50 49  
51 50  
52 51  
53 52  
54 53  
55 54  
56 55  
57 56  
58 57  
59 58  
60 59  
61 60  
... ... @@ -274,83 +273,97 @@
274 273 }
275 274  
276 275 /**
277   - * omap2_wait_clock_ready - wait for clock to enable
278   - * @reg: physical address of clock IDLEST register
279   - * @mask: value to mask against to determine if the clock is active
280   - * @name: name of the clock (for printk)
  276 + * omap2_clk_dflt_find_companion - find companion clock to @clk
  277 + * @clk: struct clk * to find the companion clock of
  278 + * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
  279 + * @other_bit: u8 ** to return the companion clock bit shift in
281 280 *
282   - * Returns 1 if the clock enabled in time, or 0 if it failed to enable
283   - * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
  281 + * Note: We don't need special code here for INVERT_ENABLE for the
  282 + * time being since INVERT_ENABLE only applies to clocks enabled by
  283 + * CM_CLKEN_PLL
  284 + *
  285 + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
  286 + * just a matter of XORing the bits.
  287 + *
  288 + * Some clocks don't have companion clocks. For example, modules with
  289 + * only an interface clock (such as MAILBOXES) don't have a companion
  290 + * clock. Right now, this code relies on the hardware exporting a bit
  291 + * in the correct companion register that indicates that the
  292 + * nonexistent 'companion clock' is active. Future patches will
  293 + * associate this type of code with per-module data structures to
  294 + * avoid this issue, and remove the casts. No return value.
284 295 */
285   -int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
  296 +void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
  297 + u8 *other_bit)
286 298 {
287   - int i = 0;
288   - int ena = 0;
  299 + u32 r;
289 300  
290 301 /*
291   - * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
292   - * 34xx reverses this, just to keep us on our toes
  302 + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
  303 + * it's just a matter of XORing the bits.
293 304 */
294   - if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
295   - ena = mask;
296   - else if (cpu_mask & RATE_IN_343X)
297   - ena = 0;
  305 + r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
298 306  
299   - /* Wait for lock */
300   - while (((__raw_readl(reg) & mask) != ena) &&
301   - (i++ < MAX_CLOCK_ENABLE_WAIT)) {
302   - udelay(1);
303   - }
  307 + *other_reg = (__force void __iomem *)r;
  308 + *other_bit = clk->enable_bit;
  309 +}
304 310  
305   - if (i <= MAX_CLOCK_ENABLE_WAIT)
306   - pr_debug("Clock %s stable after %d loops\n", name, i);
307   - else
308   - printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
309   - name, MAX_CLOCK_ENABLE_WAIT);
  311 +/**
  312 + * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
  313 + * @clk: struct clk * to find IDLEST info for
  314 + * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
  315 + * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
  316 + *
  317 + * Return the CM_IDLEST register address and bit shift corresponding
  318 + * to the module that "owns" this clock. This default code assumes
  319 + * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
  320 + * the IDLEST register address ID corresponds to the CM_*CLKEN
  321 + * register address ID (e.g., that CM_FCLKEN2 corresponds to
  322 + * CM_IDLEST2). This is not true for all modules. No return value.
  323 + */
  324 +void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
  325 + u8 *idlest_bit)
  326 +{
  327 + u32 r;
310 328  
  329 + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  330 + *idlest_reg = (__force void __iomem *)r;
  331 + *idlest_bit = clk->enable_bit;
  332 +}
311 333  
312   - return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
313   -};
314   -
315   -
316   -/*
317   - * Note: We don't need special code here for INVERT_ENABLE
318   - * for the time being since INVERT_ENABLE only applies to clocks enabled by
319   - * CM_CLKEN_PLL
  334 +/**
  335 + * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
  336 + * @clk: struct clk * belonging to the module
  337 + *
  338 + * If the necessary clocks for the OMAP hardware IP block that
  339 + * corresponds to clock @clk are enabled, then wait for the module to
  340 + * indicate readiness (i.e., to leave IDLE). This code does not
  341 + * belong in the clock code and will be moved in the medium term to
  342 + * module-dependent code. No return value.
320 343 */
321   -static void omap2_clk_wait_ready(struct clk *clk)
  344 +static void omap2_module_wait_ready(struct clk *clk)
322 345 {
323   - void __iomem *reg, *other_reg, *st_reg;
324   - u32 bit;
  346 + void __iomem *companion_reg, *idlest_reg;
  347 + u8 other_bit, idlest_bit;
325 348  
326   - /*
327   - * REVISIT: This code is pretty ugly. It would be nice to generalize
328   - * it and pull it into struct clk itself somehow.
329   - */
330   - reg = clk->enable_reg;
  349 + /* Not all modules have multiple clocks that their IDLEST depends on */
  350 + if (clk->ops->find_companion) {
  351 + clk->ops->find_companion(clk, &companion_reg, &other_bit);
  352 + if (!(__raw_readl(companion_reg) & (1 << other_bit)))
  353 + return;
  354 + }
331 355  
332   - /*
333   - * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
334   - * it's just a matter of XORing the bits.
335   - */
336   - other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
  356 + clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
337 357  
338   - /* Check if both functional and interface clocks
339   - * are running. */
340   - bit = 1 << clk->enable_bit;
341   - if (!(__raw_readl(other_reg) & bit))
342   - return;
343   - st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
344   -
345   - omap2_wait_clock_ready(st_reg, bit, clk->name);
  358 + omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
346 359 }
347 360  
348   -static int omap2_dflt_clk_enable(struct clk *clk)
  361 +int omap2_dflt_clk_enable(struct clk *clk)
349 362 {
350 363 u32 v;
351 364  
352 365 if (unlikely(clk->enable_reg == NULL)) {
353   - printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
  366 + pr_err("clock.c: Enable for %s without enable code\n",
354 367 clk->name);
355 368 return 0; /* REVISIT: -EINVAL */
356 369 }
357 370  
358 371  
... ... @@ -363,27 +376,14 @@
363 376 __raw_writel(v, clk->enable_reg);
364 377 v = __raw_readl(clk->enable_reg); /* OCP barrier */
365 378  
  379 + if (clk->ops->find_idlest)
  380 + omap2_module_wait_ready(clk);
  381 +
366 382 return 0;
367 383 }
368 384  
369   -static int omap2_dflt_clk_enable_wait(struct clk *clk)
  385 +void omap2_dflt_clk_disable(struct clk *clk)
370 386 {
371   - int ret;
372   -
373   - if (!clk->enable_reg) {
374   - printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
375   - clk->name);
376   - return 0; /* REVISIT: -EINVAL */
377   - }
378   -
379   - ret = omap2_dflt_clk_enable(clk);
380   - if (ret == 0)
381   - omap2_clk_wait_ready(clk);
382   - return ret;
383   -}
384   -
385   -static void omap2_dflt_clk_disable(struct clk *clk)
386   -{
387 387 u32 v;
388 388  
389 389 if (!clk->enable_reg) {
390 390  
... ... @@ -406,8 +406,10 @@
406 406 }
407 407  
408 408 const struct clkops clkops_omap2_dflt_wait = {
409   - .enable = omap2_dflt_clk_enable_wait,
  409 + .enable = omap2_dflt_clk_enable,
410 410 .disable = omap2_dflt_clk_disable,
  411 + .find_companion = omap2_clk_dflt_find_companion,
  412 + .find_idlest = omap2_clk_dflt_find_idlest,
411 413 };
412 414  
413 415 const struct clkops clkops_omap2_dflt = {
arch/arm/mach-omap2/clock.h
Diff comments   View file @ f40aac9
... ... @@ -65,6 +65,12 @@
65 65 u32 omap2_get_dpll_rate(struct clk *clk);
66 66 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
67 67 void omap2_clk_prepare_for_reboot(void);
  68 +int omap2_dflt_clk_enable(struct clk *clk);
  69 +void omap2_dflt_clk_disable(struct clk *clk);
  70 +void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
  71 + u8 *other_bit);
  72 +void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
  73 + u8 *idlest_bit);
68 74  
69 75 extern const struct clkops clkops_omap2_dflt_wait;
70 76 extern const struct clkops clkops_omap2_dflt;
arch/arm/mach-omap2/clock24xx.c
Diff comments   View file @ f40aac9
... ... @@ -30,6 +30,7 @@
30 30  
31 31 #include <mach/clock.h>
32 32 #include <mach/sram.h>
  33 +#include <mach/prcm.h>
33 34 #include <asm/div64.h>
34 35 #include <asm/clkdev.h>
35 36  
... ... @@ -43,6 +44,18 @@
43 44 static const struct clkops clkops_oscck;
44 45 static const struct clkops clkops_fixed;
45 46  
  47 +static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
  48 + void __iomem **idlest_reg,
  49 + u8 *idlest_bit);
  50 +
  51 +/* 2430 I2CHS has non-standard IDLEST register */
  52 +static const struct clkops clkops_omap2430_i2chs_wait = {
  53 + .enable = omap2_dflt_clk_enable,
  54 + .disable = omap2_dflt_clk_disable,
  55 + .find_idlest = omap2430_clk_i2chs_find_idlest,
  56 + .find_companion = omap2_clk_dflt_find_companion,
  57 +};
  58 +
46 59 #include "clock24xx.h"
47 60  
48 61 struct omap_clk {
... ... @@ -240,6 +253,26 @@
240 253 *-------------------------------------------------------------------------*/
241 254  
242 255 /**
  256 + * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
  257 + * @clk: struct clk * being enabled
  258 + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  259 + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  260 + *
  261 + * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
  262 + * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
  263 + * passes back the correct CM_IDLEST register address for I2CHS
  264 + * modules. No return value.
  265 + */
  266 +static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
  267 + void __iomem **idlest_reg,
  268 + u8 *idlest_bit)
  269 +{
  270 + *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
  271 + *idlest_bit = clk->enable_bit;
  272 +}
  273 +
  274 +
  275 +/**
243 276 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
244 277 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
245 278 *
... ... @@ -325,8 +358,8 @@
325 358 else if (clk == &apll54_ck)
326 359 cval = OMAP24XX_ST_54M_APLL;
327 360  
328   - omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
329   - clk->name);
  361 + omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
  362 + clk->name);
330 363  
331 364 /*
332 365 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
arch/arm/mach-omap2/clock24xx.h
Diff comments   View file @ f40aac9
... ... @@ -2337,7 +2337,7 @@
2337 2337  
2338 2338 static struct clk i2chs2_fck = {
2339 2339 .name = "i2c_fck",
2340   - .ops = &clkops_omap2_dflt_wait,
  2340 + .ops = &clkops_omap2430_i2chs_wait,
2341 2341 .id = 2,
2342 2342 .parent = &func_96m_ck,
2343 2343 .clkdm_name = "core_l4_clkdm",
... ... @@ -2370,7 +2370,7 @@
2370 2370  
2371 2371 static struct clk i2chs1_fck = {
2372 2372 .name = "i2c_fck",
2373   - .ops = &clkops_omap2_dflt_wait,
  2373 + .ops = &clkops_omap2430_i2chs_wait,
2374 2374 .id = 1,
2375 2375 .parent = &func_96m_ck,
2376 2376 .clkdm_name = "core_l4_clkdm",
arch/arm/mach-omap2/clock34xx.c
Diff comments   View file @ f40aac9
... ... @@ -2,7 +2,7 @@
2 2 * OMAP3-specific clock framework functions
3 3 *
4 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5   - * Copyright (C) 2007-2008 Nokia Corporation
  5 + * Copyright (C) 2007-2009 Nokia Corporation
6 6 *
7 7 * Written by Paul Walmsley
8 8 * Testing and integration fixes by Jouni Hรถgander
... ... @@ -41,6 +41,37 @@
41 41  
42 42 static const struct clkops clkops_noncore_dpll_ops;
43 43  
  44 +static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
  45 + void __iomem **idlest_reg,
  46 + u8 *idlest_bit);
  47 +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
  48 + void __iomem **idlest_reg,
  49 + u8 *idlest_bit);
  50 +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
  51 + void __iomem **idlest_reg,
  52 + u8 *idlest_bit);
  53 +
  54 +static const struct clkops clkops_omap3430es2_ssi_wait = {
  55 + .enable = omap2_dflt_clk_enable,
  56 + .disable = omap2_dflt_clk_disable,
  57 + .find_idlest = omap3430es2_clk_ssi_find_idlest,
  58 + .find_companion = omap2_clk_dflt_find_companion,
  59 +};
  60 +
  61 +static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
  62 + .enable = omap2_dflt_clk_enable,
  63 + .disable = omap2_dflt_clk_disable,
  64 + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
  65 + .find_companion = omap2_clk_dflt_find_companion,
  66 +};
  67 +
  68 +static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
  69 + .enable = omap2_dflt_clk_enable,
  70 + .disable = omap2_dflt_clk_disable,
  71 + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
  72 + .find_companion = omap2_clk_dflt_find_companion,
  73 +};
  74 +
44 75 #include "clock34xx.h"
45 76  
46 77 struct omap_clk {
47 78  
... ... @@ -157,10 +188,13 @@
157 188 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
158 189 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
159 190 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
160   - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
161   - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
  191 + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
  192 + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
  193 + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
  194 + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
162 195 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
163   - CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
  196 + CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
  197 + CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
164 198 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
165 199 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
166 200 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
167 201  
168 202  
... ... @@ -193,18 +227,21 @@
193 227 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
194 228 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
195 229 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
196   - CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
  230 + CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
  231 + CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
197 232 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
198 233 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
199 234 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
200 235 CLK("omap_rng", "ick", &rng_ick, CK_343X),
201 236 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
202 237 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
203   - CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
  238 + CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
  239 + CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
204 240 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
205 241 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
206 242 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
207   - CLK("omapfb", "ick", &dss_ick, CK_343X),
  243 + CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
  244 + CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
208 245 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
209 246 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
210 247 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
... ... @@ -301,6 +338,73 @@
301 338 #define SDRC_MPURATE_LOOPS 96
302 339  
303 340 /**
  341 + * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  342 + * @clk: struct clk * being enabled
  343 + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  344 + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  345 + *
  346 + * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
  347 + * from the CM_{I,F}CLKEN bit. Pass back the correct info via
  348 + * @idlest_reg and @idlest_bit. No return value.
  349 + */
  350 +static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
  351 + void __iomem **idlest_reg,
  352 + u8 *idlest_bit)
  353 +{
  354 + u32 r;
  355 +
  356 + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  357 + *idlest_reg = (__force void __iomem *)r;
  358 + *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
  359 +}
  360 +
  361 +/**
  362 + * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  363 + * @clk: struct clk * being enabled
  364 + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  365 + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  366 + *
  367 + * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
  368 + * target IDLEST bits. For our purposes, we are concerned with the
  369 + * target IDLEST bits, which exist at a different bit position than
  370 + * the *CLKEN bit position for these modules (DSS and USBHOST) (The
  371 + * default find_idlest code assumes that they are at the same
  372 + * position.) No return value.
  373 + */
  374 +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
  375 + void __iomem **idlest_reg,
  376 + u8 *idlest_bit)
  377 +{
  378 + u32 r;
  379 +
  380 + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  381 + *idlest_reg = (__force void __iomem *)r;
  382 + /* USBHOST_IDLE has same shift */
  383 + *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
  384 +}
  385 +
  386 +/**
  387 + * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  388 + * @clk: struct clk * being enabled
  389 + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  390 + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  391 + *
  392 + * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
  393 + * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
  394 + * @idlest_reg and @idlest_bit. No return value.
  395 + */
  396 +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
  397 + void __iomem **idlest_reg,
  398 + u8 *idlest_bit)
  399 +{
  400 + u32 r;
  401 +
  402 + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  403 + *idlest_reg = (__force void __iomem *)r;
  404 + *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
  405 +}
  406 +
  407 +/**
304 408 * omap3_dpll_recalc - recalculate DPLL rate
305 409 * @clk: DPLL struct clk
306 410 *
... ... @@ -725,7 +829,9 @@
725 829 u32 unlock_dll = 0;
726 830 u32 c;
727 831 unsigned long validrate, sdrcrate, mpurate;
728   - struct omap_sdrc_params *sp;
  832 + struct omap_sdrc_params *sdrc_cs0;
  833 + struct omap_sdrc_params *sdrc_cs1;
  834 + int ret;
729 835  
730 836 if (!clk || !rate)
731 837 return -EINVAL;
... ... @@ -743,8 +849,8 @@
743 849 else
744 850 sdrcrate >>= ((clk->rate / rate) >> 1);
745 851  
746   - sp = omap2_sdrc_get_params(sdrcrate);
747   - if (!sp)
  852 + ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
  853 + if (ret)
748 854 return -EINVAL;
749 855  
750 856 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
751 857  
... ... @@ -765,12 +871,29 @@
765 871  
766 872 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
767 873 validrate);
768   - pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
769   - sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
  874 + pr_debug("clock: SDRC CS0 timing params used:"
  875 + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  876 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  877 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
  878 + if (sdrc_cs1)
  879 + pr_debug("clock: SDRC CS1 timing params used: "
  880 + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  881 + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  882 + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
770 883  
771   - omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
772   - sp->actim_ctrlb, new_div, unlock_dll, c,
773   - sp->mr, rate > clk->rate);
  884 + if (sdrc_cs1)
  885 + omap3_configure_core_dpll(
  886 + new_div, unlock_dll, c, rate > clk->rate,
  887 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  888 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  889 + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  890 + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
  891 + else
  892 + omap3_configure_core_dpll(
  893 + new_div, unlock_dll, c, rate > clk->rate,
  894 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  895 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  896 + 0, 0, 0, 0);
774 897  
775 898 return 0;
776 899 }
arch/arm/mach-omap2/clock34xx.h
Diff comments   View file @ f40aac9
... ... @@ -1568,7 +1568,7 @@
1568 1568 { .parent = NULL }
1569 1569 };
1570 1570  
1571   -static struct clk ssi_ssr_fck = {
  1571 +static struct clk ssi_ssr_fck_3430es1 = {
1572 1572 .name = "ssi_ssr_fck",
1573 1573 .ops = &clkops_omap2_dflt,
1574 1574 .init = &omap2_init_clksel_parent,
1575 1575  
1576 1576  
1577 1577  
... ... @@ -1581,16 +1581,37 @@
1581 1581 .recalc = &omap2_clksel_recalc,
1582 1582 };
1583 1583  
1584   -static struct clk ssi_sst_fck = {
  1584 +static struct clk ssi_ssr_fck_3430es2 = {
  1585 + .name = "ssi_ssr_fck",
  1586 + .ops = &clkops_omap3430es2_ssi_wait,
  1587 + .init = &omap2_init_clksel_parent,
  1588 + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1589 + .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1590 + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1591 + .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1592 + .clksel = ssi_ssr_clksel,
  1593 + .clkdm_name = "core_l4_clkdm",
  1594 + .recalc = &omap2_clksel_recalc,
  1595 +};
  1596 +
  1597 +static struct clk ssi_sst_fck_3430es1 = {
1585 1598 .name = "ssi_sst_fck",
1586 1599 .ops = &clkops_null,
1587   - .parent = &ssi_ssr_fck,
  1600 + .parent = &ssi_ssr_fck_3430es1,
1588 1601 .fixed_div = 2,
1589 1602 .recalc = &omap2_fixed_divisor_recalc,
1590 1603 };
1591 1604  
  1605 +static struct clk ssi_sst_fck_3430es2 = {
  1606 + .name = "ssi_sst_fck",
  1607 + .ops = &clkops_null,
  1608 + .parent = &ssi_ssr_fck_3430es2,
  1609 + .fixed_div = 2,
  1610 + .recalc = &omap2_fixed_divisor_recalc,
  1611 +};
1592 1612  
1593 1613  
  1614 +
1594 1615 /* CORE_L3_ICK based clocks */
1595 1616  
1596 1617 /*
1597 1618  
... ... @@ -1606,9 +1627,9 @@
1606 1627 .recalc = &followparent_recalc,
1607 1628 };
1608 1629  
1609   -static struct clk hsotgusb_ick = {
  1630 +static struct clk hsotgusb_ick_3430es1 = {
1610 1631 .name = "hsotgusb_ick",
1611   - .ops = &clkops_omap2_dflt_wait,
  1632 + .ops = &clkops_omap2_dflt,
1612 1633 .parent = &core_l3_ick,
1613 1634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614 1635 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
... ... @@ -1616,6 +1637,16 @@
1616 1637 .recalc = &followparent_recalc,
1617 1638 };
1618 1639  
  1640 +static struct clk hsotgusb_ick_3430es2 = {
  1641 + .name = "hsotgusb_ick",
  1642 + .ops = &clkops_omap3430es2_hsotgusb_wait,
  1643 + .parent = &core_l3_ick,
  1644 + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1645 + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1646 + .clkdm_name = "core_l3_clkdm",
  1647 + .recalc = &followparent_recalc,
  1648 +};
  1649 +
1619 1650 static struct clk sdrc_ick = {
1620 1651 .name = "sdrc_ick",
1621 1652 .ops = &clkops_omap2_dflt_wait,
... ... @@ -1947,7 +1978,7 @@
1947 1978 .recalc = &followparent_recalc,
1948 1979 };
1949 1980  
1950   -static struct clk ssi_ick = {
  1981 +static struct clk ssi_ick_3430es1 = {
1951 1982 .name = "ssi_ick",
1952 1983 .ops = &clkops_omap2_dflt,
1953 1984 .parent = &ssi_l4_ick,
... ... @@ -1957,6 +1988,16 @@
1957 1988 .recalc = &followparent_recalc,
1958 1989 };
1959 1990  
  1991 +static struct clk ssi_ick_3430es2 = {
  1992 + .name = "ssi_ick",
  1993 + .ops = &clkops_omap3430es2_ssi_wait,
  1994 + .parent = &ssi_l4_ick,
  1995 + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1996 + .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1997 + .clkdm_name = "core_l4_clkdm",
  1998 + .recalc = &followparent_recalc,
  1999 +};
  2000 +
1960 2001 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1961 2002 * but l4_ick makes more sense to me */
1962 2003  
... ... @@ -2024,7 +2065,7 @@
2024 2065 };
2025 2066  
2026 2067 /* DSS */
2027   -static struct clk dss1_alwon_fck = {
  2068 +static struct clk dss1_alwon_fck_3430es1 = {
2028 2069 .name = "dss1_alwon_fck",
2029 2070 .ops = &clkops_omap2_dflt,
2030 2071 .parent = &dpll4_m4x2_ck,
... ... @@ -2034,6 +2075,16 @@
2034 2075 .recalc = &followparent_recalc,
2035 2076 };
2036 2077  
  2078 +static struct clk dss1_alwon_fck_3430es2 = {
  2079 + .name = "dss1_alwon_fck",
  2080 + .ops = &clkops_omap3430es2_dss_usbhost_wait,
  2081 + .parent = &dpll4_m4x2_ck,
  2082 + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  2083 + .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  2084 + .clkdm_name = "dss_clkdm",
  2085 + .recalc = &followparent_recalc,
  2086 +};
  2087 +
2037 2088 static struct clk dss_tv_fck = {
2038 2089 .name = "dss_tv_fck",
2039 2090 .ops = &clkops_omap2_dflt,
... ... @@ -2067,7 +2118,7 @@
2067 2118 .recalc = &followparent_recalc,
2068 2119 };
2069 2120  
2070   -static struct clk dss_ick = {
  2121 +static struct clk dss_ick_3430es1 = {
2071 2122 /* Handles both L3 and L4 clocks */
2072 2123 .name = "dss_ick",
2073 2124 .ops = &clkops_omap2_dflt,
... ... @@ -2079,6 +2130,18 @@
2079 2130 .recalc = &followparent_recalc,
2080 2131 };
2081 2132  
  2133 +static struct clk dss_ick_3430es2 = {
  2134 + /* Handles both L3 and L4 clocks */
  2135 + .name = "dss_ick",
  2136 + .ops = &clkops_omap3430es2_dss_usbhost_wait,
  2137 + .parent = &l4_ick,
  2138 + .init = &omap2_init_clk_clkdm,
  2139 + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  2140 + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  2141 + .clkdm_name = "dss_clkdm",
  2142 + .recalc = &followparent_recalc,
  2143 +};
  2144 +
2082 2145 /* CAM */
2083 2146  
2084 2147 static struct clk cam_mclk = {
... ... @@ -2118,7 +2181,7 @@
2118 2181  
2119 2182 static struct clk usbhost_120m_fck = {
2120 2183 .name = "usbhost_120m_fck",
2121   - .ops = &clkops_omap2_dflt_wait,
  2184 + .ops = &clkops_omap2_dflt,
2122 2185 .parent = &dpll5_m2_ck,
2123 2186 .init = &omap2_init_clk_clkdm,
2124 2187 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
... ... @@ -2129,7 +2192,7 @@
2129 2192  
2130 2193 static struct clk usbhost_48m_fck = {
2131 2194 .name = "usbhost_48m_fck",
2132   - .ops = &clkops_omap2_dflt_wait,
  2195 + .ops = &clkops_omap3430es2_dss_usbhost_wait,
2133 2196 .parent = &omap_48m_fck,
2134 2197 .init = &omap2_init_clk_clkdm,
2135 2198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
... ... @@ -2141,7 +2204,7 @@
2141 2204 static struct clk usbhost_ick = {
2142 2205 /* Handles both L3 and L4 clocks */
2143 2206 .name = "usbhost_ick",
2144   - .ops = &clkops_omap2_dflt_wait,
  2207 + .ops = &clkops_omap3430es2_dss_usbhost_wait,
2145 2208 .parent = &l4_ick,
2146 2209 .init = &omap2_init_clk_clkdm,
2147 2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
arch/arm/mach-omap2/io.c
Diff comments   View file @ f40aac9
... ... @@ -276,14 +276,15 @@
276 276 return v;
277 277 }
278 278  
279   -void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
  279 +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
  280 + struct omap_sdrc_params *sdrc_cs1)
280 281 {
281 282 omap2_mux_init();
282 283 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
283 284 pwrdm_init(powerdomains_omap);
284 285 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
285 286 omap2_clk_init();
286   - omap2_sdrc_init(sp);
  287 + omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
287 288 _omap2_init_reprogram_sdrc();
288 289 #endif
289 290 gpmc_init();
arch/arm/mach-omap2/mux.c
Diff comments   View file @ f40aac9
... ... @@ -486,6 +486,12 @@
486 486 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
487 487 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
488 488 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
  489 +
  490 +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
  491 +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
  492 + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
  493 +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
  494 + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
489 495 };
490 496  
491 497 #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
arch/arm/mach-omap2/prcm.c
Diff comments   View file @ f40aac9
... ... @@ -17,6 +17,7 @@
17 17 #include <linux/init.h>
18 18 #include <linux/clk.h>
19 19 #include <linux/io.h>
  20 +#include <linux/delay.h>
20 21  
21 22 #include <mach/common.h>
22 23 #include <mach/prcm.h>
... ... @@ -28,6 +29,8 @@
28 29 static void __iomem *prm_base;
29 30 static void __iomem *cm_base;
30 31  
  32 +#define MAX_MODULE_ENABLE_WAIT 100000
  33 +
31 34 u32 omap_prcm_get_reset_sources(void)
32 35 {
33 36 /* XXX This presumably needs modification for 34XX */
... ... @@ -119,6 +122,46 @@
119 122 return v;
120 123 }
121 124 EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
  125 +
  126 +/**
  127 + * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
  128 + * @reg: physical address of module IDLEST register
  129 + * @mask: value to mask against to determine if the module is active
  130 + * @name: name of the clock (for printk)
  131 + *
  132 + * Returns 1 if the module indicated readiness in time, or 0 if it
  133 + * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
  134 + */
  135 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
  136 +{
  137 + int i = 0;
  138 + int ena = 0;
  139 +
  140 + /*
  141 + * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
  142 + * 34xx reverses this, just to keep us on our toes
  143 + */
  144 + if (cpu_is_omap24xx())
  145 + ena = mask;
  146 + else if (cpu_is_omap34xx())
  147 + ena = 0;
  148 + else
  149 + BUG();
  150 +
  151 + /* Wait for lock */
  152 + while (((__raw_readl(reg) & mask) != ena) &&
  153 + (i++ < MAX_MODULE_ENABLE_WAIT))
  154 + udelay(1);
  155 +
  156 + if (i < MAX_MODULE_ENABLE_WAIT)
  157 + pr_debug("cm: Module associated with clock %s ready after %d "
  158 + "loops\n", name, i);
  159 + else
  160 + pr_err("cm: Module associated with clock %s didn't enable in "
  161 + "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
  162 +
  163 + return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
  164 +};
122 165  
123 166 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
124 167 {
arch/arm/mach-omap2/sdrc.c
Diff comments   View file @ f40aac9
... ... @@ -32,7 +32,7 @@
32 32 #include <mach/sdrc.h>
33 33 #include "sdrc.h"
34 34  
35   -static struct omap_sdrc_params *sdrc_init_params;
  35 +static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
36 36  
37 37 void __iomem *omap2_sdrc_base;
38 38 void __iomem *omap2_sms_base;
39 39  
40 40  
41 41  
42 42  
43 43  
44 44  
45 45  
46 46  
... ... @@ -45,33 +45,49 @@
45 45 /**
46 46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
47 47 * @r: SDRC clock rate (in Hz)
  48 + * @sdrc_cs0: chip select 0 ram timings **
  49 + * @sdrc_cs1: chip select 1 ram timings **
48 50 *
49 51 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
50   - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
51   - * SDRC clock rate 'r'. These parameters control various timing
52   - * delays in the SDRAM controller that are expressed in terms of the
53   - * number of SDRC clock cycles to wait; hence the clock rate
54   - * dependency. Note that sdrc_init_params must be sorted rate
55   - * descending. Also assumes that both chip-selects use the same
56   - * timing parameters. Returns a struct omap_sdrc_params * upon
57   - * success, or NULL upon failure.
  52 + * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
  53 + * structs,for a given SDRC clock rate 'r'.
  54 + * These parameters control various timing delays in the SDRAM controller
  55 + * that are expressed in terms of the number of SDRC clock cycles to
  56 + * wait; hence the clock rate dependency.
  57 + *
  58 + * Supports 2 different timing parameters for both chip selects.
  59 + *
  60 + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
  61 + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
  62 + * as sdrc_init_params_cs_0.
  63 + *
  64 + * Fills in the struct omap_sdrc_params * for each chip select.
  65 + * Returns 0 upon success or -1 upon failure.
58 66 */
59   -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
  67 +int omap2_sdrc_get_params(unsigned long r,
  68 + struct omap_sdrc_params **sdrc_cs0,
  69 + struct omap_sdrc_params **sdrc_cs1)
60 70 {
61   - struct omap_sdrc_params *sp;
  71 + struct omap_sdrc_params *sp0, *sp1;
62 72  
63   - if (!sdrc_init_params)
64   - return NULL;
  73 + if (!sdrc_init_params_cs0)
  74 + return -1;
65 75  
66   - sp = sdrc_init_params;
  76 + sp0 = sdrc_init_params_cs0;
  77 + sp1 = sdrc_init_params_cs1;
67 78  
68   - while (sp->rate && sp->rate != r)
69   - sp++;
  79 + while (sp0->rate && sp0->rate != r) {
  80 + sp0++;
  81 + if (sdrc_init_params_cs1)
  82 + sp1++;
  83 + }
70 84  
71   - if (!sp->rate)
72   - return NULL;
  85 + if (!sp0->rate)
  86 + return -1;
73 87  
74   - return sp;
  88 + *sdrc_cs0 = sp0;
  89 + *sdrc_cs1 = sp1;
  90 + return 0;
75 91 }
76 92  
77 93  
78 94  
... ... @@ -83,13 +99,15 @@
83 99  
84 100 /**
85 101 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
86   - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
  102 + * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
  103 + * Support for 2 chip selects timings
87 104 *
88 105 * Turn on smart idle modes for SDRAM scheduler and controller.
89 106 * Program a known-good configuration for the SDRC to deal with buggy
90 107 * bootloaders.
91 108 */
92   -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
  109 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  110 + struct omap_sdrc_params *sdrc_cs1)
93 111 {
94 112 u32 l;
95 113  
96 114  
97 115  
... ... @@ -103,11 +121,15 @@
103 121 l |= (0x2 << 3);
104 122 sdrc_write_reg(l, SDRC_SYSCONFIG);
105 123  
106   - sdrc_init_params = sp;
  124 + sdrc_init_params_cs0 = sdrc_cs0;
  125 + sdrc_init_params_cs1 = sdrc_cs1;
107 126  
108 127 /* XXX Enable SRFRONIDLEREQ here also? */
  128 + /*
  129 + * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
  130 + * can cause random memory corruption
  131 + */
109 132 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
110   - (1 << SDRC_POWER_PWDENA_SHIFT) |
111 133 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
112 134 sdrc_write_reg(l, SDRC_POWER);
113 135 }
arch/arm/mach-omap2/sram34xx.S
Diff comments   View file @ f40aac9
... ... @@ -36,7 +36,7 @@
36 36  
37 37 .text
38 38  
39   -/* r4 parameters */
  39 +/* r1 parameters */
40 40 #define SDRC_NO_UNLOCK_DLL 0x0
41 41 #define SDRC_UNLOCK_DLL 0x1
42 42  
... ... @@ -58,7 +58,6 @@
58 58  
59 59 /* SDRC_POWER bit settings */
60 60 #define SRFRONIDLEREQ_MASK 0x40
61   -#define PWDENA_MASK 0x4
62 61  
63 62 /* CM_IDLEST1_CORE bit settings */
64 63 #define ST_SDRC_MASK 0x2
65 64  
66 65  
67 66  
68 67  
69 68  
70 69  
71 70  
72 71  
73 72  
74 73  
... ... @@ -71,41 +70,72 @@
71 70  
72 71 /*
73 72 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
74   - * r0 = new SDRC_RFR_CTRL register contents
75   - * r1 = new SDRC_ACTIM_CTRLA register contents
76   - * r2 = new SDRC_ACTIM_CTRLB register contents
77   - * r3 = new M2 divider setting (only 1 and 2 supported right now)
78   - * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
  73 + *
  74 + * Params passed in registers:
  75 + * r0 = new M2 divider setting (only 1 and 2 supported right now)
  76 + * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
79 77 * SDRC rates < 83MHz
80   - * r5 = number of MPU cycles to wait for SDRC to stabilize after
  78 + * r2 = number of MPU cycles to wait for SDRC to stabilize after
81 79 * reprogramming the SDRC when switching to a slower MPU speed
82   - * r6 = new SDRC_MR_0 register value
83   - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
  80 + * r3 = increasing SDRC rate? (1 = yes, 0 = no)
84 81 *
  82 + * Params passed via the stack. The needed params will be copied in SRAM
  83 + * before use by the code in SRAM (SDRAM is not accessible during SDRC
  84 + * reconfiguration):
  85 + * new SDRC_RFR_CTRL_0 register contents
  86 + * new SDRC_ACTIM_CTRL_A_0 register contents
  87 + * new SDRC_ACTIM_CTRL_B_0 register contents
  88 + * new SDRC_MR_0 register value
  89 + * new SDRC_RFR_CTRL_1 register contents
  90 + * new SDRC_ACTIM_CTRL_A_1 register contents
  91 + * new SDRC_ACTIM_CTRL_B_1 register contents
  92 + * new SDRC_MR_1 register value
  93 + *
  94 + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
  95 + * are not programmed into the SDRC CS1 registers
85 96 */
86 97 ENTRY(omap3_sram_configure_core_dpll)
87 98 stmfd sp!, {r1-r12, lr} @ store regs to stack
88   - ldr r4, [sp, #52] @ pull extra args off the stack
89   - ldr r5, [sp, #56] @ load extra args from the stack
90   - ldr r6, [sp, #60] @ load extra args from the stack
91   - ldr r7, [sp, #64] @ load extra args from the stack
  99 +
  100 + @ pull the extra args off the stack
  101 + @ and store them in SRAM
  102 + ldr r4, [sp, #52]
  103 + str r4, omap_sdrc_rfr_ctrl_0_val
  104 + ldr r4, [sp, #56]
  105 + str r4, omap_sdrc_actim_ctrl_a_0_val
  106 + ldr r4, [sp, #60]
  107 + str r4, omap_sdrc_actim_ctrl_b_0_val
  108 + ldr r4, [sp, #64]
  109 + str r4, omap_sdrc_mr_0_val
  110 + ldr r4, [sp, #68]
  111 + str r4, omap_sdrc_rfr_ctrl_1_val
  112 + cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
  113 + beq skip_cs1_params @ do not use cs1 params
  114 + ldr r4, [sp, #72]
  115 + str r4, omap_sdrc_actim_ctrl_a_1_val
  116 + ldr r4, [sp, #76]
  117 + str r4, omap_sdrc_actim_ctrl_b_1_val
  118 + ldr r4, [sp, #80]
  119 + str r4, omap_sdrc_mr_1_val
  120 +skip_cs1_params:
92 121 dsb @ flush buffered writes to interconnect
93   - cmp r7, #1 @ if increasing SDRC clk rate,
  122 +
  123 + cmp r3, #1 @ if increasing SDRC clk rate,
94 124 bleq configure_sdrc @ program the SDRC regs early (for RFR)
95   - cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
  125 + cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
96 126 bleq unlock_dll
97 127 blne lock_dll
98 128 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
99 129 bl configure_core_dpll @ change the DPLL3 M2 divider
  130 + mov r12, r2
  131 + bl wait_clk_stable @ wait for SDRC to stabilize
100 132 bl enable_sdrc @ take SDRC out of idle
101   - cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
  133 + cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
102 134 bleq wait_dll_unlock
103 135 blne wait_dll_lock
104   - cmp r7, #1 @ if increasing SDRC clk rate,
  136 + cmp r3, #1 @ if increasing SDRC clk rate,
105 137 beq return_to_sdram @ return to SDRAM code, otherwise,
106 138 bl configure_sdrc @ reprogram SDRC regs now
107   - mov r12, r5
108   - bl wait_clk_stable @ wait for SDRC to stabilize
109 139 return_to_sdram:
110 140 isb @ prevent speculative exec past here
111 141 mov r0, #0 @ return value
... ... @@ -113,7 +143,7 @@
113 143 unlock_dll:
114 144 ldr r11, omap3_sdrc_dlla_ctrl
115 145 ldr r12, [r11]
116   - and r12, r12, #FIXEDDELAY_MASK
  146 + bic r12, r12, #FIXEDDELAY_MASK
117 147 orr r12, r12, #FIXEDDELAY_DEFAULT
118 148 orr r12, r12, #DLLIDLE_MASK
119 149 str r12, [r11] @ (no OCP barrier needed)
... ... @@ -129,7 +159,6 @@
129 159 ldr r12, [r11] @ read the contents of SDRC_POWER
130 160 mov r9, r12 @ keep a copy of SDRC_POWER bits
131 161 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
132   - bic r12, r12, #PWDENA_MASK @ clear PWDENA
133 162 str r12, [r11] @ write back to SDRC_POWER register
134 163 ldr r12, [r11] @ posted-write barrier for SDRC
135 164 idle_sdrc:
... ... @@ -149,7 +178,7 @@
149 178 ldr r12, [r11]
150 179 ldr r10, core_m2_mask_val @ modify m2 for core dpll
151 180 and r12, r12, r10
152   - orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
  181 + orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
153 182 str r12, [r11]
154 183 ldr r12, [r11] @ posted-write barrier for CM
155 184 bx lr
156 185  
... ... @@ -187,15 +216,34 @@
187 216 bne wait_dll_unlock
188 217 bx lr
189 218 configure_sdrc:
190   - ldr r11, omap3_sdrc_rfr_ctrl
191   - str r0, [r11]
192   - ldr r11, omap3_sdrc_actim_ctrla
193   - str r1, [r11]
194   - ldr r11, omap3_sdrc_actim_ctrlb
195   - str r2, [r11]
  219 + ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
  220 + ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
  221 + str r12, [r11] @ store
  222 + ldr r12, omap_sdrc_actim_ctrl_a_0_val
  223 + ldr r11, omap3_sdrc_actim_ctrl_a_0
  224 + str r12, [r11]
  225 + ldr r12, omap_sdrc_actim_ctrl_b_0_val
  226 + ldr r11, omap3_sdrc_actim_ctrl_b_0
  227 + str r12, [r11]
  228 + ldr r12, omap_sdrc_mr_0_val
196 229 ldr r11, omap3_sdrc_mr_0
197   - str r6, [r11]
198   - ldr r6, [r11] @ posted-write barrier for SDRC
  230 + str r12, [r11]
  231 + ldr r12, omap_sdrc_rfr_ctrl_1_val
  232 + cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
  233 + beq skip_cs1_prog @ do not program cs1 params
  234 + ldr r11, omap3_sdrc_rfr_ctrl_1
  235 + str r12, [r11]
  236 + ldr r12, omap_sdrc_actim_ctrl_a_1_val
  237 + ldr r11, omap3_sdrc_actim_ctrl_a_1
  238 + str r12, [r11]
  239 + ldr r12, omap_sdrc_actim_ctrl_b_1_val
  240 + ldr r11, omap3_sdrc_actim_ctrl_b_1
  241 + str r12, [r11]
  242 + ldr r12, omap_sdrc_mr_1_val
  243 + ldr r11, omap3_sdrc_mr_1
  244 + str r12, [r11]
  245 +skip_cs1_prog:
  246 + ldr r12, [r11] @ posted-write barrier for SDRC
199 247 bx lr
200 248  
201 249 omap3_sdrc_power:
202 250  
203 251  
204 252  
205 253  
... ... @@ -206,14 +254,40 @@
206 254 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
207 255 omap3_cm_iclken1_core:
208 256 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
209   -omap3_sdrc_rfr_ctrl:
  257 +
  258 +omap3_sdrc_rfr_ctrl_0:
210 259 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
211   -omap3_sdrc_actim_ctrla:
  260 +omap3_sdrc_rfr_ctrl_1:
  261 + .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
  262 +omap3_sdrc_actim_ctrl_a_0:
212 263 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
213   -omap3_sdrc_actim_ctrlb:
  264 +omap3_sdrc_actim_ctrl_a_1:
  265 + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
  266 +omap3_sdrc_actim_ctrl_b_0:
214 267 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
  268 +omap3_sdrc_actim_ctrl_b_1:
  269 + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
215 270 omap3_sdrc_mr_0:
216 271 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
  272 +omap3_sdrc_mr_1:
  273 + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
  274 +omap_sdrc_rfr_ctrl_0_val:
  275 + .word 0xDEADBEEF
  276 +omap_sdrc_rfr_ctrl_1_val:
  277 + .word 0xDEADBEEF
  278 +omap_sdrc_actim_ctrl_a_0_val:
  279 + .word 0xDEADBEEF
  280 +omap_sdrc_actim_ctrl_a_1_val:
  281 + .word 0xDEADBEEF
  282 +omap_sdrc_actim_ctrl_b_0_val:
  283 + .word 0xDEADBEEF
  284 +omap_sdrc_actim_ctrl_b_1_val:
  285 + .word 0xDEADBEEF
  286 +omap_sdrc_mr_0_val:
  287 + .word 0xDEADBEEF
  288 +omap_sdrc_mr_1_val:
  289 + .word 0xDEADBEEF
  290 +
217 291 omap3_sdrc_dlla_status:
218 292 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
219 293 omap3_sdrc_dlla_ctrl:
arch/arm/plat-omap/include/mach/clock.h
Diff comments   View file @ f40aac9
... ... @@ -20,6 +20,8 @@
20 20 struct clkops {
21 21 int (*enable)(struct clk *);
22 22 void (*disable)(struct clk *);
  23 + void (*find_idlest)(struct clk *, void __iomem **, u8 *);
  24 + void (*find_companion)(struct clk *, void __iomem **, u8 *);
23 25 };
24 26  
25 27 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
arch/arm/plat-omap/include/mach/io.h
Diff comments   View file @ f40aac9
... ... @@ -228,7 +228,8 @@
228 228 extern void omap1_init_common_hw(void);
229 229  
230 230 extern void omap2_map_common_io(void);
231   -extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
  231 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
  232 + struct omap_sdrc_params *sdrc_cs1);
232 233  
233 234 #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
234 235 #define __arch_iounmap(v) omap_iounmap(v)
arch/arm/plat-omap/include/mach/mux.h
Diff comments   View file @ f40aac9
... ... @@ -853,6 +853,10 @@
853 853 AE5_34XX_GPIO143,
854 854 H19_34XX_GPIO164_OUT,
855 855 J25_34XX_GPIO170,
  856 +
  857 + /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
  858 + H16_34XX_SDRC_CKE0,
  859 + H17_34XX_SDRC_CKE1,
856 860 };
857 861  
858 862 struct omap_mux_cfg {
arch/arm/plat-omap/include/mach/prcm.h
Diff comments   View file @ f40aac9
... ... @@ -25,6 +25,7 @@
25 25  
26 26 u32 omap_prcm_get_reset_sources(void);
27 27 void omap_prcm_arch_reset(char mode);
  28 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
28 29  
29 30 #endif
arch/arm/plat-omap/include/mach/sdrc.h
Diff comments   View file @ f40aac9
... ... @@ -30,6 +30,10 @@
30 30 #define SDRC_ACTIM_CTRL_A_0 0x09c
31 31 #define SDRC_ACTIM_CTRL_B_0 0x0a0
32 32 #define SDRC_RFR_CTRL_0 0x0a4
  33 +#define SDRC_MR_1 0x0B4
  34 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
  35 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
  36 +#define SDRC_RFR_CTRL_1 0x0D4
33 37  
34 38 /*
35 39 * These values represent the number of memory clock cycles between
... ... @@ -102,8 +106,11 @@
102 106 u32 mr;
103 107 };
104 108  
105   -void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
106   -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
  109 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  110 + struct omap_sdrc_params *sdrc_cs1);
  111 +int omap2_sdrc_get_params(unsigned long r,
  112 + struct omap_sdrc_params **sdrc_cs0,
  113 + struct omap_sdrc_params **sdrc_cs1);
107 114  
108 115 #ifdef CONFIG_ARCH_OMAP2
109 116  
arch/arm/plat-omap/include/mach/sram.h
Diff comments   View file @ f40aac9
... ... @@ -21,11 +21,12 @@
21 21 u32 mem_type);
22 22 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23  
24   -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25   - u32 sdrc_actim_ctrla,
26   - u32 sdrc_actim_ctrlb, u32 m2,
27   - u32 unlock_dll, u32 f, u32 sdrc_mr,
28   - u32 inc);
  24 +extern u32 omap3_configure_core_dpll(
  25 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  26 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  27 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  28 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  29 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
29 30  
30 31 /* Do not use these */
31 32 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
... ... @@ -59,12 +60,12 @@
59 60 u32 mem_type);
60 61 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
61 62  
62   -
63   -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
64   - u32 sdrc_actim_ctrla,
65   - u32 sdrc_actim_ctrlb, u32 m2,
66   - u32 unlock_dll, u32 f, u32 sdrc_mr,
67   - u32 inc);
  63 +extern u32 omap3_sram_configure_core_dpll(
  64 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  65 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  66 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  67 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  68 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
68 69 extern unsigned long omap3_sram_configure_core_dpll_sz;
69 70  
70 71 #endif
arch/arm/plat-omap/sram.c
Diff comments   View file @ f40aac9
... ... @@ -373,20 +373,26 @@
373 373  
374 374 #ifdef CONFIG_ARCH_OMAP3
375 375  
376   -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
377   - u32 sdrc_actim_ctrla,
378   - u32 sdrc_actim_ctrlb,
379   - u32 m2, u32 unlock_dll,
380   - u32 f, u32 sdrc_mr, u32 inc);
381   -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
382   - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
383   - u32 f, u32 sdrc_mr, u32 inc)
  376 +static u32 (*_omap3_sram_configure_core_dpll)(
  377 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  378 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  379 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  380 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  381 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
  382 +
  383 +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
  384 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  385 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  386 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  387 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
384 388 {
385 389 BUG_ON(!_omap3_sram_configure_core_dpll);
386   - return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
387   - sdrc_actim_ctrla,
388   - sdrc_actim_ctrlb, m2,
389   - unlock_dll, f, sdrc_mr, inc);
  390 + return _omap3_sram_configure_core_dpll(
  391 + m2, unlock_dll, f, inc,
  392 + sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
  393 + sdrc_actim_ctrl_b_0, sdrc_mr_0,
  394 + sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
  395 + sdrc_actim_ctrl_b_1, sdrc_mr_1);
390 396 }
391 397  
392 398 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */