13 Aug, 2010

1 commit


11 Aug, 2010

1 commit


10 Aug, 2010

1 commit

  • * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits)
    DMAENGINE: at_hdmac: locking fixlet
    DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l
    dma: dmatest: fix potential sign bug
    ioat2: catch and recover from broken vtd configurations v6
    DMAENGINE: add runtime slave control to COH 901 318 v3
    DMAENGINE: add runtime slave config to DMA40 v3
    DMAENGINE: generic slave channel control v3
    dmaengine: Driver for Topcliff PCH DMA controller
    intel_mid: Add Mrst & Mfld DMA Drivers
    drivers/dma: Eliminate a NULL pointer dereference
    dma/timb_dma: compile warning on 32 bit
    DMAENGINE: ste_dma40: support older silicon
    DMAENGINE: ste_dma40: support disabling physical channels
    DMAENGINE: ste_dma40: no disabled phy channels on ux500
    DMAENGINE: ste_dma40: fix suspend bug
    DMAENGINE: ste_dma40: add DB8500 memcpy channels
    DMAENGINE: ste_dma40: no flow control on memcpy
    DMAENGINE: ste_dma40: arch updates for LCLA and LCPA
    DMAENGINE: ste_dma40: allocate LCLA dynamically
    DMAENGINE: ste_dma40: no premature stop
    ...

    Fix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c

    Linus Torvalds
     

07 Aug, 2010

1 commit


06 Aug, 2010

1 commit

  • of_device is just an alias for platform_device, so remove it entirely. Also
    replace to_of_device() with to_platform_device() and update comment blocks.

    This patch was initially generated from the following semantic patch, and then
    edited by hand to pick up the bits that coccinelle didn't catch.

    @@
    @@
    -struct of_device
    +struct platform_device

    Signed-off-by: Grant Likely
    Reviewed-by: David S. Miller

    Grant Likely
     

05 Aug, 2010

7 commits

  • atc_chain_complete shall be called with atchan->lock held
    and bh disabled.

    Signed-off-by: Yong Wang
    Signed-off-by: Dan Williams

    Yong Wang
     
  • Use {read|write}l instead of __raw_{read|write}l since PCH DMA
    controller is PCI device.

    Signed-off-by: Yong Wang
    Signed-off-by: Dan Williams

    Yong Wang
     
  • 'cnt' is unsigned, so this code may become wrong in future as
    dmatest_add_threads() can return error code:

    cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
    thread_count += cnt > 0 ? cnt : 0;
    ^^^^^^^

    Now it can return only -EINVAL if and only if second argument of
    dmatest_add_threads() is not one of DMA_MEMCPY, DMA_XOR, DMA_PQ.
    So, now it is not wrong but may become wrong in future.

    The semantic patch that finds this problem (many false-positive results):
    (http://coccinelle.lip6.fr/)

    //
    @ r1 @
    identifier f;
    @@
    int f(...) { ... }

    @@
    identifier r1.f;
    type T;
    unsigned T x;
    @@

    *x = f(...)
    ...
    *x > 0

    Signed-off-by: Kulikov Vasiliy
    Signed-off-by: Dan Williams

    Kulikov Vasiliy
     
  • On some platforms (MacPro3,1) the BIOS assigns the ioatdma device to the
    incorrect iommu causing faults when the driver initializes. Add a quirk
    to catch this misconfiguration and try falling back to untranslated
    operation (which works in the MacPro3,1 case).

    Assuming there are other platforms with misconfigured iommus teach the
    ioatdma driver to treat initialization failures as non-fatal (just fail
    the driver load and emit a warning instead of triggering a BUG_ON).

    This can be classified as a boot regression since 2.6.32 on affected
    platforms since the ioatdma module did not autoload prior to that
    kernel.

    Cc:
    Acked-by: David Woodhouse
    Reported-by: Chris Li
    Tested-by: Chris Li
    Signed-off-by: Dan Williams

    Dan Williams
     
  • This extends the DMA engine driver for the COH 901 318 used in the
    U300 platform with the generic runtime slave control command.

    Signed-off-by: Linus Walleij
    Signed-off-by: Dan Williams

    Linus Walleij
     
  • This extends the DMA engine driver for the DMA40 used in the
    U8500 platform with the generic runtime slave configuration
    interface.

    Signed-off-by: Linus Walleij
    Signed-off-by: Dan Williams

    Linus Walleij
     
  • Topcliff PCH is the platform controller hub that is going to
    be used in Intel's upcoming general embedded platforms. This
    adds the driver for Topcliff PCH DMA controller. The DMA
    channels are strictly for device to host or host to device
    transfers and cannot be used for generic memcpy.

    Signed-off-by: Yong Wang
    [kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet]
    Signed-off-by: Dan Williams

    Yong Wang
     

04 Aug, 2010

2 commits


28 Jul, 2010

1 commit

  • This patch add DMA drivers for DMA controllers in Langwell chipset
    of Intel(R) Moorestown platform and DMA controllers in Penwell of
    Intel(R) Medfield platfrom

    This patch adds support for Moorestown DMAC1 and DMAC2 controllers.
    It also add support for Medfiled GP DMA and DMAC1 controllers.
    These controllers supports memory to peripheral and peripheral to
    memory transfers. It support only single block transfers.

    This driver is based on Kernel DMA engine
    Anyone who wishes to use this controller should use DMA engine APIs

    This controller exposes DMA_SLAVE capabilities and notifies the client drivers
    of DMA transaction completion

    Config option required to be enabled CONFIG_INTEL_MID_DMAC=y

    Signed-off-by: Vinod Koul
    Signed-off-by: Alan Cox
    Signed-off-by: Dan Williams

    Vinod Koul
     

05 Jul, 2010

1 commit


03 Jul, 2010

1 commit


01 Jul, 2010

3 commits


23 Jun, 2010

15 commits


17 Jun, 2010

2 commits


03 Jun, 2010

2 commits


31 May, 2010

1 commit