12 Nov, 2009
34 commits
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This patch adds support and enables state C4(MPU RET + CORE RET)
and MPU OFF states (C3 and C5.)Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Basic CPUidle driver for OMAP3 with deepest sleep state supported
being MPU CSWR.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Due to an OMAP3 errata (1.142), on HS/EMU devices SDRC should be
programed to issue automatic self refresh on timeout
of AUTO_CNT = 1 prior to any transition to OFF mode.
This is needed only on sil rev's ES3.0 and above.This patch enables the above needed WA in the SDRC power register
value stored in scratchpad, so that ROM code restores this value
in SDRC POWER on the wakeup path.
The original SDRC POWER register value is stored and restored back
in omap_sram_idle() function.This fixes some random crashes observed while stressing suspend
on HS/EMU devices.Signed-off-by: Rajendra Nayak
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
wake up enabling. It needs to be enabled when entering
retention or off state, otherwise waking up might not work
in all situations.Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
MPU and CORE should stay awake if there is CAM domain ACTIVE. This is
because that module doesn't have wake-up capability.This should replace the patch that is currently in the PM branch.
Signed-off-by: Jouni Hogander
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
OMAP3 can't generate wakeups in this state, thus it is not permitted.
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
Signed-off-by: Kevin Hilman
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Using debugfs, export a configurable wakeup timer to be used to
wakeup system from suspend.If a non-zero value is written to
/debug/pm_debug/wakeup_timer_seconds, A timer wakeup event will wake
the system and resume after the configured number of seconds.Signed-off-by: Kevin Hilman
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Allow enable/disable of low-power states during idle. To
enable low-power idle:echo 1 > /debug/pm_debug/sleep_while_idle
to disable:
echo 0 > /debug/pm_debug/sleep_while_idle
Also allow enable/disable of OFF-mode. To enable:
echo 1 > /debug/pm_debug/enable_off_mode
to disable:
echo 0 > /debug/pm_debug/enable_off_mode
Signed-off-by: Kevin Hilman
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This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.Signed-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman -
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
Wrong index was used for ILR.
Signed-off-by: Aaro Koskinen
Signed-off-by: Kevin Hilman -
Errata: ES3.0, ES3.1 SDRC not sending auto-refresh when OMAP wakes-up
from OFF modeSigned-off-by: Tero Kristo
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
The reboot mode can be communicated to a bootloader (or the
kernel itself) with a scratchpad register. This functionality
is especially useful, if userspace is allowed to change
the reboot mode.Signed-off-by: Juha Yrjola
Signed-off-by: Tony Lindgren
Signed-off-by: Kevin Hilman -
Clear DMA channel states so that users can assume a known initial
state.Signed-off-by: Aaro Koskinen
Signed-off-by: Kevin Hilman -
The CM_CLKEN_PLL register saved in scratchpad memory
was wrongly using offset of 0x0004 instead of 0x0000.The effect of this was that boot ROM code would
restore the wrong value when waking up from off mode.
This wrong value, however, will be overwritten by
prcm context restore. Still, a short period of wrong
clock settings in CM_CLKEN_PLL remained between ROM
code and prcm context restore. This is fixed by the
patch.Problem reported by: Jouni Hogander
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
The SMS_SYSCONFIG register gets reset in off mode, added a
save/restore mechanism for that.Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.Signed-off-by: Kalle Jokiniemi
Signed-off-by: Jouni Hogander
Signed-off-by: Kevin Hilman -
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.Signed-off-by: Jouni Hogander
Signed-off-by: Kevin Hilman -
Fix for ES3.0 bug: SDRC not sending auto-refresh when OMAP wakes-up
from OFF mode (warning for HS devices.)Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
The function omap3_save_secure_ram() is now called only once during
the initialization of the device and consequent sleep cycles will
re-use the same saved contents for secure RAM. Users who need secure
services should do secure RAM saving before entering off-mode, if a
secure service has been accessed after last save.There are both latency and reliability issues with saving secure RAM
context in the idle path. The context save uses a hardware resource
which takes an order of hundreds of milliseconds to initialize after a
wake up from off-mode, and also there is no way of checking whether it
is ready from kernel side or not. It just crashes if you use it too
quicklyAdditional fix to ensure scratchpad save is done after secure
RAM by Roger Quadros.Signed-off-by: Tero Kristo
Signed-off-by: Roger Quadros
Signed-off-by: Kevin Hilman -
For HS/EMU devices, some additional resources need to be
saved/restored for off-mode support. Namely, saving the secure RAM
and a pointer to it in the scratchpad.Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
For HS/EMU devices, these additional features are also used:
- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restoreSigned-off-by: Tero Kristo
Signed-off-by: Kevin Hilman -
Add context save and restore for CORE powerdomain resources in order
to support off-mode.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Adds a 'save_state' option when calling into SRAM idle function
and adds some minor cleanups of SRAM asm code.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
During the MMU restoration on the restore path from MPU OFF, the page
table entry for the page consisting of the code being executed is
modified to make MMU return VA=PA.The MMU is then enabled and the original entry is being stored in
scratchpad. This patch reads the original values stored in
scratchpad, and restores them back.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Expand the powerdomains handled in the idle path to include PER, NEON
and CORE. This includes properly clearing the previous powerstates,
linking NEON state to MPU state and calling the UART prepare functions
for only the appropraite powerdomain transitions (CORE for UART1,2,
PER for UART3.)Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Generalize the copy of SRAM functions into omap_push_sram_idle()
so it can be used on init but also after off-mode transitions.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Add context save and restore for the System Control Module to suport
off-mode.ETK and debobs definitions added by Peter De Schrijver.
Signed-off-by: Rajendra Nayak
Signed-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman -
This patch populates the scratchpad contents as expected by the
bootROM code.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Add context save and restore for PRCM module to support off-mode.
Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero
Kristo.Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi.
Signed-off-by: Rajendra Nayak
Signed-off-by: Tero Kristo
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman -
Add context save and restore for the INTC module to support off-mode.
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
Add context save and restore to enable off-mode.
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman -
This patch adds the context save and restore functions for GPMC to
enable off-mode.Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
11 Nov, 2009
1 commit
04 Nov, 2009
5 commits
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* 'for-linus' of git://github.com/at91linux/linux-2.6-at91:
at91: at91sam9g45 family: identify several chip versions
avr32: add two new at91 to cpu.h definition -
cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.Signed-off-by: Nicolas Ferre
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Acked-by: Hans-Christian Egtvedt -
Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.Signed-off-by: Nicolas Ferre
Signed-off-by: Haavard Skinnemoen -
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...
