20 Oct, 2011
1 commit
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Currently no type of alignment is specified for PCI expansion roms while
parsing the openfirmware tree. This causes calls to pci_map_rom() to fail.
IORESOURCE_SIZEALIGN is the default alignment used for rom resouces in
pci/probe.c, and has been verified to work with various cards on a ultra 10.Signed-off-By: Kjetil Oftedal
Signed-off-by: David S. Miller
13 Oct, 2011
2 commits
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Use set_current_blocked() instead.
Signed-off-by: David S. Miller
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As described in e6fa16ab ("signal: sigprocmask() should do
retarget_shared_pending()") the modification of current->blocked is
incorrect as we need to check whether the signal we're about to block
is pending in the shared queue.Cc: Oleg Nesterov
Cc: "David S. Miller"
Signed-off-by: Matt Fleming
Signed-off-by: David S. Miller
08 Oct, 2011
1 commit
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The LEON MMU Model (SRMMU) does not implement MMu Table probing
in hardware, instead it is implemented in software. However the
software implementation does not return the PTE as it should which
always results in INVALID entires and the PROM mappings are not
inherited as they should during startup. The following patch
removes the masking of the PTE.Signed-off-by: Daniel Hellstrom
Signed-off-by: David S. Miller
30 Sep, 2011
1 commit
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In the OF 'translations' property, the template TTEs in the mappings
never specify the executable bit. This is the case even though some
of these mappings are for OF's code segment.Therefore, we need to force the execute bit on in every mapping.
This problem can only really trigger on Niagara/sun4v machines and the
history behind this is a little complicated.Previous to sun4v, the sun4u TTE entries lacked a hardware execute
permission bit. So OF didn't have to ever worry about setting
anything to handle executable pages. Any valid TTE loaded into the
I-TLB would be respected by the chip.But sun4v Niagara chips have a real hardware enforced executable bit
in their TTEs. So it has to be set or else the I-TLB throws an
instruction access exception with type code 6 (protection violation).We've been extremely fortunate to not get bitten by this in the past.
The best I can tell is that the OF's mappings for it's executable code
were mapped using permanent locked mappings on sun4v in the past.
Therefore, the fact that we didn't have the exec bit set in the OF
translations we would use did not matter in practice.Thanks to Greg Onufer for helping me track this down.
Signed-off-by: David S. Miller
22 Sep, 2011
1 commit
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If "-p" is given on the command line, clear the CON_BOOT
flag for the initial early boot PROM console.This is necessary to try and see crash messages that occur
between the registry of the VT console and the probing of
the first framebuffer or serial console. During this time
no console messages are emitted because the VT console
registry (even if no backend is registered to it) removes
the early console if CON_BOOT is set.Signed-off-by: David S. Miller
21 Sep, 2011
1 commit
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The address limit is already set in flush_old_exec() so this assignment of
USER_DS is redundant.Signed-off-by: Mathias Krause
Cc: David Miller
Signed-off-by: Andrew Morton
Signed-off-by: David S. Miller
17 Sep, 2011
1 commit
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Recognize T4 and T5 chips. Treating them both as "T2 plus other
stuff" should be extremely safe and make sure distributions will work
when those chips actually ship to customers.Signed-off-by: David S. Miller
30 Aug, 2011
3 commits
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Signed-off-by: David S. Miller
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On Sun4d systems running in SMP mode, IRQ 14 is used for timer interrupts
and has a specialized interrupt handler. IPI is currently set to use IRQ 14
as well, which causes it to trigger the timer interrupt handler, and not the
IPI interrupt handler.The IPI interrupt is therefore changed to IRQ 13, which is the highest
normally handled interrupt. This IRQ is also used for SBUS interrupts,
however there is nothing in the IPI/SBUS interrupt handlers that indicate
that they will not handle sharing the interrupt.
(IRQ 13 is indicated as audio interrupt, which is unlikely to be found in a
sun4d system)Signed-off-by: Kjetil Oftedal
Signed-off-by: David S. Miller -
Signed-off-by: Stephen Rothwell
Signed-off-by: David S. Miller
27 Aug, 2011
1 commit
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The nfsservctl system call is now gone, so we should remove all
linkage for it.Signed-off-by: NeilBrown
Signed-off-by: J. Bruce Fields
Signed-off-by: Linus Torvalds
21 Aug, 2011
1 commit
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If we can't push the pending register windows onto the user's stack,
we disallow signal delivery even if the signal would be delivered on a
valid seperate signal stack.Add a register window save area in the signal frame, and store any
unsavable windows there.On sigreturn, if any windows are still queued up in the signal frame,
try to push them back onto the stack and if that fails we kill the
process immediately.This allows the debug/tst-longjmp_chk2 glibc test case to pass.
Signed-off-by: David S. Miller
19 Aug, 2011
1 commit
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CC arch/sparc/kernel/pcic.o
arch/sparc/kernel/pcic.c: In function 'pcic_probe':
arch/sparc/kernel/pcic.c:359:33: error: array subscript is above array bounds [-Werror=array-bounds]
arch/sparc/kernel/pcic.c:359:8: error: array subscript is above array bounds [-Werror=array-bounds]
arch/sparc/kernel/pcic.c:360:33: error: array subscript is above array bounds [-Werror=array-bounds]
arch/sparc/kernel/pcic.c:360:8: error: array subscript is above array bounds [-Werror=array-bounds]
arch/sparc/kernel/pcic.c:361:33: error: array subscript is above array bounds [-Werror=array-bounds]
arch/sparc/kernel/pcic.c:361:8: error: array subscript is above array bounds [-Werror=array-bounds]
cc1: all warnings being treated as errorsI'm not particularly familiar with sparc but t_nmi (defined in head_32.S via
the TRAP_ENTRY macro) and pcic_nmi_trap_patch (defined in entry.S) both appear
to be 4 instructions long and I presume from the usage that instructions are
int sized.Signed-off-by: Ian Campbell
Cc: "David S. Miller"
Cc: sparclinux@vger.kernel.org
Reviewed-by: Sam Ravnborg
Signed-off-by: David S. Miller
16 Aug, 2011
3 commits
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Signed-off-by: David S. Miller
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The sparc32 version of arch_write_unlock() is just a plain assignment.
Unfortunately this allows the compiler to schedule side-effects in a
protected region to occur after the HW-level unlock, which is broken.
E.g., the following trivial test case gets miscompiled:#include
rwlock_t lock;
int counter;
void foo(void) { write_lock(&lock); ++counter; write_unlock(&lock); }Fixed by adding a compiler memory barrier to arch_write_unlock(). The
sparc64 version combines the barrier and assignment into a single asm(),
and implements the operation as a static inline, so that's what I did too.Compile-tested with sparc32_defconfig + CONFIG_SMP=y.
Signed-off-by: Mikael Pettersson
Signed-off-by: David S. Miller -
The sparc64 spinlock_64.h contains a number of operations defined
first as static inline functions, and then as macros with the same
names and parameters as the functions. Maybe this was needed at
some point in the past, but now nothing seems to depend on these
macros (checked with a recursive grep looking for ifdefs on these
names). Other archs don't define these identity-macros.So this patch deletes these unnecessary macros.
Compile-tested with sparc64_defconfig.
Signed-off-by: Mikael Pettersson
Signed-off-by: David S. Miller
12 Aug, 2011
1 commit
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Reported-by: Pieter-Paul Giesberts
Signed-off-by: David S. Miller
06 Aug, 2011
2 commits
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arch/sparc/mm/init_64.c:1622:22: error: unused variable '__swapper_4m_tsb_phys_patch_end' [-Werror=unused-variable]
arch/sparc/mm/init_64.c:1621:22: error: unused variable '__swapper_4m_tsb_phys_patch' [-Werror=unused-variable]Signed-off-by: David S. Miller
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* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
sparc: Size mondo queues more sanely.
sparc: Access kernel TSB using physical addressing when possible.
sparc: Fix __atomic_add_unless() return value.
sparc: use kbuild-generic support for true asm-generic header files
sparc: Use popc when possible for ffs/__ffs/ffz.
sparc: Set reboot-cmd using reboot data hypervisor call if available.
sparc: Add some missing hypervisor API groups.
sparc: Use hweight64() in popc emulation.
sparc: Use popc if possible for hweight routines.
sparc: Minor tweaks to Niagara page copy/clear.
sparc: Sanitize cpu feature detection and reporting.
05 Aug, 2011
2 commits
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There is currently no upper limit on the mondo queue sizes we'll use,
which guarentees that we'll eventually his page allocation limits, and
thus allocation failures, due to MAX_ORDER.Cap the sizes sanely, current limits are:
CPU MONDO 2 * max_possible_cpus
DEV MONDO 256 (basically NR_IRQS)
RES MONDO 128
NRES MONDO 4Signed-off-by: David S. Miller
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On sun4v this is basically required since we point the hypervisor and
the TSB walking hardware at these tables using physical addressing
too.Signed-off-by: David S. Miller
04 Aug, 2011
2 commits
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Signed-off-by: David S. Miller
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Signed-off-by: Sam Ravnborg
Signed-off-by: David S. Miller
03 Aug, 2011
8 commits
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Some trivial conflicts due to other various merges
adding to the end of common lists sooner than this one.arch/ia64/Kconfig
arch/powerpc/Kconfig
arch/x86/Kconfig
lib/Kconfig
lib/MakefileSigned-off-by: Len Brown
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cmpxchg() is widely used by lockless code, including NMI-safe lockless
code. But on some architectures, the cmpxchg() implementation is not
NMI-safe, on these architectures the lockless code may need a
spin_trylock_irqsave() based implementation.This patch adds a Kconfig option: ARCH_HAVE_NMI_SAFE_CMPXCHG, so that
NMI-safe lockless code can depend on it or provide different
implementation according to it.On many architectures, cmpxchg is only NMI-safe for several specific
operand sizes. So, ARCH_HAVE_NMI_SAFE_CMPXCHG define in this patch
only guarantees cmpxchg is NMI-safe for sizeof(unsigned long).Signed-off-by: Huang Ying
Acked-by: Mike Frysinger
Acked-by: Paul Mundt
Acked-by: Hans-Christian Egtvedt
Acked-by: Benjamin Herrenschmidt
Acked-by: Chris Metcalf
Acked-by: Richard Henderson
CC: Mikael Starvik
Acked-by: David Howells
CC: Yoshinori Sato
CC: Tony Luck
CC: Hirokazu Takata
CC: Geert Uytterhoeven
CC: Michal Simek
Acked-by: Ralf Baechle
CC: Kyle McMartin
CC: Martin Schwidefsky
CC: Chen Liqin
CC: "David S. Miller"
CC: Ingo Molnar
CC: Chris Zankel
Signed-off-by: Len Brown -
Signed-off-by: David S. Miller
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Signed-off-by: David S. Miller
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Signed-off-by: David S. Miller
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Signed-off-by: David S. Miller
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Just like powerpc, we code patch at boot time.
Signed-off-by: David S. Miller
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Don't use floating point on Niagara2, use the traditional
plain Niagara code instead.Unroll Niagara loops to 128 bytes for copy, and 256 bytes
for clear.Signed-off-by: David S. Miller
01 Aug, 2011
1 commit
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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k:
m68k/math-emu: Remove unnecessary code
m68k/math-emu: Remove commented out old code
m68k: Kill warning in setup_arch() when compiling for Sun3
m68k/atari: Prefix GPIO_{IN,OUT} with CODEC_
sparc: iounmap() and *_free_coherent() - Use lookup_resource()
m68k/atari: Reserve some ST-RAM early on for device buffer use
m68k/amiga: Chip RAM - Use lookup_resource()
resources: Add lookup_resource()
sparc: _sparc_find_resource() should check for exact matches
m68k/amiga: Chip RAM - Offset resource end by CHIP_PHYSADDR
m68k/amiga: Chip RAM - Use resource_size() to fix off-by-one error
m68k/amiga: Chip RAM - Change chipavail to an atomic_t
m68k/amiga: Chip RAM - Always allocate from the start of memory
m68k/amiga: Chip RAM - Convert from printk() to pr_*()
m68k/amiga: Chip RAM - Use tabs for indentation
31 Jul, 2011
2 commits
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Replace a custom implementation (which doesn't lock the resource tree) by a
call to lookup_resource()Signed-off-by: Geert Uytterhoeven
Acked-by: David S. Miller -
The address that's passed to _sparc_find_resource() should always be the
start address of a resource:
- iounmap() passes a page-aligned virtual address, while the original
address was created by adding the in-page offset to the resource's
start address,
- sbus_free_coherent() and pci32_free_coherent() should be passed an
address obtained from sbus_alloc_coherent() resp. pci32_alloc_coherent(),
which is always a resource's start address.Hence replace the range check by a check for an exact match.
Signed-off-by: Geert Uytterhoeven
Acked-by: David S. Miller
30 Jul, 2011
1 commit
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* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: remove printks about disabled bridge windows
PCI: fold pci_calc_resource_flags() into decode_bar()
PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
PCI: correct pcie_set_readrq write size
PCI: pciehp: change wait time for valid configuration access
x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
PCI: ARI is a PCIe v2 feature
x86/PCI: quirks: Use pci_dev->revision
PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
PCI hotplug: cpqphp: use pci_dev->vendor
PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
x86/PCI: config space accessor functions should not ignore the segment argument
PCI: Assign values to 'pci_obff_signal_type' enumeration constants
x86/PCI: reduce severity of host bridge window conflict warnings
PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
PCI: PCIe AER: add aer_recover_queue
x86/PCI: select direct access mode for mmconfig option
PCI hotplug: Rename is_ejectable which also exists in dock.c
29 Jul, 2011
1 commit
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Instead of evaluating the cpu features for ELF_HWCAP every exec,
calculate it once at boot time.Add AV_SPARC_* capability flag bits, compatible with what Solaris
reports to applications.Report these capabilities once in the kernel log, and also via
/proc/cpuinfo in a new "cpucaps" entry.If available, fetch the cpu features from the machine description
'hwcap-list' property of the 'cpu' node.Signed-off-by: David S. Miller
28 Jul, 2011
3 commits
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The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.So we'll need about 3 new elf capability flags in the end to represent
all of these things.Signed-off-by: David S. Miller
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The hypervisor call is only necessary if hypervisor events are
being requested.So if we're not tracking hypervisor events, simply do a direct
register write.Signed-off-by: David S. Miller
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Signed-off-by: David S. Miller