05 Oct, 2010

2 commits

  • This splits up the sh intc core in to something more vaguely resembling
    a subsystem. Most of the functionality was alread fairly well
    compartmentalized, and there were only a handful of interdependencies
    that needed to be resolved in the process.

    This also serves as future-proofing for the genirq and sparseirq rework,
    which will make some of the split out functionality wholly generic,
    allowing things to be killed off in place with minimal migration pain.

    Signed-off-by: Paul Mundt

    Paul Mundt
     
  • This implements a scheme roughly analogous to the PowerPC virtual to
    hardware IRQ mapping, which we use for IRQ to per-controller ID mapping.
    This makes it possible for drivers to use the IDs directly for lookup
    instead of hardcoding the vector.

    The main motivation for this work is as a building block for dynamically
    allocating virtual IRQs for demuxing INTC events sharing a single INTEVT
    in addition to a common masking source.

    Signed-off-by: Paul Mundt

    Paul Mundt
     

02 Oct, 2010

1 commit


15 Apr, 2010

1 commit

  • This implements support for hardware-managed IRQ balancing as implemented
    by SH-X3 cores (presently only hooked up for SH7786, but can probably be
    carried over to other SH-X3 cores, too).

    CPUs need to specify their distribution register along with the mask
    definitions, as these follow the same format. Peripheral IRQs that don't
    opt out of balancing will be automatically distributed at the whim of the
    hardware block, while each CPU needs to verify whether it is handling the
    IRQ or not, especially before clearing the mask.

    Signed-off-by: Paul Mundt

    Paul Mundt
     

13 Apr, 2010

1 commit

  • This adds support for hardware-assisted userspace irq masking for
    special priority levels. Due to the SR.IMASK interactivity, only some
    platforms implement this in hardware (including but not limited to
    SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU
    needs to wire this up on its own, for now only SH7786 is wired up as an
    example.

    Signed-off-by: Paul Mundt

    Paul Mundt