17 Dec, 2008

1 commit

  • Does the same for the accompanying MDIO driver, and then modifies the TBI
    configuration method. The old way used fields in einfo, which no longer
    exists. The new way is to create an MDIO device-tree node for each instance
    of gianfar, and create a tbi-handle property to associate ethernet controllers
    with the TBI PHYs they are connected to.

    Signed-off-by: Andy Fleming
    Signed-off-by: David S. Miller

    Andy Fleming
     

11 Nov, 2008

1 commit

  • Commit d0fc2eaaf4c56a95f5ed29b6bfb609e19714fc16 "powerpc/fsl: Refactor
    device bindings" split out a number of device bindings from
    booting-without-of.txt into separate files. Having them all in one file
    was a frequent source of merge conflicts.

    However, in the next merge, 49997d75152b3d23c53b0fa730599f2f74c92c65, there
    was another conflict. Some of the bindings removed from
    booting-without-of.txt were mistakenly added back in and the copies in
    dts-bindings were kept as well.

    This patch re-removes "Freescale Display Interface" and "Freescale on board
    FPGA" and fixes the table of contents.

    Signed-off-by: Trent Piepho
    Signed-off-by: Kumar Gala

    Trent Piepho
     

21 Oct, 2008

2 commits


14 Oct, 2008

2 commits

  • The "fsl,ssi-dma-channel" compatible property is used to specify a DMA channel
    on the Freescale Elo DMA controller that should be used exclusively by the
    Freescale SSI audio controller. When a property is marked as such, the Elo
    DMA driver will ignore it, and so it will be available for the sound drivers.

    Signed-off-by: Timur Tabi
    Signed-off-by: Kumar Gala

    Timur Tabi
     
  • Modify mpc83xx_add_bridge to get config space register base address from
    the device tree instead of immr + hardcoded offset.

    83xx pci nodes have this change:
    register properties now contain two address length tuples:
    First is the pci bridge register base, this has always been there.
    Second is the config base, this is new.

    This is documented in dts-bindings/fsl/83xx-512x-pci.txt

    The changes accomplish these things:
    mpc83xx_add_bridge no longer needs to call get_immrbase
    it uses hard coded addresses if the second register value is missing

    Signed-off-by: John Rigby
    Signed-off-by: Kumar Gala

    John Rigby
     

07 Oct, 2008

2 commits


23 Sep, 2008

1 commit


18 Sep, 2008

1 commit

  • Add the fsl,playback-dma and fsl,capture-dma properties to the Freescale
    MPC8610 HPCD device tree. These properties connect the SSI nodes to the
    DMA nodes for the DMA channels that the SSI should use. Also update the
    ssi.txt documentation.

    These properties will be needed when the ASoC V2 version of the Freescale
    MPC8610 device drivers are merged into the mainline.

    Signed-off-by: Timur Tabi
    Signed-off-by: Kumar Gala

    Timur Tabi
     

04 Aug, 2008

1 commit

  • from include/asm-powerpc. This is the result of a

    mkdir arch/powerpc/include/asm
    git mv include/asm-powerpc/* arch/powerpc/include/asm

    Followed by a few documentation/comment fixups and a couple of places
    where was being used explicitly. Of the latter only
    one was outside the arch code and it is a driver only built for powerpc.

    Signed-off-by: Stephen Rothwell
    Signed-off-by: Paul Mackerras

    Stephen Rothwell
     

30 Jul, 2008

1 commit


29 Jul, 2008

1 commit

  • This file contains 8 yr. old board specific information that was for
    the now gone ppc implementation, and it pre-dates widespread u-boot
    support. Any of the technical details of the board memory map would be
    more appropriately captured in a dts if I revive it as powerpc anyway.

    Signed-off-by: Paul Gortmaker
    Acked-by: Jason Wessel
    Signed-off-by: Kumar Gala

    Paul Gortmaker
     

28 Jul, 2008

1 commit

  • This patch replaces the get_mctrl/set_mctrl stubs with modem control line
    read/write access through the GPIO lib.

    Available modem control lines are described in the device tree using GPIO
    bindings. The driver expect a GPIO pin for each of the CTS, RTS, DCD, DSR,
    DTR and RI signals. Unused control lines can be left out.

    Signed-off-by: Laurent Pinchart
    Signed-off-by: Kumar Gala

    Laurent Pinchart
     

27 Jul, 2008

1 commit


25 Jul, 2008

1 commit


22 Jul, 2008

2 commits


18 Jul, 2008

1 commit


17 Jul, 2008

5 commits


15 Jul, 2008

1 commit


14 Jul, 2008

3 commits


04 Jul, 2008

1 commit


11 Jun, 2008

1 commit


10 Jun, 2008

1 commit

  • GTM stands for General-purpose Timers Module and able to generate
    timer{1,2,3,4} interrupts. These timers are used by the drivers that
    need time precise interrupts (like for USB transactions scheduling for
    the Freescale USB Host controller as found in some QE and CPM chips),
    or these timers could be used as wakeup events from the CPU deep-sleep
    mode.

    Things unimplemented:
    1. Cascaded (32 bit) timers (1-2, 3-4).
    This is straightforward to implement when needed, two timers should
    be marked as "requested" and configured as appropriate.
    2. Super-cascaded (64 bit) timers (1-2-3-4).
    This is also straightforward to implement when needed, all timers
    should be marked as "requested" and configured as appropriate.

    Signed-off-by: Anton Vorontsov
    Signed-off-by: Kumar Gala

    Anton Vorontsov
     

03 Jun, 2008

2 commits


31 May, 2008

1 commit


02 May, 2008

1 commit

  • Various improvements for configuring the MPC5200 MII link from the
    device tree:
    * Look for 'current-speed' property for fixed speed MII links
    * Look for 'fsl,7-wire-mode' property for boards using the 7 wire mode
    * move definition of private data structure out of the header file

    Signed-off-by: Grant Likely
    Acked-by: Wolfgang Grandegger

    Grant Likely
     

29 Apr, 2008

1 commit


28 Apr, 2008

1 commit

  • The following features are supported:
    plane 0 works as a regular frame buffer, can be accessed by /dev/fb0
    plane 1 has two AOIs (area of interest), can be accessed by /dev/fb1 and /dev/fb2
    plane 2 has two AOIs, can be accessed by /dev/fb3 and /dev/fb4
    Special ioctls support AOIs

    All /dev/fb* can be used as regular frame buffer devices, except hardware
    change can only be made through /dev/fb0. Changing pixel clock has no effect
    on other fbs.

    Limitation of usage of AOIs:
    AOIs on the same plane can not be horizonally overlapped
    AOIs have horizonal order, i.e. AOI0 should be always on top of AOI1
    AOIs can not beyond phisical display area. Application should check AOI geometry
    before changing physical resolution on /dev/fb0

    required command line parameters to preallocate memory for frame buffer diufb.

    optional command line parameters to set modes and monitor
    video=fslfb:[resolution][,bpp][,monitor]
    Syntax:

    Resolution
    xres x yres-bpp@refresh_rate, the -bpp and @refresh_rate are optional
    eg, 1024x768, 1280x1024, 1280x1024-32, 1280x1024@60, 1280x1024-32@60, 1280x480-32@60

    Bpp
    bpp=32, bpp=24, or bpp=16

    Monitor
    monitor=0, monitor=1, monitor=2
    0 is DVI
    1 is Single link LVDS
    2 is Double link LVDS

    Note: switching monitor is a board feather, not DIU feather. MPC8610HPCD has three
    monitor ports to swtich to. MPC5121ADS doesn't have additional monitor port. So switching
    monirot port for MPC5121ADS has no effect.

    If compiled as a module, it takes pamameters mode, bpp, monitor with the same syntax above.

    Signed-off-by: York Sun
    Signed-off-by: Timur Tabi
    Cc: Paul Mackerras
    Cc: Benjamin Herrenschmidt
    Cc: "Antonino A. Daplas"
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    York Sun
     

27 Apr, 2008

1 commit

  • This functionality is definitely experimental, but is capable of running
    unmodified PowerPC 440 Linux kernels as guests on a PowerPC 440 host. (Only
    tested with 440EP "Bamboo" guests so far, but with appropriate userspace
    support other SoC/board combinations should work.)

    See Documentation/powerpc/kvm_440.txt for technical details.

    [stephen: build fix]

    Signed-off-by: Hollis Blanchard
    Acked-by: Paul Mackerras
    Signed-off-by: Stephen Rothwell
    Signed-off-by: Avi Kivity

    Hollis Blanchard
     

25 Apr, 2008

1 commit

  • The Xilinx 16550 uart core is not a standard 16550 because it uses
    word-based addressing rather than byte-based addressing. With
    additional properties it is compatible with the open firmware
    'ns16550' compatible binding.

    This code updates the of_serial driver to handle the reg-offset
    and reg-shift properties to enable this core to be used.

    Signed-off-by: John Linn
    Acked-by: Arnd Bergmann
    Signed-off-by: Josh Boyer

    John Linn
     

17 Apr, 2008

1 commit

  • - get rid of `model = "UCC"' in the ucc nodes
    It isn't used anywhere, so remove it. If we'll ever need something
    like this, we'll use compatible property instead.
    - replace last occurrences of device-id with cell-index.
    Drivers are modified for backward compatibility's sake.

    Signed-off-by: Anton Vorontsov
    Acked-by: Timur Tabi
    Signed-off-by: Kumar Gala

    Anton Vorontsov