Eric Lee / meta-smarcimx8m-rocko

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Commit 8da26e4982ee9584cf2dd508bb8b567502b8fcce

Authored by Eric Lee
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Exists in master and in 1 other branch smarcimx8m-rocko

Yocto rocko meta layer support for SMARC-iMX8M, initial commit

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  1 +# We have a conf and classes directory, add to BBPATH
  2 +BBPATH .= ":${LAYERDIR}"
  3 +
  4 +# We have a packages directory, add to BBFILES
  5 +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
  6 + ${LAYERDIR}/recipes-*/*/*.bbappend"
  7 +
  8 +BBFILE_COLLECTIONS += "smarcimx8m"
  9 +BBFILE_PATTERN_smarcimx8m := "^${LAYERDIR}/"
  10 +BBFILE_PRIORITY_smarcimx8m = "12"
  11 +
  12 +BBMASK += "meta-freescale/recipes-graphics/clutter/clutter-1.0_%.bbappend"
  13 +BBMASK += "meta-freescale/recipes-graphics/cogl/cogl-1.0_%.bbappend"
  14 +BBMASK += "meta-freescale/recipes-graphics/mesa/mesa-demos_%.bbappend"
  15 +BBMASK += "meta-freescale/recipes-graphics/xorg-driver/xf86-video-imxfb-vivante_5.0.11.p8.6.bb"
  16 +
  17 +HOSTTOOLS_NONFATAL_append = " sha384sum"
  18 +
  19 +EMB_UBOOT_MIRROR ?= "git://git@git.embedian.com/developer/smarc-t335x-uboot.git"
  20 +EMB_KERNEL_MIRROR ?= "git://git@git.embedian.com/developer/smarc-fsl-linux-kernel.git"
  21 +
  22 +MIRRORS += " \
  23 +${EMB_UBOOT_MIRROR} git://github.com/embedian/smarc-uboot.git;protocol=git;branch=${SRCBRANCH} \n \
  24 +${EMB_KERNEL_MIRROR} git://github.com/embedian/smarc-fsl-linux-kernel.git;protocol=git;branch=${SRCBRANCH} \n \
  25 +"
conf/machine/smarcimx8m2g.conf
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  1 +#@TYPE: Machine
  2 +#@NAME: EMBEDIAN SMARC-iMX8M COMPUTER ON MODULES with 2GB LPDDR4 MEMORY
  3 +#@SOC: i.MX8MQ
  4 +#@DESCRIPTION: Machine configuration for Embedian SMARC-iMX8M
  5 +#@MAINTAINER: Eric Lee <eric.lee@embedian.com>
  6 +
  7 +MACHINEOVERRIDES =. "mx8:mx8mq:"
  8 +MACHINEOVERRIDES =. "imx:"
  9 +
  10 +require conf/machine/include/arm/arch-arm64.inc
  11 +require conf/machine/include/imx-base.inc
  12 +
  13 +MACHINE_FEATURES += " usbgadget vfat ext2 alsa serial pci wifi bluetooth optee"
  14 +
  15 +MACHINE_SOCARCH_FILTER_append_mx8mq = "virtual/libopenvg virtual/libgles1 virtual/libgles2 virtual/egl virtual/mesa virtual/libgl virtual/libg2d"
  16 +
  17 +# Embedian BSP default providers
  18 +PREFERRED_PROVIDER_virtual/kernel_smarcimx8m2g ?= "linux-smarcimx8m"
  19 +PREFERRED_VERSION_linux-smarcimx8m_smarcimx8m2g = "4.9.88"
  20 +
  21 +KERNEL_DEVICETREE = " \
  22 + embedian/fsl-smarcimx8mq.dtb \
  23 + embedian/fsl-smarcimx8mq-dcss-lvds.dtb \
  24 + embedian/fsl-smarcimx8mq-lcdif-lvds.dtb \
  25 + embedian/fsl-smarcimx8mq-hdmi.dtb \
  26 + embedian/fsl-smarcimx8mq-hdmi-4k.dtb \
  27 + embedian/fsl-smarcimx8mq-dual-display.dtb \
  28 +"
  29 +
  30 +IMAGE_BOOTFILES_DEPENDS += "imx-m4-demos:do_deploy"
  31 +IMAGE_BOOTFILES += "imx8mq_m4_TCM_hello_world.bin imx8mq_m4_TCM_rpmsg_lite_pingpong_rtos_linux_remote.bin imx8mq_m4_TCM_rpmsg_lite_str_echo_rtos.bin"
  32 +
  33 +PREFERRED_PROVIDER_u-boot_smarcimx8m2g = "u-boot-smarcimx8m"
  34 +PREFERRED_PROVIDER_virtual/bootloader_smarcimx8m2g = "u-boot-smarcimx8m"
  35 +
  36 +UBOOT_CONFIG ??= "sd"
  37 +UBOOT_CONFIG[sd] = "smarcimx8mq_2g_ser3_defconfig,sdcard"
  38 +SPL_BINARY = "spl/u-boot-spl.bin"
  39 +
  40 +# Set DDR FIRMWARE
  41 +DDR_FIRMWARE_NAME = "lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_dmem.bin"
  42 +
  43 +# Set u-boot DTB
  44 +UBOOT_DTB_NAME = "fsl-smarcimx8mq.dtb"
  45 +
  46 +# Set imx-mkimage boot target
  47 +IMXBOOT_TARGETS = "flash_evk flash_evk_no_hdmi"
  48 +
  49 +SERIAL_CONSOLE = "115200 ttymxc0"
  50 +
  51 +IMAGE_BOOTLOADER = "imx-boot"
  52 +
  53 +BOOT_SPACE = "65536"
  54 +
  55 +LOADADDR = ""
  56 +UBOOT_SUFFIX = "bin"
  57 +UBOOT_MAKE_TARGET = ""
  58 +IMX_BOOT_SEEK = "33"
  59 +
  60 +OPTEE_BIN_EXT = "8mq"
  61 +
  62 +MACHINE_EXTRA_RDEPENDS += " \
  63 + pm-utils \
  64 + kmod \
  65 + hdparm \
  66 + gptfdisk \
  67 + lftp \
  68 + vim \
  69 + ntp \
  70 + boost \
  71 + nodejs \
  72 + networkmanager \
  73 + "
  74 +
  75 +# Packages added to all images (including core-image-minimal)
  76 +IMAGE_INSTALL_append = " \
  77 + fsl-rc-local \
  78 +"
  79 +
  80 +IMAGE_FSTYPES = "tar.bz2"
  81 +
  82 +# Ship all kernel modules by default
  83 +MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
  84 +
  85 +MACHINE_FIRMWARE_append_mx8 = " linux-firmware-ath10k"
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  1 +#
  2 +# local.conf covers user settings, site.conf covers site specific information
  3 +# such as proxy server addresses and optionally any shared download location
  4 +#
  5 +# SITE_CONF_VERSION is increased each time build/conf/site.conf
  6 +# changes incompatibly
  7 +SCONF_VERSION = "1"
  8 +
  9 +# Uncomment to cause CVS to use the proxy host specified
  10 +#CVS_PROXY_HOST = "proxy.example.com"
  11 +#CVS_PROXY_PORT = "81"
  12 +
  13 +# For svn, you need to create ~/.subversion/servers containing:
  14 +#[global]
  15 +#http-proxy-host = proxy.example.com
  16 +#http-proxy-port = 81
  17 +#
  18 +
  19 +# Uncomment to cause git to use the proxy host specificed
  20 +# although this only works for http
  21 +#GIT_PROXY_HOST = "proxy.example.com"
  22 +#GIT_PROXY_PORT = "81"
  23 +#export GIT_PROXY_COMMAND = "${COREBASE}/scripts/oe-git-proxy-command"
  24 +
  25 +# Set to yes to have a gitconfig generated for handling proxies; you
  26 +# might not want this if you have all that set in your global git
  27 +# configuration. If you don't enable it, the rest of the entries
  28 +# (_PROXY_IGNORE, etc) don't really work that well
  29 +#GIT_CORE_CONFIG = "Yes"
  30 +
  31 +# Space separate list of hosts to ignore for GIT proxy
  32 +#GIT_PROXY_IGNORE = "host.server.com another.server.com"
  33 +
  34 +# If SOCKS is available run the following command to comple a simple transport
  35 +# gcc scripts/oe-git-proxy-socks.c -o oe-git-proxy-socks
  36 +# and then share that binary somewhere in PATH, then use the following settings
  37 +#GIT_PROXY_HOST = "proxy.example.com"
  38 +#GIT_PROXY_PORT = "81"
  39 +
  40 +# GIT_PROXY_COMMAND is used by git to override all proxy settings from
  41 +# configuration files, so we prefix OE_ to avoid breaking havoc on the
  42 +# generated (or local) gitconfig's.
  43 +#OE_GIT_PROXY_COMMAND = "${COREBASE}/scripts/oe-git-proxy-socks-command"
  44 +
  45 +
  46 +# Uncomment this to use a shared download directory
  47 +#DL_DIR = "/some/shared/download/directory/"
  48 +
  49 +# Uncomment this to use shared state information.
  50 +#SSTATE_MIRRORS ?= " \
  51 +# file://.* http://www.embedian.com/oe-sstate-cache/PATH "
  52 +
  53 +PREMIRRORS_prepend = " \
  54 + svn://.*/.* http://www.embedian.com/oe-downloads/ \n \
  55 + git://.*/.* http://www.embedian.com/oe-downloads/ \n \
  56 + ftp://.*/.* http://www.embedian.com/oe-downloads/ \n \
  57 + http://.*/.* http://www.embedian.com/oe-downloads/ \n \
  58 + https://.*/.* http://www.embedian.com/oe-downloads/ \n \"
recipes-bsp/imx-atf/imx-atf/0001-ATF-support-to-different-LPDDR4-configurations.patch
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  1 +From 9d25029d24435b11c0d2222b22db1b641e7eaea0 Mon Sep 17 00:00:00 2001
  2 +From: Oliver Chen <Oliver.Chen@nxp.com>
  3 +Date: Thu, 31 May 2018 15:00:45 +0800
  4 +Subject: [PATCH] support to different LPDDR4 configurations 1. auto-detect DDR
  5 + boot frequency and backup DRAM PLL cfg 2. save/restore all necessary
  6 + DDRC/DDRPHY register to adapt to all LPDDR4 configurations
  7 +
  8 +---
  9 + plat/freescale/imx8mq/ddr/lpddr4_ddrc_cfg.c | 236 ++--
  10 + plat/freescale/imx8mq/ddr/lpddr4_dvfs.c | 17 +
  11 + plat/freescale/imx8mq/ddr/lpddr4_phy_cfg.c | 1490 +++++++++++++-------------
  12 + plat/freescale/imx8mq/ddr/lpddr4_retention.c | 6 +-
  13 + plat/freescale/imx8mq/ddr/lpddr4_swffc.c | 77 +-
  14 + plat/freescale/imx8mq/include/soc.h | 1 +
  15 + 6 files changed, 921 insertions(+), 906 deletions(-)
  16 +
  17 +diff --git a/plat/freescale/imx8mq/ddr/lpddr4_ddrc_cfg.c b/plat/freescale/imx8mq/ddr/lpddr4_ddrc_cfg.c
  18 +index a4d45bf..eb7a06c 100644
  19 +--- a/plat/freescale/imx8mq/ddr/lpddr4_ddrc_cfg.c
  20 ++++ b/plat/freescale/imx8mq/ddr/lpddr4_ddrc_cfg.c
  21 +@@ -14,133 +14,135 @@
  22 + #include <spinlock.h>
  23 + #include <soc.h>
  24 +
  25 +-#define WR_POST_EXT_3200
  26 ++struct ddrc_cfg_param {
  27 ++ uint32_t offset; /*reg offset */
  28 ++ uint32_t val; /* config param */
  29 ++};
  30 +
  31 +-static inline void umctl2_addrmap(void)
  32 +-{
  33 +- /* Address mapping */
  34 +- /* need be refined for DDR vender */
  35 +- /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
  36 +- mmio_write_32(DDRC_ADDRMAP0(0), 0x00000015);
  37 +- mmio_write_32(DDRC_ADDRMAP3(0), 0x00000000);
  38 +- mmio_write_32(DDRC_ADDRMAP4(0), 0x00001F1F);
  39 +- /* bank interleave */
  40 +- mmio_write_32(DDRC_ADDRMAP1(0), 0x00080808);
  41 +- mmio_write_32(DDRC_ADDRMAP5(0), 0x07070707);
  42 +- mmio_write_32(DDRC_ADDRMAP6(0), 0x08080707);
  43 +-}
  44 ++/* lpddr4 phy init config parameters */
  45 ++static struct ddrc_cfg_param umctl2_cfg[] = {
  46 ++ { .offset = DDRC_DBG1(0) , .val = 0x00 },
  47 ++ { .offset = DDRC_PWRCTL(0) , .val = 0x00 },
  48 ++ { .offset = DDRC_MSTR(0) , .val = 0x00 },
  49 ++ { .offset = DDRC_MSTR2(0) , .val = 0x00 },
  50 ++ { .offset = DDRC_DERATEEN(0), .val = 0x00 },
  51 ++ { .offset = DDRC_DERATEINT(0), .val = 0x00},
  52 ++ { .offset = DDRC_RFSHTMG(0), .val = 0x00 },
  53 ++ { .offset = DDRC_INIT0(0) , .val = 0x00 },
  54 ++ { .offset = DDRC_INIT1(0) , .val = 0x00 },
  55 ++ { .offset = DDRC_INIT3(0) , .val = 0x00 },
  56 ++ { .offset = DDRC_INIT4(0) , .val = 0x00 },
  57 ++ { .offset = DDRC_INIT6(0) , .val = 0x00 },
  58 ++ { .offset = DDRC_INIT7(0) , .val = 0x00 },
  59 ++ { .offset = DDRC_DRAMTMG0(0), .val = 0x00 },
  60 ++ { .offset = DDRC_DRAMTMG1(0), .val = 0x00 },
  61 ++ { .offset = DDRC_DRAMTMG3(0), .val = 0x00 },
  62 ++ { .offset = DDRC_DRAMTMG4(0), .val = 0x00 },
  63 ++ { .offset = DDRC_DRAMTMG5(0), .val = 0x00 },
  64 ++ { .offset = DDRC_DRAMTMG6(0), .val = 0x00 },
  65 ++ { .offset = DDRC_DRAMTMG7(0), .val = 0x00 },
  66 ++ { .offset = DDRC_DRAMTMG12(0), .val = 0x00 },
  67 ++ { .offset = DDRC_DRAMTMG13(0), .val = 0x00 },
  68 ++ { .offset = DDRC_DRAMTMG14(0), .val = 0x00 },
  69 ++ { .offset = DDRC_DRAMTMG17(0), .val = 0x00 },
  70 +
  71 +-static inline void umctl2_perf(void)
  72 +-{
  73 +- mmio_write_32(DDRC_ODTCFG(0), 0x0b060908);
  74 +- mmio_write_32(DDRC_ODTMAP(0), 0x00000000);
  75 +- mmio_write_32(DDRC_SCHED(0), 0x29511505);
  76 +- mmio_write_32(DDRC_SCHED1(0), 0x0000002c);
  77 +- mmio_write_32(DDRC_PERFHPR1(0), 0x5900575b);
  78 +- mmio_write_32(DDRC_PERFLPR1(0), 0x00000009);
  79 +- mmio_write_32(DDRC_PERFWR1(0), 0x02005574);
  80 +- mmio_write_32(DDRC_DBG0(0), 0x00000016);
  81 +- mmio_write_32(DDRC_DBG1(0), 0x00000000);
  82 +- mmio_write_32(DDRC_DBGCMD(0), 0x00000000);
  83 +- mmio_write_32(DDRC_SWCTL(0), 0x00000001);
  84 +- mmio_write_32(DDRC_POISONCFG(0), 0x00000011);
  85 +- mmio_write_32(DDRC_PCCFG(0), 0x00000111);
  86 +- mmio_write_32(DDRC_PCFGR_0(0), 0x000010f3);
  87 +- mmio_write_32(DDRC_PCFGW_0(0), 0x000072ff);
  88 +- mmio_write_32(DDRC_PCTRL_0(0), 0x00000001);
  89 +- mmio_write_32(DDRC_PCFGQOS0_0(0), 0x01110d00);
  90 +- mmio_write_32(DDRC_PCFGQOS1_0(0), 0x00620790);
  91 +- mmio_write_32(DDRC_PCFGWQOS0_0(0), 0x00100001);
  92 +- mmio_write_32(DDRC_PCFGWQOS1_0(0), 0x0000041f);
  93 +- mmio_write_32(DDRC_FREQ1_DERATEEN(0), 0x00000202);
  94 +- mmio_write_32(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
  95 +- mmio_write_32(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
  96 +- mmio_write_32(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
  97 +-}
  98 ++ { .offset = DDRC_ZQCTL0(0), .val = 0x00 },
  99 ++ { .offset = DDRC_ZQCTL1(0), .val = 0x00 },
  100 ++ { .offset = DDRC_ZQCTL2(0), .val = 0x00 },
  101 +
  102 +-static inline void umctl2_freq1(void)
  103 +-{
  104 +- mmio_write_32(DDRC_FREQ1_DERATEEN(0), 0x0000000);
  105 +- mmio_write_32(DDRC_FREQ1_DERATEINT(0), 0x0800000);
  106 +- mmio_write_32(DDRC_FREQ1_RFSHCTL0(0), 0x0210000);
  107 +- mmio_write_32(DDRC_FREQ1_RFSHTMG(0), 0x014001E);
  108 +- mmio_write_32(DDRC_FREQ1_INIT3(0), 0x0140009);
  109 +- mmio_write_32(DDRC_FREQ1_INIT4(0), 0x00310008);
  110 +- mmio_write_32(DDRC_FREQ1_INIT6(0), 0x0066004a);
  111 +- mmio_write_32(DDRC_FREQ1_INIT7(0), 0x0006004a);
  112 +- mmio_write_32(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07);
  113 +- mmio_write_32(DDRC_FREQ1_DRAMTMG1(0), 0x003040A);
  114 +- mmio_write_32(DDRC_FREQ1_DRAMTMG2(0), 0x305080C);
  115 +- mmio_write_32(DDRC_FREQ1_DRAMTMG3(0), 0x0505000);
  116 +- mmio_write_32(DDRC_FREQ1_DRAMTMG4(0), 0x3040203);
  117 +- mmio_write_32(DDRC_FREQ1_DRAMTMG5(0), 0x2030303);
  118 +- mmio_write_32(DDRC_FREQ1_DRAMTMG6(0), 0x2020004);
  119 +- mmio_write_32(DDRC_FREQ1_DRAMTMG7(0), 0x0000302);
  120 +- mmio_write_32(DDRC_FREQ1_DRAMTMG12(0), 0x0020310);
  121 +- mmio_write_32(DDRC_FREQ1_DRAMTMG13(0), 0xA100002);
  122 +- mmio_write_32(DDRC_FREQ1_DRAMTMG14(0), 0x0000020);
  123 +- mmio_write_32(DDRC_FREQ1_DRAMTMG17(0), 0x0220011);
  124 +- mmio_write_32(DDRC_FREQ1_ZQCTL0(0), 0x0A70005);
  125 +- mmio_write_32(DDRC_FREQ1_DFITMG0(0), 0x3858202);
  126 +- mmio_write_32(DDRC_FREQ1_DFITMG1(0), 0x0000404);
  127 +- mmio_write_32(DDRC_FREQ1_DFITMG2(0), 0x0000502);
  128 +-}
  129 ++ { .offset = DDRC_DFITMG0(0), .val = 0x00 },
  130 ++ { .offset = DDRC_DFITMG1(0), .val = 0x00 },
  131 ++ { .offset = DDRC_DFIUPD0(0), .val = 0x00 },
  132 ++ { .offset = DDRC_DFIUPD1(0), .val = 0x00 },
  133 ++ { .offset = DDRC_DFIUPD2(0), .val = 0x00 },
  134 ++ { .offset = DDRC_DFIMISC(0), .val = 0x00 },
  135 ++ { .offset = DDRC_DFITMG2(0), .val = 0x00 },
  136 +
  137 +-void lpddr4_cfg_umctl2(void)
  138 +-{
  139 +- /* Start to config, default 3200mbps */
  140 +- mmio_write_32(DDRC_DBG1(0), 0x00000001);
  141 +- mmio_write_32(DDRC_PWRCTL(0), 0x00000001);
  142 +- mmio_write_32(DDRC_MSTR(0), 0xa3080020);
  143 +- mmio_write_32(DDRC_MSTR2(0), 0x00000000);
  144 +- mmio_write_32(DDRC_RFSHTMG(0), 0x006100E0);
  145 +- mmio_write_32(DDRC_INIT0(0), 0xC003061B);
  146 +- mmio_write_32(DDRC_INIT1(0), 0x009D0000);
  147 +- mmio_write_32(DDRC_INIT3(0), 0x00D4002D);
  148 +-#ifdef WR_POST_EXT_3200 /* recommened to define */
  149 +- mmio_write_32(DDRC_INIT4(0), 0x00330008);
  150 +-#else
  151 +- mmio_write_32(DDRC_INIT4(0), 0x00310008);
  152 +-#endif
  153 +- mmio_write_32(DDRC_INIT6(0), 0x0066004a);
  154 +- mmio_write_32(DDRC_INIT7(0), 0x0006004a);
  155 ++ { .offset = DDRC_DBICTL(0), .val = 0x00 },
  156 ++ { .offset = DDRC_DFIPHYMSTR(0), .val = 0x00 },
  157 +
  158 +- mmio_write_32(DDRC_DRAMTMG0(0), 0x1A201B22);
  159 +- mmio_write_32(DDRC_DRAMTMG1(0), 0x00060633);
  160 +- mmio_write_32(DDRC_DRAMTMG3(0), 0x00C0C000);
  161 +- mmio_write_32(DDRC_DRAMTMG4(0), 0x0F04080F);
  162 +- mmio_write_32(DDRC_DRAMTMG5(0), 0x02040C0C);
  163 +- mmio_write_32(DDRC_DRAMTMG6(0), 0x01010007);
  164 +- mmio_write_32(DDRC_DRAMTMG7(0), 0x00000401);
  165 +- mmio_write_32(DDRC_DRAMTMG12(0), 0x00020600);
  166 +- mmio_write_32(DDRC_DRAMTMG13(0), 0x0C100002);
  167 +- mmio_write_32(DDRC_DRAMTMG14(0), 0x000000E6);
  168 +- mmio_write_32(DDRC_DRAMTMG17(0), 0x00A00050);
  169 ++ { .offset = DDRC_RANKCTL(0), .val = 0x00 },
  170 ++ { .offset = DDRC_DRAMTMG2(0), .val = 0x00 },
  171 +
  172 +- mmio_write_32(DDRC_ZQCTL0(0), 0x03200018);
  173 +- mmio_write_32(DDRC_ZQCTL1(0), 0x028061A8);
  174 +- mmio_write_32(DDRC_ZQCTL2(0), 0x00000000);
  175 ++ /* Address mapping */
  176 ++ { .offset = DDRC_ADDRMAP0(0), .val = 0x00 },
  177 ++ { .offset = DDRC_ADDRMAP1(0), .val = 0x00 },
  178 ++ { .offset = DDRC_ADDRMAP2(0), .val = 0x00 },
  179 ++ { .offset = DDRC_ADDRMAP3(0), .val = 0x00 },
  180 ++ { .offset = DDRC_ADDRMAP4(0), .val = 0x00 },
  181 ++ { .offset = DDRC_ADDRMAP5(0), .val = 0x00 },
  182 ++ { .offset = DDRC_ADDRMAP6(0), .val = 0x00 },
  183 +
  184 +- mmio_write_32(DDRC_DFITMG0(0), 0x0497820A);
  185 +- mmio_write_32(DDRC_DFITMG1(0), 0x00080303);
  186 +- mmio_write_32(DDRC_DFIUPD0(0), 0xE0400018);
  187 +- mmio_write_32(DDRC_DFIUPD1(0), 0x00DF00E4);
  188 +- mmio_write_32(DDRC_DFIUPD2(0), 0x80000000);
  189 +- mmio_write_32(DDRC_DFIMISC(0), 0x00000011);
  190 +- mmio_write_32(DDRC_DFITMG2(0), 0x0000170A);
  191 ++ /* performance tunning */
  192 ++ { .offset = DDRC_ODTCFG(0), .val = 0x00 },
  193 ++ { .offset = DDRC_ODTMAP(0), .val = 0x00 },
  194 ++ { .offset = DDRC_SCHED(0), .val = 0x00 },
  195 ++ { .offset = DDRC_SCHED1(0), .val = 0x00 },
  196 ++ { .offset = DDRC_PERFHPR1(0), .val = 0x00 },
  197 ++ { .offset = DDRC_PERFLPR1(0), .val = 0x00 },
  198 ++ { .offset = DDRC_PERFWR1(0), .val = 0x00 },
  199 ++ { .offset = DDRC_DBG0(0), .val = 0x00 },
  200 ++ { .offset = DDRC_DBG1(0), .val = 0x00 },
  201 ++ { .offset = DDRC_DBGCMD(0), .val = 0x00 },
  202 ++ { .offset = DDRC_SWCTL(0), .val = 0x00 },
  203 ++ { .offset = DDRC_POISONCFG(0), .val = 0x00 },
  204 ++ { .offset = DDRC_PCCFG(0), .val = 0x00 },
  205 ++ { .offset = DDRC_PCFGR_0(0), .val = 0x00 },
  206 ++ { .offset = DDRC_PCFGW_0(0), .val = 0x00 },
  207 ++ { .offset = DDRC_PCTRL_0(0), .val = 0x00 },
  208 ++ { .offset = DDRC_PCFGQOS0_0(0), .val = 0x00 },
  209 ++ { .offset = DDRC_PCFGQOS1_0(0), .val = 0x00 },
  210 ++ { .offset = DDRC_PCFGWQOS0_0(0), .val = 0x00 },
  211 ++ { .offset = DDRC_PCFGWQOS1_0(0), .val = 0x00 },
  212 +
  213 +- mmio_write_32(DDRC_DBICTL(0), 0x00000001);
  214 +- mmio_write_32(DDRC_DFIPHYMSTR(0), 0x00000001);
  215 ++ /* frequency point 1 */
  216 ++ { .offset = DDRC_FREQ1_DERATEEN(0), .val = 0x00 },
  217 ++ { .offset = DDRC_FREQ1_DERATEINT(0), .val = 0x00 },
  218 ++ { .offset = DDRC_FREQ1_RFSHCTL0(0), .val = 0x00 },
  219 ++ { .offset = DDRC_FREQ1_RFSHTMG(0), .val = 0x00 },
  220 ++ { .offset = DDRC_FREQ1_INIT3(0), .val = 0x00 },
  221 ++ { .offset = DDRC_FREQ1_INIT4(0), .val = 0x00 },
  222 ++ { .offset = DDRC_FREQ1_INIT6(0), .val = 0x00 },
  223 ++ { .offset = DDRC_FREQ1_INIT7(0), .val = 0x00 },
  224 ++ { .offset = DDRC_FREQ1_DRAMTMG0(0), .val = 0x00 },
  225 ++ { .offset = DDRC_FREQ1_DRAMTMG1(0), .val = 0x00 },
  226 ++ { .offset = DDRC_FREQ1_DRAMTMG2(0), .val = 0x00 },
  227 ++ { .offset = DDRC_FREQ1_DRAMTMG3(0), .val = 0x00 },
  228 ++ { .offset = DDRC_FREQ1_DRAMTMG4(0), .val = 0x00 },
  229 ++ { .offset = DDRC_FREQ1_DRAMTMG5(0), .val = 0x00 },
  230 ++ { .offset = DDRC_FREQ1_DRAMTMG6(0), .val = 0x00 },
  231 ++ { .offset = DDRC_FREQ1_DRAMTMG7(0), .val = 0x00 },
  232 ++ { .offset = DDRC_FREQ1_DRAMTMG12(0), .val = 0x00 },
  233 ++ { .offset = DDRC_FREQ1_DRAMTMG13(0), .val = 0x00 },
  234 ++ { .offset = DDRC_FREQ1_DRAMTMG14(0), .val = 0x00 },
  235 ++ { .offset = DDRC_FREQ1_DRAMTMG17(0), .val = 0x00 },
  236 ++ { .offset = DDRC_FREQ1_ZQCTL0(0), .val = 0x00 },
  237 ++ { .offset = DDRC_FREQ1_DFITMG0(0), .val = 0x00 },
  238 ++ { .offset = DDRC_FREQ1_DFITMG1(0), .val = 0x00 },
  239 ++ { .offset = DDRC_FREQ1_DFITMG2(0), .val = 0x00 }
  240 ++};
  241 ++
  242 ++void lpddr4_save_umctl2(void)
  243 ++{
  244 ++ int index, offset, size;
  245 +
  246 +- mmio_write_32(DDRC_RANKCTL(0), 0x00000c99);
  247 +- mmio_write_32(DDRC_DRAMTMG2(0), 0x070E171a);
  248 ++ size = sizeof(umctl2_cfg) / 8;
  249 +
  250 +- /* address mapping */
  251 +- umctl2_addrmap();
  252 ++ for (index = 0; index < size; index++) {
  253 ++ offset = umctl2_cfg[index].offset;
  254 ++ umctl2_cfg[index].val = mmio_read_32(offset);
  255 ++ }
  256 ++}
  257 ++
  258 ++void lpddr4_cfg_umctl2(void)
  259 ++{
  260 ++ int index, offset, size, val;
  261 +
  262 +- /* performance setting */
  263 +- umctl2_perf();
  264 ++ size = sizeof(umctl2_cfg) / 8;
  265 +
  266 +- /* freq set point 1 setting */
  267 +- umctl2_freq1();
  268 ++ for (index = 0; index < size; index++) {
  269 ++ offset = umctl2_cfg[index].offset;
  270 ++ val = umctl2_cfg[index].val;
  271 ++ mmio_write_32(offset,val);
  272 ++ }
  273 + }
  274 +diff --git a/plat/freescale/imx8mq/ddr/lpddr4_dvfs.c b/plat/freescale/imx8mq/ddr/lpddr4_dvfs.c
  275 +index 4cb525b..5346642 100644
  276 +--- a/plat/freescale/imx8mq/ddr/lpddr4_dvfs.c
  277 ++++ b/plat/freescale/imx8mq/ddr/lpddr4_dvfs.c
  278 +@@ -16,6 +16,7 @@
  279 +
  280 + #include "lpddr4_dvfs.h"
  281 +
  282 ++#define HW_DRAM_PLL_CFG2_ADDR (0x30360000 + 0x68)
  283 + #define DDRC_LPDDR4 (1 << 5)
  284 + #define DDR_TYPE_MASK 0x3f
  285 +
  286 +@@ -27,6 +28,12 @@ static volatile uint32_t wfe_done;
  287 + static volatile bool wait_ddrc_hwffc_done = true;
  288 +
  289 + static unsigned int init_fsp = 0x1;
  290 ++unsigned int default_ddr_pllcfg = 0;
  291 ++
  292 ++static inline int get_init_fsp(void)
  293 ++{
  294 ++ return (mmio_read_32(DDRC_DFIMISC(0))>>8)&0xf;
  295 ++}
  296 +
  297 + static inline int get_ddr_type(void)
  298 + {
  299 +@@ -35,6 +42,15 @@ static inline int get_ddr_type(void)
  300 +
  301 + void lpddr4_switch_to_3200(void)
  302 + {
  303 ++ init_fsp = get_init_fsp();
  304 ++ if(init_fsp == 0)
  305 ++ {
  306 ++ default_ddr_pllcfg = mmio_read_32(HW_DRAM_PLL_CFG2_ADDR);
  307 ++ return;
  308 ++ }
  309 ++
  310 ++ default_ddr_pllcfg = 0;
  311 ++
  312 + if (get_ddr_type() == DDRC_LPDDR4)
  313 + lpddr4_dvfs_swffc(init_fsp, 0x0);
  314 + }
  315 +@@ -98,6 +114,7 @@ int lpddr4_dvfs_handler(uint32_t smc_fid,
  316 + init_fsp = (~init_fsp) & 0x1;
  317 + #else
  318 + lpddr4_dvfs_swffc(init_fsp, target_freq);
  319 ++ init_fsp = (~init_fsp) & 0x1;
  320 + #endif
  321 + wait_ddrc_hwffc_done = false;
  322 + wfe_done = 0;
  323 +diff --git a/plat/freescale/imx8mq/ddr/lpddr4_phy_cfg.c b/plat/freescale/imx8mq/ddr/lpddr4_phy_cfg.c
  324 +index d6c57e0..ddba7f2 100644
  325 +--- a/plat/freescale/imx8mq/ddr/lpddr4_phy_cfg.c
  326 ++++ b/plat/freescale/imx8mq/ddr/lpddr4_phy_cfg.c
  327 +@@ -20,7 +20,7 @@ struct ddrphy_cfg_param {
  328 + };
  329 +
  330 + /* lpddr4 phy init config parameters */
  331 +-static const struct ddrphy_cfg_param phy_init_cfg[] = {
  332 ++static struct ddrphy_cfg_param phy_cfg[] = {
  333 + { .offset = 0x20110, .val = 0x02 }, /* MapCAB0toDFI */
  334 + { .offset = 0x20111, .val = 0x03 }, /* MapCAB1toDFI */
  335 + { .offset = 0x20112, .val = 0x04 }, /* MapCAB2toDFI */
  336 +@@ -69,6 +69,7 @@ static const struct ddrphy_cfg_param phy_init_cfg[] = {
  337 + { .offset = 0x200c5, .val = 0x19 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p0
  338 + { .offset = 0x1200c5, .val = 0x7 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p1
  339 + { .offset = 0x2200c5, .val = 0x7 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p2
  340 ++ { .offset = 0x200cb, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_PllCtrl3
  341 + { .offset = 0x2002e, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0
  342 + { .offset = 0x12002e, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1
  343 + { .offset = 0x22002e, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2
  344 +@@ -202,729 +203,738 @@ static const struct ddrphy_cfg_param phy_init_cfg[] = {
  345 + { .offset = 0x2002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p0
  346 + { .offset = 0x12002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p1
  347 + { .offset = 0x22002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p2
  348 +-};
  349 +
  350 +-/* lpddr4 phy trained CSR registers */
  351 +-static struct ddrphy_cfg_param phy_trained_csr[] = {
  352 +- { .offset = 0x200b2, .val = 0 },
  353 +- { .offset = 0x1200b2, .val = 0 },
  354 +- { .offset = 0x2200b2, .val = 0 },
  355 +- { .offset = 0x200cb, .val = 0 },
  356 +- { .offset = 0x10043, .val = 0 },
  357 +- { .offset = 0x110043, .val = 0 },
  358 +- { .offset = 0x210043, .val = 0 },
  359 +- { .offset = 0x10143, .val = 0 },
  360 +- { .offset = 0x110143, .val = 0 },
  361 +- { .offset = 0x210143, .val = 0 },
  362 +- { .offset = 0x11043, .val = 0 },
  363 +- { .offset = 0x111043, .val = 0 },
  364 +- { .offset = 0x211043, .val = 0 },
  365 +- { .offset = 0x11143, .val = 0 },
  366 +- { .offset = 0x111143, .val = 0 },
  367 +- { .offset = 0x211143, .val = 0 },
  368 +- { .offset = 0x12043, .val = 0 },
  369 +- { .offset = 0x112043, .val = 0 },
  370 +- { .offset = 0x212043, .val = 0 },
  371 +- { .offset = 0x12143, .val = 0 },
  372 +- { .offset = 0x112143, .val = 0 },
  373 +- { .offset = 0x212143, .val = 0 },
  374 +- { .offset = 0x13043, .val = 0 },
  375 +- { .offset = 0x113043, .val = 0 },
  376 +- { .offset = 0x213043, .val = 0 },
  377 +- { .offset = 0x13143, .val = 0 },
  378 +- { .offset = 0x113143, .val = 0 },
  379 +- { .offset = 0x213143, .val = 0 },
  380 +- { .offset = 0x80, .val = 0 },
  381 +- { .offset = 0x100080, .val = 0 },
  382 +- { .offset = 0x200080, .val = 0 },
  383 +- { .offset = 0x1080, .val = 0 },
  384 +- { .offset = 0x101080, .val = 0 },
  385 +- { .offset = 0x201080, .val = 0 },
  386 +- { .offset = 0x2080, .val = 0 },
  387 +- { .offset = 0x102080, .val = 0 },
  388 +- { .offset = 0x202080, .val = 0 },
  389 +- { .offset = 0x3080, .val = 0 },
  390 +- { .offset = 0x103080, .val = 0 },
  391 +- { .offset = 0x203080, .val = 0 },
  392 +- { .offset = 0x4080, .val = 0 },
  393 +- { .offset = 0x104080, .val = 0 },
  394 +- { .offset = 0x204080, .val = 0 },
  395 +- { .offset = 0x5080, .val = 0 },
  396 +- { .offset = 0x105080, .val = 0 },
  397 +- { .offset = 0x205080, .val = 0 },
  398 +- { .offset = 0x6080, .val = 0 },
  399 +- { .offset = 0x106080, .val = 0 },
  400 +- { .offset = 0x206080, .val = 0 },
  401 +- { .offset = 0x7080, .val = 0 },
  402 +- { .offset = 0x107080, .val = 0 },
  403 +- { .offset = 0x207080, .val = 0 },
  404 +- { .offset = 0x8080, .val = 0 },
  405 +- { .offset = 0x108080, .val = 0 },
  406 +- { .offset = 0x208080, .val = 0 },
  407 +- { .offset = 0x9080, .val = 0 },
  408 +- { .offset = 0x109080, .val = 0 },
  409 +- { .offset = 0x209080, .val = 0 },
  410 +- { .offset = 0x10080, .val = 0 },
  411 +- { .offset = 0x110080, .val = 0 },
  412 +- { .offset = 0x210080, .val = 0 },
  413 +- { .offset = 0x10180, .val = 0 },
  414 +- { .offset = 0x110180, .val = 0 },
  415 +- { .offset = 0x210180, .val = 0 },
  416 +- { .offset = 0x11080, .val = 0 },
  417 +- { .offset = 0x111080, .val = 0 },
  418 +- { .offset = 0x211080, .val = 0 },
  419 +- { .offset = 0x11180, .val = 0 },
  420 +- { .offset = 0x111180, .val = 0 },
  421 +- { .offset = 0x211180, .val = 0 },
  422 +- { .offset = 0x12080, .val = 0 },
  423 +- { .offset = 0x112080, .val = 0 },
  424 +- { .offset = 0x212080, .val = 0 },
  425 +- { .offset = 0x12180, .val = 0 },
  426 +- { .offset = 0x112180, .val = 0 },
  427 +- { .offset = 0x212180, .val = 0 },
  428 +- { .offset = 0x13080, .val = 0 },
  429 +- { .offset = 0x113080, .val = 0 },
  430 +- { .offset = 0x213080, .val = 0 },
  431 +- { .offset = 0x13180, .val = 0 },
  432 +- { .offset = 0x113180, .val = 0 },
  433 +- { .offset = 0x213180, .val = 0 },
  434 +- { .offset = 0x10081, .val = 0 },
  435 +- { .offset = 0x110081, .val = 0 },
  436 +- { .offset = 0x210081, .val = 0 },
  437 +- { .offset = 0x10181, .val = 0 },
  438 +- { .offset = 0x110181, .val = 0 },
  439 +- { .offset = 0x210181, .val = 0 },
  440 +- { .offset = 0x11081, .val = 0 },
  441 +- { .offset = 0x111081, .val = 0 },
  442 +- { .offset = 0x211081, .val = 0 },
  443 +- { .offset = 0x11181, .val = 0 },
  444 +- { .offset = 0x111181, .val = 0 },
  445 +- { .offset = 0x211181, .val = 0 },
  446 +- { .offset = 0x12081, .val = 0 },
  447 +- { .offset = 0x112081, .val = 0 },
  448 +- { .offset = 0x212081, .val = 0 },
  449 +- { .offset = 0x12181, .val = 0 },
  450 +- { .offset = 0x112181, .val = 0 },
  451 +- { .offset = 0x212181, .val = 0 },
  452 +- { .offset = 0x13081, .val = 0 },
  453 +- { .offset = 0x113081, .val = 0 },
  454 +- { .offset = 0x213081, .val = 0 },
  455 +- { .offset = 0x13181, .val = 0 },
  456 +- { .offset = 0x113181, .val = 0 },
  457 +- { .offset = 0x213181, .val = 0 },
  458 +- { .offset = 0x100d0, .val = 0 },
  459 +- { .offset = 0x1100d0, .val = 0 },
  460 +- { .offset = 0x2100d0, .val = 0 },
  461 +- { .offset = 0x101d0, .val = 0 },
  462 +- { .offset = 0x1101d0, .val = 0 },
  463 +- { .offset = 0x2101d0, .val = 0 },
  464 +- { .offset = 0x110d0, .val = 0 },
  465 +- { .offset = 0x1110d0, .val = 0 },
  466 +- { .offset = 0x2110d0, .val = 0 },
  467 +- { .offset = 0x111d0, .val = 0 },
  468 +- { .offset = 0x1111d0, .val = 0 },
  469 +- { .offset = 0x2111d0, .val = 0 },
  470 +- { .offset = 0x120d0, .val = 0 },
  471 +- { .offset = 0x1120d0, .val = 0 },
  472 +- { .offset = 0x2120d0, .val = 0 },
  473 +- { .offset = 0x121d0, .val = 0 },
  474 +- { .offset = 0x1121d0, .val = 0 },
  475 +- { .offset = 0x2121d0, .val = 0 },
  476 +- { .offset = 0x130d0, .val = 0 },
  477 +- { .offset = 0x1130d0, .val = 0 },
  478 +- { .offset = 0x2130d0, .val = 0 },
  479 +- { .offset = 0x131d0, .val = 0 },
  480 +- { .offset = 0x1131d0, .val = 0 },
  481 +- { .offset = 0x2131d0, .val = 0 },
  482 +- { .offset = 0x100d1, .val = 0 },
  483 +- { .offset = 0x1100d1, .val = 0 },
  484 +- { .offset = 0x2100d1, .val = 0 },
  485 +- { .offset = 0x101d1, .val = 0 },
  486 +- { .offset = 0x1101d1, .val = 0 },
  487 +- { .offset = 0x2101d1, .val = 0 },
  488 +- { .offset = 0x110d1, .val = 0 },
  489 +- { .offset = 0x1110d1, .val = 0 },
  490 +- { .offset = 0x2110d1, .val = 0 },
  491 +- { .offset = 0x111d1, .val = 0 },
  492 +- { .offset = 0x1111d1, .val = 0 },
  493 +- { .offset = 0x2111d1, .val = 0 },
  494 +- { .offset = 0x120d1, .val = 0 },
  495 +- { .offset = 0x1120d1, .val = 0 },
  496 +- { .offset = 0x2120d1, .val = 0 },
  497 +- { .offset = 0x121d1, .val = 0 },
  498 +- { .offset = 0x1121d1, .val = 0 },
  499 +- { .offset = 0x2121d1, .val = 0 },
  500 +- { .offset = 0x130d1, .val = 0 },
  501 +- { .offset = 0x1130d1, .val = 0 },
  502 +- { .offset = 0x2130d1, .val = 0 },
  503 +- { .offset = 0x131d1, .val = 0 },
  504 +- { .offset = 0x1131d1, .val = 0 },
  505 +- { .offset = 0x2131d1, .val = 0 },
  506 +- { .offset = 0x10068, .val = 0 },
  507 +- { .offset = 0x10168, .val = 0 },
  508 +- { .offset = 0x10268, .val = 0 },
  509 +- { .offset = 0x10368, .val = 0 },
  510 +- { .offset = 0x10468, .val = 0 },
  511 +- { .offset = 0x10568, .val = 0 },
  512 +- { .offset = 0x10668, .val = 0 },
  513 +- { .offset = 0x10768, .val = 0 },
  514 +- { .offset = 0x10868, .val = 0 },
  515 +- { .offset = 0x11068, .val = 0 },
  516 +- { .offset = 0x11168, .val = 0 },
  517 +- { .offset = 0x11268, .val = 0 },
  518 +- { .offset = 0x11368, .val = 0 },
  519 +- { .offset = 0x11468, .val = 0 },
  520 +- { .offset = 0x11568, .val = 0 },
  521 +- { .offset = 0x11668, .val = 0 },
  522 +- { .offset = 0x11768, .val = 0 },
  523 +- { .offset = 0x11868, .val = 0 },
  524 +- { .offset = 0x12068, .val = 0 },
  525 +- { .offset = 0x12168, .val = 0 },
  526 +- { .offset = 0x12268, .val = 0 },
  527 +- { .offset = 0x12368, .val = 0 },
  528 +- { .offset = 0x12468, .val = 0 },
  529 +- { .offset = 0x12568, .val = 0 },
  530 +- { .offset = 0x12668, .val = 0 },
  531 +- { .offset = 0x12768, .val = 0 },
  532 +- { .offset = 0x12868, .val = 0 },
  533 +- { .offset = 0x13068, .val = 0 },
  534 +- { .offset = 0x13168, .val = 0 },
  535 +- { .offset = 0x13268, .val = 0 },
  536 +- { .offset = 0x13368, .val = 0 },
  537 +- { .offset = 0x13468, .val = 0 },
  538 +- { .offset = 0x13568, .val = 0 },
  539 +- { .offset = 0x13668, .val = 0 },
  540 +- { .offset = 0x13768, .val = 0 },
  541 +- { .offset = 0x13868, .val = 0 },
  542 +- { .offset = 0x10069, .val = 0 },
  543 +- { .offset = 0x10169, .val = 0 },
  544 +- { .offset = 0x10269, .val = 0 },
  545 +- { .offset = 0x10369, .val = 0 },
  546 +- { .offset = 0x10469, .val = 0 },
  547 +- { .offset = 0x10569, .val = 0 },
  548 +- { .offset = 0x10669, .val = 0 },
  549 +- { .offset = 0x10769, .val = 0 },
  550 +- { .offset = 0x10869, .val = 0 },
  551 +- { .offset = 0x11069, .val = 0 },
  552 +- { .offset = 0x11169, .val = 0 },
  553 +- { .offset = 0x11269, .val = 0 },
  554 +- { .offset = 0x11369, .val = 0 },
  555 +- { .offset = 0x11469, .val = 0 },
  556 +- { .offset = 0x11569, .val = 0 },
  557 +- { .offset = 0x11669, .val = 0 },
  558 +- { .offset = 0x11769, .val = 0 },
  559 +- { .offset = 0x11869, .val = 0 },
  560 +- { .offset = 0x12069, .val = 0 },
  561 +- { .offset = 0x12169, .val = 0 },
  562 +- { .offset = 0x12269, .val = 0 },
  563 +- { .offset = 0x12369, .val = 0 },
  564 +- { .offset = 0x12469, .val = 0 },
  565 +- { .offset = 0x12569, .val = 0 },
  566 +- { .offset = 0x12669, .val = 0 },
  567 +- { .offset = 0x12769, .val = 0 },
  568 +- { .offset = 0x12869, .val = 0 },
  569 +- { .offset = 0x13069, .val = 0 },
  570 +- { .offset = 0x13169, .val = 0 },
  571 +- { .offset = 0x13269, .val = 0 },
  572 +- { .offset = 0x13369, .val = 0 },
  573 +- { .offset = 0x13469, .val = 0 },
  574 +- { .offset = 0x13569, .val = 0 },
  575 +- { .offset = 0x13669, .val = 0 },
  576 +- { .offset = 0x13769, .val = 0 },
  577 +- { .offset = 0x13869, .val = 0 },
  578 +- { .offset = 0x1008c, .val = 0 },
  579 +- { .offset = 0x11008c, .val = 0 },
  580 +- { .offset = 0x21008c, .val = 0 },
  581 +- { .offset = 0x1018c, .val = 0 },
  582 +- { .offset = 0x11018c, .val = 0 },
  583 +- { .offset = 0x21018c, .val = 0 },
  584 +- { .offset = 0x1108c, .val = 0 },
  585 +- { .offset = 0x11108c, .val = 0 },
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