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arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
45.6 KB
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/*
* Copyright 2017 NXP
* Copyright 2018-2019 Variscite Ltd.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "../freescale/fsl-imx8mq.dtsi"
/ {
firmware {
android {
compatible = "android,firmware";
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
/* sd card node which used if androidboot.storage_type=sd */
dev_sd = "/dev/block/platform/30b50000.usdhc/by-name/vendor";
/* emmc node which used if androidboot.storage_type=emmc */
dev_emmc = "/dev/block/platform/30b40000.usdhc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,slotselect,avb";
};
};
vbmeta {
/*we need use FirstStageMountVBootV2 if we enable avb*/
compatible = "android,vbmeta";
/*parts means the partition witch can be mount in first stage*/
parts = "vbmeta,boot,system,vendor";
};
};
};
};
/ {
compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay = <20000>;
enable-active-high;
};
reg_audio: audio_vdd {
compatible = "regulator-fixed";
regulator-name = "sgtl5000_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: 5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_1p8v: 1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_gpio_dvfs: regulator-gpio {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dvfs>;
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regulator-min-microvolt = <900000>; |
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regulator-max-microvolt = <1000000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
states = <900000 0x1 1000000 0x0>;
};
};
sound-sgtl5000 {
compatible = "fsl,imx-audio-sgtl5000",
"smarc,imx8mq-audio-sgtl5000";
model = "imx8mq-audio-sgtl5000";
ssi-controller = <&sai2>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
fsl,no-audmux;
};
sound-hdmi {
compatible = "fsl,imx8mq-evk-cdnhdmi",
"fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
protocol = <1>;
hdmi-out;
constraint-rate = <44100>,
<88200>,
<176400>,
<32000>,
<48000>,
<96000>,
<192000>;
status = "disabled";
};
sound-hdmi-arc {
compatible = "fsl,imx-audio-spdif";
model = "imx-hdmi-arc";
spdif-controller = <&spdif2>;
spdif-in;
status = "disabled";
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio4 0 0>; /* Backlight Enable */
pwms = <&pwm1 0 1000000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
status = "disabled";
};
/* external oscillator of mcp2515 on SPI1.0 and SPI1.1 */
can_osc: can_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
smarcimx8mq {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /*RESET_OUT#*/
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MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 /*FEC_IRQ#*/
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x41 /*PCIE_WAKE#*/
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*SLEEP#*/
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MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41 /*CHARGING#*/ |
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MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 /*CHARGER_PRSNT#*/ |
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MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /*CARRIER_STBY#*/ |
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MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 /*BATLOW#*/ |
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MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x41 /*USB0_EN_OC#*/ |
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MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x41 /*USB2_EN_OC#*/
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x41 /*USB3_EN_OC#*/
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /*GPIO0*/
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /*GPIO2*/
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
>;
};
pinctrl_csi2: csi2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /*GPIO1*/
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*GPIO3*/
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
>;
};
pinctrl_dvfs: dvfsgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
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MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 |
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>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
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MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 |
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MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_sai1_pcm: sai1grp_pcm {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai1_dsd: sai1grp_dsd {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x16
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x16
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x16
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x16
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x16
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
>;
};
pinctrl_lvds: lvdsgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x16
>;
};
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|
546 547 548 549 550 551 |
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0xc1
>;
};
|
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|
552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 |
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <6>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
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662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 |
};
};
};
s35390a: s35390a@30 {
compatible = "s35390a";
reg = <0x30>;
};
cape_eeprom0: cape_eeprom@57 {
compatible = "at,24c256";
reg = <0x57>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
clock-names = "mclk";
VDDA-supply = <®_audio>;
VDDIO-supply = <®_1p8v>;
status = "okay";
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
dsi_lvds_bridge: sn65dsi84@2c {
status = "disabled";
reg = <0x2c>;
compatible = "ti,sn65dsi84";
|
|
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|
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enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; |
|
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|
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interrupt-parent = <&gpio4>; |
|
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|
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interrupts = <29 IRQ_TYPE_EDGE_FALLING>; |
|
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|
700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 |
/* AUO G070VW01 7-inch 800x480 LVDS Display */
sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;
/* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
/* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
|
|
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|
732 |
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 |
|
81f7e3824
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|
733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 |
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
};
ov5640_mipi: ov5640_mipi@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <20000000>;
csi_id = <0>;
pwn-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /*GPIO0*/
rst-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; /*GPIO2*/
mclk = <20000000>;
mclk_source = <0>;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
ov5640_mipi2: ov5640_mipi2@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi2>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <20000000>;
csi_id = <1>;
pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /*GPIO1*/
rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; /*GPIO3*/
mclk = <20000000>;
mclk_source = <0>;
port {
ov5640_mipi2_ep: endpoint {
remote-endpoint = <&mipi2_sensor_ep>;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "okay";
};
/* SER3 */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
/* SER2 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
|
|
36535f77a
Make changes for ...
|
843 |
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; |
|
81f7e3824
Initial Release, ...
|
844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 |
fsl,uart-has-rtscts;
status = "okay";
};
/* SER1 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
/* SER0 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
|
|
455791eed
Change USB0 from ...
|
903 |
dr_mode = "peripheral"; |
|
81f7e3824
Initial Release, ...
|
904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 |
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai4 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};
&spdif2 {
assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&gpu_pd {
power-supply = <&sw1a_reg>;
};
&vpu_pd {
power-supply = <&sw1c_reg>;
};
&gpu {
|
|
81f7e3824
Initial Release, ...
|
965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 |
status = "okay";
};
&vpu {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&mu {
status = "okay";
};
|
|
1e6655478
Fix Support for L...
|
982 983 984 985 986 987 988 989 990 |
&resmem {
/* cma region is provided by kernel command line as cma=<size>M */
/delete-node/ linux,cma;
/delete-node/ rpmsg@0x98000000;
rpmsg_reserved: rpmsg@0x40000000 {
no-map;
reg = <0 0x40000000 0 0x400000>;
};
|
|
81f7e3824
Initial Release, ...
|
991 992 993 994 995 996 997 998 999 1000 |
};
&A53_0 {
operating-points = <
/* kHz uV */
1500000 1000000
1300000 1000000
1000000 900000
800000 900000
>;
|
|
81f7e3824
Initial Release, ...
|
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 |
};
/* Data for energy-aware-scheduling */
/{
cpus {
energy-costs {
CPU_COST_A53: core-cost-a53 {
busy-cost-data = <
546 1017
682 1272
887 2041
1024 2356
>;
idle-cost-data = <
94
94
0
>;
};
CLUSTER_COST_A53: cluster-cost-a53 {
busy-cost-data = <
546 1017
682 1272
887 2041
1024 3095
>;
idle-cost-data = <
1037
1037
1037
>;
};
};
};
};
&A53_0 {
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
&A53_1 {
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
&A53_2 {
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
&A53_3 {
sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&csi2_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <1 2>;
};
csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};
&mipi_csi_2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi2_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi2_ep>;
data-lanes = <1 2 3 4>;
};
csi2_mipi_ep: endpoint2 {
remote-endpoint = <&csi2_ep>;
};
};
};
|
|
81f7e3824
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|
1105 1106 |
&mipi_dsi_bridge {
status = "disabled";
|
|
1e6655478
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|
1107 |
panel@0 {
|
|
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|
1108 1109 1110 1111 1112 1113 1114 |
reg = <0>;
status = "okay";
/* AUO G070VW01 800x480 LVDS Display */
compatible = "auo,g070vw01";
/* AUO G185XW01 1366x768 LVDS Display */
/*compatible = "auo,g185xw01";*/
/* AUO G240HW01 1920x1080 LVDS Display */
|
|
1e6655478
Fix Support for L...
|
1115 1116 1117 1118 |
/*compatible = "auo,g240hw01";*/
backlight = <&backlight>;
enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
dsi-lanes = <4>;
|
|
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Initial Release, ...
|
1119 1120 1121 1122 |
/* AUO G070VW01 800x480 LVDS Display */
panel-width-mm = <152>;
panel-height-mm = <91>;
/* AUO G185XW01 1366x768 LVDS Display */
|
|
1e6655478
Fix Support for L...
|
1123 |
/*panel-width-mm = <410>; |
|
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|
1124 1125 |
panel-height-mm = <230>;*/
/* AUO G240HW01 1920x1080 LVDS Display */
|
|
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|
1126 |
/*panel-width-mm = <531>; |
|
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|
1127 |
panel-height-mm = <299>;*/ |
|
1e6655478
Fix Support for L...
|
1128 |
delay,prepare = <120>; |
|
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|
1129 |
|
|
1e6655478
Fix Support for L...
|
1130 |
port {
|
|
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|
1131 1132 1133 1134 |
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
|
|
1e6655478
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|
1135 |
}; |
|
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|
1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 |
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 0>, <&gpio1 0 0>, <&gpio3 15 0>, <&gpio3 17 0>;
fsl,spi-num-chipselects = <4>;
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
spi-max-frequency = <24000000>;
};
can1: can@2 {
compatible = "microchip,mcp2515";
reg = <2>;
|
|
1e6655478
Fix Support for L...
|
1168 1169 |
interrupt-parent = <&gpio3>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
|
079674164
Change SPI CAN bu...
|
1170 |
spi-max-frequency = <12000000>; |
|
81f7e3824
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|
1171 |
clocks = <&can_osc>; |
|
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|
1172 1173 1174 1175 1176 1177 1178 |
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
};
can2: can@3 {
compatible = "microchip,mcp2515";
reg = <3>;
|
|
1e6655478
Fix Support for L...
|
1179 1180 |
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
|
|
079674164
Change SPI CAN bu...
|
1181 |
spi-max-frequency = <12000000>; |
|
81f7e3824
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|
1182 |
clocks = <&can_osc>; |
|
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|
1183 1184 1185 1186 1187 1188 1189 1190 1191 |
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
|
|
1e6655478
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|
1192 1193 1194 |
&snvs_rtc {
status = "disabled";
};
|
|
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|
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 |
&crypto {
status = "disabled";
};
&resmem {
carveout_region: imx_ion@0 {
compatible = "imx-ion-pool";
reg = <0x0 0xf8000000 0 0x8000000>;
};
};
|