commit 02b4e2756e01c623cc4dbceae4b07be75252db5b upstream.

All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: Florian Fainelli
Tested-by: Florian Fainelli
Tested-by: Heiko Stuebner
Tested-by: Dinh Nguyen
Acked-by: Sebastian Hesselbarth
Tested-by: Sebastian Hesselbarth
Acked-by: Shawn Guo
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Tested-by: Geert Uytterhoeven
Tested-by: Michal Simek
Tested-by: Wei Xu
Signed-off-by: Russell King
Cc: Alexander Kochetkov
Signed-off-by: Greg Kroah-Hartman