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Commit b82727ec646578bdd3a6f31f6451f67784874675

Authored by Thomas Gleixner
1 parent efa63c6495
Exists in master and in 39 other branches 8mp-imx_5.4.70_2.3.0, 8qm-imx_5.4.70_2.3.0, emb_imx_lf-5.15.y, emb_lf-6.1.y, imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, imx_4.1.15_1.0.0_ga, pitx_8mp_lf-5.10.y, rt-smarc-imx_4.1.15_1.0.0_ga, rt_linux_5.15.71, smarc-8m-android-11.0.0_2.0.0, smarc-imx6_4.14.98_2.0.0_ga, smarc-imx6_4.9.88_2.0.0_ga, smarc-imx7_4.14.98_2.0.0_ga, smarc-imx7_4.9.11_1.0.0_ga, smarc-imx7_4.9.88_2.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-imx_4.1.15_1.0.0_ga, smarc-imx_4.9.11_1.0.0_ga, smarc-imx_4.9.51_imx8m_ga, smarc-imx_4.9.88_2.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_1.2.0_ga, smarc_8m_00d0_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.14.78_1.0.0_ga, smarc_8m_imx_4.14.98_2.0.0_ga, smarc_8m_imx_4.19.35_1.1.0, smarc_8mm_imx_4.14.78_1.0.0_ga, smarc_8mm_imx_4.14.98_2.0.0_ga, smarc_8mm_imx_4.19.35_1.1.0, smarc_8mm_imx_5.4.24_2.1.0, smarc_8mp_lf-5.10.y, smarc_8mq_imx_5.4.24_2.1.0, smarc_8mq_lf-5.10.y, smarc_imx_lf-5.15.y

m32r: Convert mappi3 irq chip 

Convert the irq chips to the new functions and use proper flow
handlers. handle_level_irq is appropriate.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>

Showing 1 changed file with 31 additions and 31 deletions Inline Diff

arch/m32r/platforms/mappi3/setup.c
Diff comments   View file @ b82727e
1 /* 1 /*
2 * linux/arch/m32r/platforms/mappi3/setup.c 2 * linux/arch/m32r/platforms/mappi3/setup.c
3 * 3 *
4 * Setup routines for Renesas MAPPI-III(M3A-2170) Board 4 * Setup routines for Renesas MAPPI-III(M3A-2170) Board
5 * 5 *
6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, 6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10 #include <linux/irq.h> 10 #include <linux/irq.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/init.h> 12 #include <linux/init.h>
13 #include <linux/platform_device.h> 13 #include <linux/platform_device.h>
14 14
15 #include <asm/system.h> 15 #include <asm/system.h>
16 #include <asm/m32r.h> 16 #include <asm/m32r.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 18
19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) 19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
20 20
21 icu_data_t icu_data[NR_IRQS]; 21 icu_data_t icu_data[NR_IRQS];
22 22
23 static void disable_mappi3_irq(unsigned int irq) 23 static void disable_mappi3_irq(unsigned int irq)
24 { 24 {
25 unsigned long port, data; 25 unsigned long port, data;
26 26
27 if ((irq == 0) ||(irq >= NR_IRQS)) { 27 if ((irq == 0) ||(irq >= NR_IRQS)) {
28 printk("bad irq 0x%08x\n", irq); 28 printk("bad irq 0x%08x\n", irq);
29 return; 29 return;
30 } 30 }
31 port = irq2port(irq); 31 port = irq2port(irq);
32 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; 32 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
33 outl(data, port); 33 outl(data, port);
34 } 34 }
35 35
36 static void enable_mappi3_irq(unsigned int irq) 36 static void enable_mappi3_irq(unsigned int irq)
37 { 37 {
38 unsigned long port, data; 38 unsigned long port, data;
39 39
40 if ((irq == 0) ||(irq >= NR_IRQS)) { 40 if ((irq == 0) ||(irq >= NR_IRQS)) {
41 printk("bad irq 0x%08x\n", irq); 41 printk("bad irq 0x%08x\n", irq);
42 return; 42 return;
43 } 43 }
44 port = irq2port(irq); 44 port = irq2port(irq);
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; 45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
46 outl(data, port); 46 outl(data, port);
47 } 47 }
48 48
49 static void mask_and_ack_mappi3(unsigned int irq) 49 static void mask_mappi3(struct irq_data *data)
50 { 50 {
51 disable_mappi3_irq(irq); 51 disable_mappi3_irq(data->irq);
52 } 52 }
53 53
54 static void end_mappi3_irq(unsigned int irq) 54 static void unmask_mappi3(struct irq_data *data)
55 { 55 {
56 enable_mappi3_irq(irq); 56 enable_mappi3_irq(data->irq);
57 } 57 }
58 58
59 static unsigned int startup_mappi3_irq(unsigned int irq) 59 static void shutdown_mappi3(struct irq_data *data)
60 { 60 {
61 enable_mappi3_irq(irq);
62 return (0);
63 }
64
65 static void shutdown_mappi3_irq(unsigned int irq)
66 {
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71 } 65 }
72 66
73 static struct irq_chip mappi3_irq_type = 67 static struct irq_chip mappi3_irq_type = {
74 { 68 .name = "MAPPI3-IRQ",
75 .name = "MAPPI3-IRQ", 69 .irq_shutdown = shutdown_mappi3,
76 .startup = startup_mappi3_irq, 70 .irq_mask = mask_mappi3,
77 .shutdown = shutdown_mappi3_irq, 71 .irq_unmask = unmask_mappi3,
78 .enable = enable_mappi3_irq,
79 .disable = disable_mappi3_irq,
80 .ack = mask_and_ack_mappi3,
81 .end = end_mappi3_irq
82 }; 72 };
83 73
84 void __init init_IRQ(void) 74 void __init init_IRQ(void)
85 { 75 {
86 #if defined(CONFIG_SMC91X) 76 #if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
88 set_irq_chip(M32R_IRQ_INT0, &mappi3_irq_type); 78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
79 handle_level_irq);
89 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
90 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
91 #endif /* CONFIG_SMC91X */ 82 #endif /* CONFIG_SMC91X */
92 83
93 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
94 set_irq_chip(M32R_IRQ_MFT2, &mappi3_irq_type); 85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
86 handle_level_irq);
95 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
96 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
97 89
98 #ifdef CONFIG_SERIAL_M32R_SIO 90 #ifdef CONFIG_SERIAL_M32R_SIO
99 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
100 set_irq_chip(M32R_IRQ_SIO0_R, &mappi3_irq_type); 92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
93 handle_level_irq);
101 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
102 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
103 96
104 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
105 set_irq_chip(M32R_IRQ_SIO0_S, &mappi3_irq_type); 98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
99 handle_level_irq);
106 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
107 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
108 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
109 set_irq_chip(M32R_IRQ_SIO1_R, &mappi3_irq_type); 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
104 handle_level_irq);
110 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
111 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
112 107
113 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
114 set_irq_chip(M32R_IRQ_SIO1_S, &mappi3_irq_type); 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
110 handle_level_irq);
115 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
116 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
117 #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 113 #endif /* CONFIG_M32R_USE_DBG_CONSOLE */
118 114
119 #if defined(CONFIG_USB) 115 #if defined(CONFIG_USB)
120 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
121 set_irq_chip(M32R_IRQ_INT1, &mappi3_irq_type); 117 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
118 handle_level_irq);
122 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
123 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
124 #endif /* CONFIG_USB */ 121 #endif /* CONFIG_USB */
125 122
126 /* CFC IREQ */ 123 /* CFC IREQ */
127 set_irq_chip(PLD_IRQ_CFIREQ, &mappi3_irq_type); 124 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
125 handle_level_irq);
128 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
129 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
130 128
131 #if defined(CONFIG_M32R_CFC) 129 #if defined(CONFIG_M32R_CFC)
132 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
133 set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi3_irq_type); 131 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
132 handle_level_irq);
134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
135 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
136 135
137 #endif /* CONFIG_M32R_CFC */ 136 #endif /* CONFIG_M32R_CFC */
138 137
139 /* IDE IREQ */ 138 /* IDE IREQ */
140 set_irq_chip(PLD_IRQ_IDEIREQ, &mappi3_irq_type); 139 set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
140 handle_level_irq);
141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
142 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
143 143
144 } 144 }
145 145
146 #if defined(CONFIG_SMC91X) 146 #if defined(CONFIG_SMC91X)
147 147
148 #define LAN_IOSTART 0x300 148 #define LAN_IOSTART 0x300
149 #define LAN_IOEND 0x320 149 #define LAN_IOEND 0x320
150 static struct resource smc91x_resources[] = { 150 static struct resource smc91x_resources[] = {
151 [0] = { 151 [0] = {
152 .start = (LAN_IOSTART), 152 .start = (LAN_IOSTART),
153 .end = (LAN_IOEND), 153 .end = (LAN_IOEND),
154 .flags = IORESOURCE_MEM, 154 .flags = IORESOURCE_MEM,
155 }, 155 },
156 [1] = { 156 [1] = {
157 .start = M32R_IRQ_INT0, 157 .start = M32R_IRQ_INT0,
158 .end = M32R_IRQ_INT0, 158 .end = M32R_IRQ_INT0,
159 .flags = IORESOURCE_IRQ, 159 .flags = IORESOURCE_IRQ,
160 } 160 }
161 }; 161 };
162 162
163 static struct platform_device smc91x_device = { 163 static struct platform_device smc91x_device = {
164 .name = "smc91x", 164 .name = "smc91x",
165 .id = 0, 165 .id = 0,
166 .num_resources = ARRAY_SIZE(smc91x_resources), 166 .num_resources = ARRAY_SIZE(smc91x_resources),
167 .resource = smc91x_resources, 167 .resource = smc91x_resources,
168 }; 168 };
169 169
170 #endif 170 #endif
171 171
172 #if defined(CONFIG_FB_S1D13XXX) 172 #if defined(CONFIG_FB_S1D13XXX)
173 173
174 #include <video/s1d13xxxfb.h> 174 #include <video/s1d13xxxfb.h>
175 #include <asm/s1d13806.h> 175 #include <asm/s1d13806.h>
176 176
177 static struct s1d13xxxfb_pdata s1d13xxxfb_data = { 177 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
178 .initregs = s1d13xxxfb_initregs, 178 .initregs = s1d13xxxfb_initregs,
179 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), 179 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
180 .platform_init_video = NULL, 180 .platform_init_video = NULL,
181 #ifdef CONFIG_PM 181 #ifdef CONFIG_PM
182 .platform_suspend_video = NULL, 182 .platform_suspend_video = NULL,
183 .platform_resume_video = NULL, 183 .platform_resume_video = NULL,
184 #endif 184 #endif
185 }; 185 };
186 186
187 static struct resource s1d13xxxfb_resources[] = { 187 static struct resource s1d13xxxfb_resources[] = {
188 [0] = { 188 [0] = {
189 .start = 0x1d600000UL, 189 .start = 0x1d600000UL,
190 .end = 0x1d73FFFFUL, 190 .end = 0x1d73FFFFUL,
191 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
192 }, 192 },
193 [1] = { 193 [1] = {
194 .start = 0x1d400000UL, 194 .start = 0x1d400000UL,
195 .end = 0x1d4001FFUL, 195 .end = 0x1d4001FFUL,
196 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
197 } 197 }
198 }; 198 };
199 199
200 static struct platform_device s1d13xxxfb_device = { 200 static struct platform_device s1d13xxxfb_device = {
201 .name = S1D_DEVICENAME, 201 .name = S1D_DEVICENAME,
202 .id = 0, 202 .id = 0,
203 .dev = { 203 .dev = {
204 .platform_data = &s1d13xxxfb_data, 204 .platform_data = &s1d13xxxfb_data,
205 }, 205 },
206 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), 206 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
207 .resource = s1d13xxxfb_resources, 207 .resource = s1d13xxxfb_resources,
208 }; 208 };
209 #endif 209 #endif
210 210
211 static int __init platform_init(void) 211 static int __init platform_init(void)
212 { 212 {