Commit cdc56c112932a058f86e6ed9e2cd696ffafac8c2
Committed by
Tony Lindgren
Tony Lindgren
1 parent
df4f3459c7
bus: ti-sysc: avoid toggling power state of module during probe
Current implementation for ti-sysc powers down the module once module init is complete. However, right after power is disabled, it is enabled via runtime PM. This is unnecessary so avoid it by re-ordering the events a bit; move powering down of the module post runtime PM enable which makes sure the use counts are maintained properly and there is no extra power down/up sequence for the module. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Showing 1 changed file with 18 additions and 12 deletions Side-by-side Diff
drivers/bus/ti-sysc.c
| ... | ... | @@ -1584,12 +1584,7 @@ |
| 1584 | 1584 | static int sysc_init_module(struct sysc *ddata) |
| 1585 | 1585 | { |
| 1586 | 1586 | int error = 0; |
| 1587 | - bool manage_clocks = true; | |
| 1588 | 1587 | |
| 1589 | - if (ddata->cfg.quirks & | |
| 1590 | - (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) | |
| 1591 | - manage_clocks = false; | |
| 1592 | - | |
| 1593 | 1588 | error = sysc_clockdomain_init(ddata); |
| 1594 | 1589 | if (error) |
| 1595 | 1590 | return error; |
| 1596 | 1591 | |
| 1597 | 1592 | |
| 1598 | 1593 | |
| 1599 | 1594 | |
| 1600 | 1595 | |
| ... | ... | @@ -1621,28 +1616,32 @@ |
| 1621 | 1616 | if (ddata->legacy_mode) { |
| 1622 | 1617 | error = sysc_legacy_init(ddata); |
| 1623 | 1618 | if (error) |
| 1624 | - goto err_main_clocks; | |
| 1619 | + goto err_reset; | |
| 1625 | 1620 | } |
| 1626 | 1621 | |
| 1627 | 1622 | if (!ddata->legacy_mode) { |
| 1628 | 1623 | error = sysc_enable_module(ddata->dev); |
| 1629 | 1624 | if (error) |
| 1630 | - goto err_main_clocks; | |
| 1625 | + goto err_reset; | |
| 1631 | 1626 | } |
| 1632 | 1627 | |
| 1633 | 1628 | error = sysc_reset(ddata); |
| 1634 | 1629 | if (error) |
| 1635 | 1630 | dev_err(ddata->dev, "Reset failed with %d\n", error); |
| 1636 | 1631 | |
| 1637 | - if (!ddata->legacy_mode && manage_clocks) | |
| 1632 | + if (error && !ddata->legacy_mode) | |
| 1638 | 1633 | sysc_disable_module(ddata->dev); |
| 1639 | 1634 | |
| 1635 | +err_reset: | |
| 1636 | + if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
| 1637 | + reset_control_assert(ddata->rsts); | |
| 1638 | + | |
| 1640 | 1639 | err_main_clocks: |
| 1641 | - if (manage_clocks) | |
| 1640 | + if (error) | |
| 1642 | 1641 | sysc_disable_main_clocks(ddata); |
| 1643 | 1642 | err_opt_clocks: |
| 1644 | 1643 | /* No re-enable of clockdomain autoidle to prevent module autoidle */ |
| 1645 | - if (manage_clocks) { | |
| 1644 | + if (error) { | |
| 1646 | 1645 | sysc_disable_opt_clocks(ddata); |
| 1647 | 1646 | sysc_clkdm_allow_idle(ddata); |
| 1648 | 1647 | } |
| 1649 | 1648 | |
| ... | ... | @@ -2415,9 +2414,16 @@ |
| 2415 | 2414 | goto unprepare; |
| 2416 | 2415 | } |
| 2417 | 2416 | |
| 2418 | - /* Balance reset counts */ | |
| 2419 | - if (ddata->rsts) | |
| 2417 | + /* Balance use counts as PM runtime should have enabled these all */ | |
| 2418 | + if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
| 2420 | 2419 | reset_control_assert(ddata->rsts); |
| 2420 | + | |
| 2421 | + if (!(ddata->cfg.quirks & | |
| 2422 | + (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { | |
| 2423 | + sysc_disable_main_clocks(ddata); | |
| 2424 | + sysc_disable_opt_clocks(ddata); | |
| 2425 | + sysc_clkdm_allow_idle(ddata); | |
| 2426 | + } | |
| 2421 | 2427 | |
| 2422 | 2428 | sysc_show_registers(ddata); |
| 2423 | 2429 |