20 Nov, 2020
9 commits
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The blk-ctl register allow access to set the MIPI DSI LDO trim value.
Signed-off-by: Oliver Brown
Reviewed-by: Laurentiu Palcu -
Enable ADC monomix for fixing only one channel in recording
Signed-off-by: Shengjiu Wang
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Enable support for Hifiberry dacplus audio hats on
iMX8MMini EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit ec6d8970ba79fc7cef371eea888d24e5bd347f2a) -
Enable support for IQauidio dacpro audio hats on
iMX8MMini EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit f4122d1b5c3e66c3fe731ea19e6e6e17c2000af6) -
Enable support for IQauidio dacplus audio hats on
iMX8MMini EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit 95b3f81802fe52fbe66ce6fbb28ae43f78d85f04) -
Enable support for Hifiberry dacplus audio hats on
iMX8MNano EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit c0bee3e1d91937b49e22e635f2bca53e8b25f57c) -
Enable support for IQauidio dacpro audio hats on
iMX8MNano EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit 9ebf35bcd2ce93b3595dee2b3a3f662b70f10088) -
Enable support for IQauidio dacplus audio hats on
iMX8MNano EVK.Signed-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit 0fe19d3f2e949c65ffa636d4971b9f5f463497fd) -
Enable imx-pcm512x sound driver as built-in module
for iMX8M EVK supportSigned-off-by: Adrian Alonso
Reviewed-by: Shengjiu Wang
(cherry picked from commit 84db7260f5a350f6e3d5418e7a90e8b352aaa183)
19 Nov, 2020
6 commits
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Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit 8e43cd16c8bbfe5b7e3c0fc1e7c3ddf738d8db01) -
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit 2972241b831ed65f641ccdb80b504cadef0ba591) -
According to i.MX8MP Architecture Defition Document, the maximum
clock rate comes generated by 'ccm_media_disp2_pix_clk_root' is
160MHz, so 1039.5MHz clock rate is not supported. And besides,
this clock rate will be set to the matched rate with display mode
in lcdif driver, so it is not necessary to set its rate in its
assigned-clock-rates property, and just leave it to be 0.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit 0e3556f282466e6b91def024afc815ef77733161) -
Due to commit 26ef2488a2ef (MLK-24998-1 arm64: dts: imx8mp: correct
assigned-clock-rates for video_pll1), default 27MHz dsi PHY reference
clock cannot be derived from 'vide_pll1', so change to use osc_24m
for the clock source and use 12MHz for dsi reference clock rate, since
below usual DDR clock rates can be derived through 12MHz clock rate:891000,
810000,
792000,
648000,
472500,
445500,
390000,
297000,
240000,
189000,All these clock rates comes from ADV7535 bridge driver.
Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit f3915cb61639821fbdcdc9db3cf3a8e0880cbca3) -
According to i.MX8MP Architecture Defition Document, the maximum
output frequency generated by video_pll1 is 1190MHz, so correct
its assigned-clock-rates to be 1039.5MHz to meet the spec.Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit 1dff13053bf83c2d4fb818562a086ad834f2a0bf) -
According to i.MX8MP Architecture Defition Document, the maximum
output frequency generated by video_pll1 is 1190MHz, so correct
its assigned-clock-rates to be 1039.5MHz to meet the spec.Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit b935595aa00859887a407dc6900763bfd41dfac2)
16 Nov, 2020
1 commit
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The A53 900MHz opp is actually 896MHz when reading back from SCFW, so
use the 896MHz instead of 900MHz to make it accurate enough.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 58be8bf3e6e8f51ed3a3b8f992baaa9eeaf3516d)
13 Nov, 2020
5 commits
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Adding "id" parameter in the ISP deivce nodes.
Signed-off-by: Oliver F. Brown
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Change the name of the Balser camera node from basler_camera to basler_camera_vvcam.
Signed-off-by: Oliver F. Brown
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Remove unused pll8k and pll11k clock.
Signed-off-by: Shengjiu Wang
Reviewed-by: Peng Zhang -
As the i.MX8MP DDR4 EVK board is running at ND mode, so the clock
frequency of bus & peripherals need to be updated to ND mode setting
accordingly. GIC, NOC & NOC_IO frequency is already configured as
ND mode setting when boot into linux kernel, so skip the configure
for them.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
Reviewed-by: Ye Li -
correct sdma device name as other socS, otherwise sdma firmware loaded in
Yocto will be failed since its rule is based on '30bd0000.dma-controller'
instead of '30bd0000.sdma' as other socS.Signed-off-by: Robin Gong
Reviewed-by: Shengjiu Wang
(cherry picked from commit 1d3c451b9703cd7b3b59c25f58bc541f8c30e8ae)
12 Nov, 2020
1 commit
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Add phy tuning result for USB certification, mainly for pass
eye pattern test, 6 parameters involved, details please check
its dt binding doc:
Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txtReviewed-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 87c832bb437df4a88a6331217ca64f6771ca569f)
06 Nov, 2020
2 commits
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The pinctrl settings for LCDIF were wrongly implemented, so correct
them.Signed-off-by: Robert Chiras
Acked-by: Laurentiu Palcu -
Change to max frequency that defined in OD mode for higher performance.
G1: 800M
G2: 700M
VC8000E: 500M
VPU_BUS: 800MSigned-off-by: Jian Li
Reviewed-by: Zhou Peng
03 Nov, 2020
1 commit
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Remove fsl,xcvr-fw property from xcvr node in sync
with the upstream accepted driver version.Signed-off-by: Viorel Suman
02 Nov, 2020
1 commit
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Update i.MX8MP imx8mp-pinfunc.h file according latest reference manual Rev.D.
Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
30 Oct, 2020
2 commits
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commit d01f449c008a ("of_net: add NVMEM support to of_get_mac_address")
introduces more return value types, so it has to use IS_ERR to check
the return value.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Since imx_mic_host module depends on COSM module, and COSM module
depends on SCIF module, so enable these modules and build them as
modules.Signed-off-by: Sherry Sun
28 Oct, 2020
2 commits
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Can see lcdif underrun occasionally in 4k display when run stress case
Increase lcdif FIFO panic level to avoid underrunSigned-off-by: Jian Li
Reviewed-by: Fancy Fang -
ATF put into the end of OCRAM on 8mp A1. Change the ocram layout
for lpa.Signed-off-by: Bing Song
27 Oct, 2020
1 commit
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Add i.MX8DXL DDR3 EVK rpmsg dts for communicating with M4
Reviewed-by: Fugang Duan
Signed-off-by: Peng Fan
26 Oct, 2020
1 commit
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Since the bug had been fixed on A1 chip, and PCIe GEN3 can can be
supported now.
Set the max speed of iMX8MP PCIe to GEN3.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
23 Oct, 2020
1 commit
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This reverts commit 3d65a3518149d33e289b5417d7a4a175b4ef0737.
The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.Signed-off-by: Jacky Bai
Tested-by: Jian Li
22 Oct, 2020
1 commit
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add memory-region to reserve GPU memory above 4G region.
Signed-off-by: Xianzhong
20 Oct, 2020
1 commit
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DDR4 EVK need larger min/max panic threshold to avoid display flickering
Signed-off-by: Jian Li
Reviewed-by: Fancy Fang
19 Oct, 2020
1 commit
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Add the i.MX8MP DDR4 EVK board support, on this board, there are
no flexspi & eMMC, so disable these nodes.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
16 Oct, 2020
2 commits
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Correct ddr4 evk board dts since it's based on old i.mx8mm-evk board.
Signed-off-by: Robin Gong
Reviewed-by: Fugang Duan -
Add nxp 88w8987 wireless support on imx8mm lpddr4 evk:
- covert to use pwrseq instead of regulator
- enable 32Khz input
- set 16k sample rate for bt scoReviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
15 Oct, 2020
2 commits
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Use the kexec command to restart the root cell Linux, and the system
will hang up in imx8mm_soc_uid(). The reason is that ocotp root clk is
not enabled when the unique ID is read. Therefore, add CLK_OCOTP_ROOT to
init-on-array in root.dts to ensure that ocotp root clk in the root cell
Linux is always enabled.Signed-off-by: Alice Guo
Reviewed-by: Peng Fan -
changed to pca9450 pmic for new i.mx8mm-evk board.
Signed-off-by: Robin Gong
Reviewed-by: Jacky Bai
