19 Nov, 2020
1 commit
-
Due to commit 82586f0aa1c2 (arm64: dts: imx8mp: correct
assigned-clock-rates for video_pll1), so remove unused
2079M clock from imx_pll1443x_tbl.Signed-off-by: Fancy Fang
Reviewed-by: Jacky Bai
(cherry picked from commit b96af227c28b1dfdbdf656de2a77bc4de99136e2)
13 Nov, 2020
2 commits
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when system running at ND mode, the noc, noc_io & gic clock can be sourced
from system PLL1, then system PLL2 will be disable during boot stage. it
seems disabling system PLL2 will lead to system hang due to unknow reason.
As the system PLL1/PLL2 should be used as fixed rate PLL, so simplify the
complexity of clock tree management, change these two PLLs as fixed rate clock.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
Reviewed-by: Ye Li -
this support is similar as i.MX8MM.
for userspace monitor control of the K-divider dynamically,
we provide two interfaces to userspace: delta_k & pll_parameter1): delta_k is used to adjust the K divider in PLL based on small
steps;
2): the pll_parameter interface is used for get PLL's current
M-divider, P-divider, S-divider & K-divider setting in PLL registerexample for the usage of these two interfaces:
A): Get the current PLL setting of dividers:
root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24ddB): if want to adjust the K-divider by a delta_k '1', then
echo 0x1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k;root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24deC): if want to adjust the K-divider by a delta_k '-1', then
echo -1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k;root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24dcSigned-off-by: Jacky Bai
Tested-by: Shengjiu Wang
Reviewed-by: Anson Huang
06 Nov, 2020
1 commit
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The PLL table count init is missed, then it will lead to
pll set rate failure due.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
27 Oct, 2020
1 commit
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As the DRAM PLL frequency can be changed during busfreq transition by
TF-A on i.MX8MQ, add 'CLK_GET_RATE_NOCACHE' flag for dram pll to make
sure linux kernel can get the correct rate of this pll.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
20 Oct, 2020
1 commit
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Fix below section mismatch build warnings:
The function imx8mp_clocks_probe() references
the function __init imx_clk_init_on().
This is often because imx8mp_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on is wrong.FATAL: modpost: Section mismatches detected.
Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.Signed-off-by: Jindong
Reviewed-by: Anson Huang
08 Oct, 2020
1 commit
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* tag 'v5.4.70': (3051 commits)
Linux 5.4.70
netfilter: ctnetlink: add a range check for l3/l4 protonum
ep_create_wakeup_source(): dentry name can change under you...
...Conflicts:
arch/arm/mach-imx/pm-imx6.c
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
drivers/crypto/caam/caamalg.c
drivers/gpu/drm/imx/dw_hdmi-imx.c
drivers/gpu/drm/imx/imx-ldb.c
drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
drivers/net/ethernet/freescale/enetc/enetc.c
drivers/net/ethernet/freescale/enetc/enetc_pf.c
drivers/thermal/imx_thermal.c
drivers/usb/cdns3/ep0.c
drivers/xen/swiotlb-xen.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.cSigned-off-by: Jason Liu
07 Oct, 2020
3 commits
-
[ Upstream commit f3bb0f796f5ffe32f0fbdce5b1b12eb85511158f ]
The ChipID IO region has it's own clock, which is being disabled while
scanning for unused clocks. It turned out that some CPU hotplug, CPU idle
or even SOC firmware code depends on the reads from that area. Fix the
mysterious hang caused by entering deep CPU idle state by ignoring the
'chipid' clock during unused clocks scan, as there are no direct clients
for it which will keep it enabled.Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Marek Szyprowski
Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrocki
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 5105660ee80862b85f7769626d0f936c18ce1885 ]
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
added checks to avoid enabling PLLs that have already been enabled by
the bootloader. However, the PLL_E configuration inherited from the
bootloader isn't necessarily the one that is needed for the kernel.This can cause SATA to fail like this:
[ 5.310270] phy phy-sata.6: phy poweron failed --> -110
[ 5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
[ 5.323022] tegra-ahci: probe of 70027000.sata failed with error -110Fix this by always programming the PLL_E. This ensures that any mis-
configuration by the bootloader will be overwritten by the kernel.Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by: LABBE Corentin
Tested-by: Corentin Labbe
Reviewed-by: Dmitry Osipenko
Signed-off-by: Thierry Reding
Signed-off-by: Sasha Levin -
commit b02cf0c4736c65c6667f396efaae6b5521e82abf upstream.
The fixed divider the emac_ptp_free_clk should be 2, not 4.
Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen
Link: https://lore.kernel.org/r/20200831202657.8224-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman
01 Oct, 2020
3 commits
-
[ Upstream commit 28b2f82e0383e27476be8a5e13d2aea07ebeb275 ]
Fix below division by zero warning:
[ 3.176443] Division by zero in kernel.
[ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124
[ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree)
[ 3.197821] Workqueue: events dbs_work_handler
[ 3.202849] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[ 3.211058] [] (show_stack) from [] (dump_stack+0xd8/0x110)
[ 3.218820] [] (dump_stack) from [] (Ldiv0_64+0x8/0x18)
[ 3.226263] [] (Ldiv0_64) from [] (clk_pfdv2_set_rate+0x54/0xac)
[ 3.234487] [] (clk_pfdv2_set_rate) from [] (clk_change_rate+0x1a4/0x698)
[ 3.243468] [] (clk_change_rate) from [] (clk_change_rate+0x280/0x698)
[ 3.252180] [] (clk_change_rate) from [] (clk_core_set_rate_nolock+0x1a0/0x278)
[ 3.261679] [] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x30/0x64)
[ 3.270743] [] (clk_set_rate) from [] (imx7ulp_set_target+0x184/0x2a4)
[ 3.279501] [] (imx7ulp_set_target) from [] (__cpufreq_driver_target+0x188/0x514)
[ 3.289196] [] (__cpufreq_driver_target) from [] (od_dbs_update+0x130/0x15c)
[ 3.298438] [] (od_dbs_update) from [] (dbs_work_handler+0x2c/0x5c)
[ 3.306914] [] (dbs_work_handler) from [] (process_one_work+0x2ac/0x704)
[ 3.315826] [] (process_one_work) from [] (worker_thread+0x2c/0x574)
[ 3.324404] [] (worker_thread) from [] (kthread+0x134/0x148)
[ 3.332278] [] (kthread) from [] (ret_from_fork+0x14/0x20)
[ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8)
[ 3.345314] 5fa0: 00000000 00000000 00000000 00000000
[ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000Signed-off-by: Anson Huang
Signed-off-by: Peng Fan
Signed-off-by: Shawn Guo
Signed-off-by: Sasha Levin -
[ Upstream commit cc26ed7be46c5f5fa45f3df8161ed7ca3c4d318c ]
do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.Signed-off-by: Dinh Nguyen
Link: https://lkml.kernel.org/r/20200114160726.19771-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 7f6ac72946b88b89ee44c1c527aa8591ac5ffcbe ]
The buffer allocated in ti_adpll_clk_get_name doesn't account for the
terminating null. This patch switches to devm_kasprintf to avoid
overflowing.Signed-off-by: Stephen Kitt
Link: https://lkml.kernel.org/r/20191019140634.15596-1-steve@sk2.org
Acked-by: Tony Lindgren
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
23 Sep, 2020
3 commits
-
[ Upstream commit e9c006bc782c488f485ffe50de20b44e1e3daa18 ]
A new warning in Clang points out that the initialization of
mux_pll_src_4plls_p appears incorrect:../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
concatenation of string literals in an array initialization; did you
mean to separate the elements with a comma? [-Wstring-concatenation]
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
^
,
../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
around the string literal to silence warning
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
^
1 warning generated.Given the name of the variable and the same variable name in rv1108, it
seems that this should have been four distinct elements. Fix it up by
adding the comma as suggested.Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Link: https://github.com/ClangBuiltLinux/linux/issues/1123
Signed-off-by: Nathan Chancellor
Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com
Reviewed-by: Heiko Stübner
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 3dabfa2bda48dab717986609762ce2a49335eb99 ]
'sizeof(*pllen)' should be used in place of 'sizeof(*pllout)' to avoid a
small over-allocation.Fixes: 2d1726915159 ("clk: davinci: New driver for davinci PLL clocks")
Signed-off-by: Christophe JAILLET
Link: https://lore.kernel.org/r/20200809144959.747986-1-christophe.jaillet@wanadoo.fr
Reviewed-by: David Lechner
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
add lpi2c4 clock support which exists on MX8QM.
Reviewed-by: Fugang Duan
Signed-off-by: Clark Wang
21 Aug, 2020
6 commits
-
[ Upstream commit f34e4651ce66a754f41203284acf09b28b9dd955 ]
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL
feedback loop. Bypass it by zeroing fb_prediv_mask when running on
bcm2711.Note that, since the prediv configuration bits were re-purposed, this
was triggering miscalculations on all clocks hanging from the VPU clock,
notably the aux UART, making its output unintelligible.Fixes: 42de9ad400af ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support")
Reported-by: Nathan Chancellor
Signed-off-by: Nicolas Saenz Julienne
Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.de
Tested-by: Nathan Chancellor
Reviewed-by: Florian Fainelli
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 12b90b40854a8461a02ef19f6f4474cc88d64b66 ]
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().Signed-off-by: Xu Wang
Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn
Acked-by: Barry Song
Fixes: 7bf21bc81f28 ("clk: sirf: re-arch to make the codes support both prima2 and atlas6")
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 3386af51d3bcebcba3f7becdb1ef2e384abe90cf ]
Add missing halt_check, hwcg_reg and hwcg_bit properties.
These were likely omitted when porting the driver upstream.Signed-off-by: Konrad Dybcio
Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit c8b9002f44e4a1d2771b2f59f6de900864b1f9d7 ]
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 667f39b59b494d96ae70f4217637db2ebbee3df0 ]
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit f47ee279d25fb0e010cae5d6e758e39b40eb6378 ]
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea
Reviewed-by: Manivannan Sadhasivam
Link: https://lore.kernel.org/r/c57e7ebabfa970014f073b92fe95b47d3e5a70b1.1593788312.git.cristian.ciocaltea@gmail.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
19 Aug, 2020
3 commits
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[ Upstream commit cf8030d7035bd3e89c9e66f7193a7fc8057a9b9a ]
In order to make the last clock available, maxbit has to be set to the
highest bit value plus 1.Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver")
Signed-off-by: Álvaro Fernández Rojas
Link: https://lore.kernel.org/r/20200609110846.4029620-1-noltari@gmail.com
Reviewed-by: Florian Fainelli
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit fcd2e0deae50bce48450f14c8fc5611b08d7438c ]
Currently we are not initializing the scmi clock with discrete rates
correctly. We fetch the min_rate and max_rate value only for clocks with
ranges and ignore the ones with discrete rates. This will lead to wrong
initialization of rate range when clock supports discrete rate.Fix this by using the first and the last rate in the sorted list of the
discrete clock rates while registering the clock.Link: https://lore.kernel.org/r/20200709081705.46084-2-sudeep.holla@arm.com
Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
Reviewed-by: Stephen Boyd
Reported-and-tested-by: Dien Pham
Signed-off-by: Sudeep Holla
Signed-off-by: Sasha Levin -
[ Upstream commit dad4e7fda4bdc1a6357db500a7bab8843c08e521 ]
The current implementation always uses rpmh_write_async, which doesn't
wait for completion. That's fine for disable requests since there's no
immediate need for the clocks and they can be disabled in the
background. However, for enable requests we need to ensure the clocks
are actually enabled before returning to the client. Otherwise, clients
can end up accessing their HW before the necessary clocks are enabled,
which can lead to bus errors.Use the synchronous version of this API (rpmh_write) for enable requests
in the active set to ensure completion.Completion isn't required for sleep/wake sets, since they don't take
effect until after we enter sleep. All rpmh requests are automatically
flushed prior to entering sleep.Fixes: 9c7e47025a6b ("clk: qcom: clk-rpmh: Add QCOM RPMh clock driver")
Signed-off-by: Mike Tipton
Link: https://lkml.kernel.org/r/20200215021232.1149-1-mdtipton@codeaurora.org
Reviewed-by: Bjorn Andersson
[sboyd@kernel.org: Reorg code a bit for readability, rename to 'wait' to
make local variable not conflict with completion.h mechanism]
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
22 Jul, 2020
4 commits
-
commit 37c72e4cae37f0dace1abb3711ede7fbc6d0862a upstream.
Add the missing ufs card and ufs phy clocks for SM8150. They were missed
in earlier addition of clock driver.Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
Signed-off-by: Vinod Koul
Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit f73a4230d5bbc8fc7e1a2479ac997f786111c7bb upstream.
Add the GPU and NPU clocks for SM8150. They were missed in earlier
addition of clock driver.Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
Signed-off-by: Vinod Koul
Link: https://lkml.kernel.org/r/20200513065420.32735-1-vkoul@kernel.org
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit c2407ab3bd55064d459bc822efd1c134e852798c ]
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.Signed-off-by: Eddie James
Reviewed-by: Andrew Jeffery
Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com
Acked-by: Joel Stanley
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 8e3709d7e3a67e2d3f42bd1fc2052353a5678944 ]
When building arm32 allmodconfig:
ld.lld: error: undefined symbol: ap_cp_unique_name
>>> referenced by ap-cpu-clk.c
>>> clk/mvebu/ap-cpu-clk.o:(ap_cpu_clock_probe) in archive drivers/built-in.aap_cp_unique_name is only compiled into the kernel image when
CONFIG_ARMADA_AP_CP_HELPER is selected (as it is not user selectable).
However, CONFIG_ARMADA_AP_CPU_CLK does not select it.This has been a problem since the driver was added to the kernel but it
was not built before commit c318ea261749 ("cpufreq: ap806: fix cpufreq
driver needs ap cpu clk") so it was never noticed.Fixes: f756e362d938 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Nathan Chancellor
Link: https://lore.kernel.org/r/20200701201128.2448427-1-natechancellor@gmail.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
01 Jul, 2020
1 commit
-
[ Upstream commit d0a5fdf4cc83dabcdea668f971b8a2e916437711 ]
The (struct __prci_data).hw_clks.hws is an array with dynamic elements.
Using struct_size(pd, hw_clks.hws, ARRAY_SIZE(__prci_init_clocks))
instead of sizeof(*pd) to get the correct memory size of
struct __prci_data for sifive/fu540-prci. After applying this
modifications, the kernel runs smoothly with CONFIG_SLAB_FREELIST_RANDOM
enabled on the HiFive unleashed board.Fixes: 30b8e27e3b58 ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block")
Signed-off-by: Vincent Chen
Signed-off-by: Palmer Dabbelt
Signed-off-by: Sasha Levin
24 Jun, 2020
10 commits
-
[ Upstream commit 2d491066ccd4286538450c227fc5094ceb04b494 ]
The latest specs for the AST2600 A1 chip include some different bit
definitions for calculating the AHB clock divider. Implement these in
order to get the correct AHB clock value in Linux.Signed-off-by: Eddie James
Link: https://lkml.kernel.org/r/20200408203616.4031-1-eajames@linux.ibm.com
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit c2f30986d418f26abefc2eec90ebf06716c970d2 ]
The function _sprd_pll_recalc_rate() defines return value to unsigned
long, but it would return a negative value when malloc fail, changing
to return its parent_rate makes more sense, since if the callback
.recalc_rate() is not set, the framework returns the parent_rate as
well.Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang
Link: https://lkml.kernel.org/r/20200519030036.1785-2-zhang.lyra@gmail.com
Reviewed-by: Baolin Wang
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit f376c43bec4f8ee8d1ba5c5c4cfbd6e84fb279cb ]
bcm2835_register_gate is used as a callback for the clk_register member
of bcm2835_clk_desc, which expects a struct clk_hw * return type but
bcm2835_register_gate returns a struct clk *.This discrepancy is hidden by the fact that bcm2835_register_gate is
cast to the typedef bcm2835_clk_register by the _REGISTER macro. This
turns out to be a control flow integrity violation, which is how this
was noticed.Change the return type of bcm2835_register_gate to be struct clk_hw *
and use clk_hw_register_gate to do so. This should be a non-functional
change as clk_register_gate calls clk_hw_register_gate anyways but this
is needed to avoid issues with further changes.Fixes: b19f009d4510 ("clk: bcm2835: Migrate to clk_hw based registration and OF APIs")
Link: https://github.com/ClangBuiltLinux/linux/issues/1028
Signed-off-by: Nathan Chancellor
Link: https://lkml.kernel.org/r/20200516080806.1459784-1-natechancellor@gmail.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 25bdae0f1c6609ceaf55fe6700654f0be2253d8e ]
Mark the SCLK clock for Exynos5433 I2S1 device with IGNORE_UNUSED flag to
match its behaviour with SCLK clock for AUD_I2S (I2S0) device until
a proper fix for Exynos I2S driver is ready.This fixes the following synchronous abort issue revealed by the probe
order change caused by the commit 93d2e4322aa7 ("of: platform: Batch
fwnode parsing when adding all top level devices")Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 50 Comm: kworker/0:1 Not tainted 5.7.0-rc5+ #701
Hardware name: Samsung TM2E board (DT)
Workqueue: events deferred_probe_work_func
pstate: 60000005 (nZCv daif -PAN -UAO)
pc : samsung_i2s_probe+0x768/0x8f0
lr : samsung_i2s_probe+0x688/0x8f0
...
Call trace:
samsung_i2s_probe+0x768/0x8f0
platform_drv_probe+0x50/0xa8
really_probe+0x108/0x370
driver_probe_device+0x54/0xb8
__device_attach_driver+0x90/0xc0
bus_for_each_drv+0x70/0xc8
__device_attach+0xdc/0x140
device_initial_probe+0x10/0x18
bus_probe_device+0x94/0xa0
deferred_probe_work_func+0x70/0xa8
process_one_work+0x2a8/0x718
worker_thread+0x48/0x470
kthread+0x134/0x160
ret_from_fork+0x10/0x1c
Code: 17ffffaf d503201f f94086c0 91003000 (88dffc00)
---[ end trace ccf721c9400ddbd6 ]---Signed-off-by: Marek Szyprowski
Signed-off-by: Sylwester Nawrocki
Signed-off-by: Sasha Levin -
[ Upstream commit c7c1cbbc9217ebb5601b88d138d4a5358548de9d ]
The parent_names is never released for a component clock definition,
causing some memory leak. Fix by releasing it once it is no longer
needed.Reported-by: Tomi Valkeinen
Signed-off-by: Tero Kristo
Link: https://lkml.kernel.org/r/20200429131341.4697-2-t-kristo@ti.com
Acked-by: Tony Lindgren
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit a29ae8600d50ece1856b062a39ed296b8b952259 ]
Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers.
In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when
booting Linux the PLL fails to lock.
The initialization sequence from u-boot is:
- put the PLL into reset
- write 0x59C88000 to HHI_GP_PLL_CNTL2
- write 0xCA463823 to HHI_GP_PLL_CNTL3
- write 0x0286A027 to HHI_GP_PLL_CNTL4
- write 0x00003000 to HHI_GP_PLL_CNTL5
- set M, N, OD and the enable bit
- take the PLL out of reset
- check if it has locked
- disable the PLLIn Linux we already initialize M, N, OD, the enable and the reset bits.
Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the
exact meaning is unknown) so the PLL can lock when the vendor u-boot did
not initialize these registers yet.Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 8bb629cfb28f4dad9d47f69249366e50ae5edc25 ]
The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL
register:
- HHI_VID_CLK_CNTL[0] = DIV1_EN
- HHI_VID_CLK_CNTL[1] = DIV2_EN
- HHI_VID_CLK_CNTL[2] = DIV4_EN
- HHI_VID_CLK_CNTL[3] = DIV6_EN
- HHI_VID_CLK_CNTL[4] = DIV12_ENUpdate the bits accordingly so we will enable the bits in the correct
register once we switch these clocks to be mutable.Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 0d3051c790ed2ef6bd91b92b07220313f06b95b3 ]
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin -
[ Upstream commit da1978ac3d6cf278dedf5edbf350445a0fff2f08 ]
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not
easy to see that the vendor kernel does the same, but it actually does.
meson_clk_pll_ops in mainline still cannot fully recalculate all rates
from the HDMI PLL registers because some register bits (at the time of
writing it's unknown which bits are used for this) double the HDMI PLL
output rate (compared to simply considering M, N and FRAC) for some (but
not all) PLL settings.Update the vid_pll_in_sel parent so our clock calculation works for
simple clock settings like the CVBS output (where no rate doubling is
going on). The PLL ops need to be fixed later on for more complex clock
settings (all HDMI rates).Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees")
Suggested-by: Neil Armstrong
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin -
[ Upstream commit a403bbab1a73d798728d76931cab3ff0399b9560 ]
Fixes an issue leading to having all clocks following a critical
clocks marked as well as criticals.Fixes: fa6415affe20 ("clk: st: clk-flexgen: Detect critical clocks")
Signed-off-by: Alain Volmat
Link: https://lkml.kernel.org/r/20200322140740.3970-1-avolmat@me.com
Reviewed-by: Patrice Chotard
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
