27 Mar, 2020
1 commit
06 Dec, 2019
1 commit
25 Nov, 2019
1 commit
29 Mar, 2019
1 commit
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Introduce inmate linux support for jailhouse, we need to benchmark
inmate OS, so choose linux. The clock/pin are preconfigured by 1st
root cell linux.Signed-off-by: Peng Fan
Acked-by: Ye Li
19 Mar, 2019
1 commit
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Because we add the partition reboot function, and assign all flexcan
pins to M4, A core cannot access flexcan pins for now.LPUART3 uses flexcan pins before, so disable it to avoid this error:
imx8qxp-pinctrl iomuxc: pin_config_set op failed for pin 110Signed-off-by: Clark Wang
15 Mar, 2019
1 commit
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Add dma support for lpspi0 and lpspi2 modules on i.MX8QXP board.
Ensure the lpspi does not use cs-gpio in slave mode.
Signed-off-by: Clark Wang
11 Mar, 2019
1 commit
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We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.Signed-off-by: Leonard Crestez
Reviewed-by: Peng Fan
(cherry picked from commit f573dbd5ce119740ad30b663e3599cb75e6f67ed)
06 Mar, 2019
1 commit
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Fix lvds-pwm usage, it needs to be under vehicle_rpmsg_m4 node for
android auto.Signed-off-by: Peng Fan
(cherry picked from commit 31db2776c4cf4b27417c57f3c7c013085cee1528)
05 Mar, 2019
3 commits
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Need to change the default HDMI TX clocks to 800 MHz for DPLL and 100 MHz
for bus.Signed-off-by: Oliver Brown
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Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu
01 Mar, 2019
2 commits
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These CAN related regulators will be handled when kernel boots. However,
these regulators which aren't used by any devices will be disabled by the
regulator framework. So, the pins in these regulators will be non-active
status. This causes the CAN module cannot be used in M4 side.So, disable these regualtors for 8QM/QXP, and let M4 handles these.
Suggested-by: Fugang Duan
Signed-off-by: Clark Wang -
Passthrough lvds pwm, otherwise dom0 will panic when reboot if
domu started and shutdown, because LVDS_1_PWM_0 is assigned
to domu and when domu shutdown, the resource will be powered
off, however dom0 still think it is powered on.since lvds1_pwm is expected for domu, so let's passthrough it.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
(cherry picked from commit abb243aba12a6649fad8114e298ff075b0a8399d)
28 Feb, 2019
1 commit
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The IPG clock is introduced for i2c0 and i2c2 nodes in order to do
properly clock gating/ungating for i2c0 and i2c2.
'ipg' clock drives the access to the device iomapped registers,
so with this patch we are now able to read I2C registers.Signed-off-by: Stoica Cosmin-Stefan
Reviewed-by: Daniel Baluta
Reviewed-by: Fugang Duan
27 Feb, 2019
1 commit
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Switch to use rpmsg i2c to support android auto, because
android auto change to use rpmsg i2c.
Also add the alias node to let m4 could use it successfully, because
M4 side use the alias id as the BUSID.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
26 Feb, 2019
5 commits
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The resources are wrongly added.
Signed-off-by: Peng Fan
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Cleanup the resources that not could be set SID and remove the UNUSED
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
Update domu car dts according to android auto changes.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
When resources are owned by M41, we need to handle that correctly in
xen.Also drop power doamins for xen,shared gpio, xen will power up the gpio.
gpio1 is owned by M41, so we also need to check its power status in xen.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
CM41 runs before CortexA, we should not use smmu to restrict it, because
smmu is owned by xen. Also remove MU_13/12 which is wrongly added
before.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
23 Feb, 2019
2 commits
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change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.Signed-off-by: Han Xu
(cherry picked from commit f55654688059a337490915cd6f652d0585597f3d) -
Increased the clock rate for better performance.
Signed-off-by: Han Xu
(cherry picked from commit 582ba08afcaf79fc09465a0cd2dd66cf1e86813e)
22 Feb, 2019
2 commits
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After fix the ADMA length mismatch issue on imx8mm, we can
support eMMC CMDQ, so enable it. This patch also make imx8mm
support HS400ES mode.Signed-off-by: Haibo Chen
(cherry picked from commit 861d1d962e90f1244bfc8249d111c633c9c038ca) -
Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM
board.Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So
delete these two files.Signed-off-by: Clark Wang
21 Feb, 2019
1 commit
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IR uses GPIO1_13 not GPIO_12 in imx8mm-evk board.
Signed-off-by: Joakim Zhang
20 Feb, 2019
2 commits
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Enable IR on imx8mq-evk board.
Signed-off-by: Joakim Zhang
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Enable IR on imx8mm-evk board.
Signed-off-by: Joakim Zhang
19 Feb, 2019
1 commit
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i.MX8QXP has separated irq, and shared irq for lpuart with eDMA,
it is better for uart to use separated irq although there has
no function impact.Reviewed-by: Robin Gong
Signed-off-by: Fugang Duan
15 Feb, 2019
1 commit
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Update resource ID table to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Reviewed-by: Peng Fan
(cherry picked from commit 8fa8f318eeac939604e2616fd7a6e1fd10d837a0)
14 Feb, 2019
1 commit
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LSIO_GPIO1 drive the IOEXP_RST signal, its power is off in system
suspend to save power, which introduces reset pulse for expander IO.To avoid unexpected reset, set the PIN to "latch" status before the
GPIO controller is power off during suspend.Signed-off-by: Fugang Duan
(cherry picked from commit: 0c859a75a465d39d10784d95895188bb6f02492e)
12 Feb, 2019
10 commits
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Currently, the phy_ref clock is also used by dsi_bridge nodes (nwl-dsi
driver) in order to set the phy_ref rate needed by a specific mode.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Currently, the phy_ref clock is also used by dsi_bridge nodes (nwl-dsi
driver) in order to set the phy_ref rate needed by a specific mode.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Reconfigure the LCDIF, DCSS and DSI clocks such that we can use
mode_valid to determine which mode can be supported or not by a specific
display pipe (DCSS+DSI or LCDIF+DSI).Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
buffer twice
1. Modify adding buffer for queue list to not queue same buffer twice
2. remove decoder_str in dts fileSigned-off-by: Huang Chaofan
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Increase the clock rate for all mt35xu512aba on fspi from 29Mhz to 133Mhz for better performance.
Signed-off-by: Han Xu
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This reverts commit eb56237c4dc10fd9ef303e61b0afae2fba9d5174.
The HW suggested value can't work well at some USB devices, so revert
this patch.Reported-by: Andy Tian
Tested-by: Andy Tian
Suggested-by: Yin Huang
Signed-off-by: Peter Chen -
the region of CMA associated with M0+ core is in [256M, 1G]
It can't be guaranteed that it's uncachable for M0+ core.
There are some risk, reserve memory to make sure it's in [128M, 256M].
Eliminate the potential risksSigned-off-by: ming_qian
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the sim_hsio clock must be on before doing hsio power domain on/off.
Assign this clock to hiso power domain to make sure this clock is
enable before power domain on/off.Signed-off-by: Jacky Bai
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This reverts commit 68b8fbbad02bc3bfca95fdc75ee67bd06d91b684.
the audio playback issue is caused by incorrect setting for WAIT mode.
no need to change the latency setting, so back to use the original
latency setting. -
There are two validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for DX/QXP 17x17 chips. These boards have different design as 21x21 DDR3l
and LPDDR4 validation board. Need to create new FDT for them.Because except DDR the two boards have same design, use 17x17 for its name
without binding DDR type.Signed-off-by: Ye Li
Acked-by: Peng Fan
