23 Feb, 2019
1 commit
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change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.Signed-off-by: Han Xu
(cherry picked from commit f55654688059a337490915cd6f652d0585597f3d)
12 Feb, 2019
24 commits
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Increase the clock rate for all mt35xu512aba on fspi from 29Mhz to 133Mhz for better performance.
Signed-off-by: Han Xu
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This reverts commit eb56237c4dc10fd9ef303e61b0afae2fba9d5174.
The HW suggested value can't work well at some USB devices, so revert
this patch.Reported-by: Andy Tian
Tested-by: Andy Tian
Suggested-by: Yin Huang
Signed-off-by: Peter Chen -
- Correct the rpmsg compatible property on imx8mm/mq.
- Move the rpmsg dts to the -m4 dts on imx8qm.Signed-off-by: Richard Zhu
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at present, driver use core number(core_type) to determine platform
type, 1 means qxp, 2 means qm.
this method is not accurate. it's hard to expansion.
so get platform type from device id instead of core number.
remove core_type in dts.Signed-off-by: ming_qian
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Add cyw4356 and cyw4359 support on imx8qm/8qxp MEK boards..
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Since user want to keep modem keep the orignal state during system
suspend, then need to keep the reset PIN state by set sleep pinctrl,
and configure the PIN group to default pinctrl after system resume
back.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
By default, i.MX8QM MEK base board support NXP tja1100 PHY by load
the dts file: fsl-imx8qm-mek-enet2-tja1100.dts
In fact, the MEK base board also support AR8031 daughter board. So
enable the PHY in default dts.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
To improve the signal quality, and passed eye-diagram.
Suggested-by: Yin Huang
Signed-off-by: Peter Chen -
delete "fsl-imx8qm-mek-8cam.dts" and "fsl-imx8qm-mek-mipi-two-ov5640.dts"
file because they are for eight and four cameras. The default dts support
connect four or eight sensors, so the two dts are redundant.The default "fsl-imx8qm-mek.dts" support one max9286 with four ov10635 or
two max9286 with eight ov10635, user can connect one or both of themThe "fsl-imx8qm-mek-ov5640.dts" is only for ov5640 sensor, support
one or two mipi interfaceSigned-off-by: Guoniu.Zhou
(cherry picked from commit e0cf682b551a2fd8813298d27399837577b352c4) -
- Since the l1ss is not enabled yet, configure
the clkreq# as gpio on 8qm/qxp mek boards.
Re-configure the clkreq# as input and open
drain when l1ss is enabled later.
- Correct the perst# configurations of 8qm.Signed-off-by: Richard Zhu
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Correct the interrupt line for adv7535.
Fixes: 0f43068a7028 ("Correct interrupts for adv7535")
Signed-off-by: Fugang Duan
Tested-by: Robert Chiras
Acked-by: Fancy Fang -
Once 32Khz low power clock enable for Murata 1CQ module, Bluetooth core
may enter low power idle status that cause HCI communication error when
HCI device is down for 2 seconds after initialization.
Currently, remove the LP 32Khz input for the module.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Keep wlreg_on regulator on during system suspended status due to
external wifi module power requirement. Also keep the old Murata
1CQ M.2 card support.To set the PIN to "latch" status before the GPIO controller is power
off during suspend, and set the PIN to "PASS" status after GPIO
controller status restored during system resume back.Reviewed-by: yang.tian
Tested-by: yang.tian
Signed-off-by: Fugang Duan -
This patch fixes the interrupts used by ADV7535. Initial patch
configured the GPIO0 IO00 as IO pin for the DSI_INT, used by ADV7535,
but the correct one is IO01, since IO00 is used by PWM.Fixes: c2f1eceb5629 ("arm64: dts: imx8qm/qxp mek: Configure interrupts
for adv7535")
Signed-off-by: Robert Chiras -
Configure the interrupt for ADV7535 so that it can generate interrupts
events for HDP when the HDMI cable is plugged in or out.Signed-off-by: Robert Chiras
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Configure imx8qm/qxp pin as RTC 32KHz clock output as the
low power clock source for some WIFI chip.Reviewed-by: Haibo Chen
Signed-off-by: Fugang Duan -
There is noise issue with 192kHz recoding with ESAI + CS42xx8 on imx8qm
mek board.This issue is caused by the round trip delay due to longer trace length
on board. After we switch to tx master, rx slave mode, the issue is gone.
so the setting can workaround the issue, the reason is that the bitclock,
frame clock and data is generated from one side, for recording, is from
codec, the asynchronous of clock and data is eliminated.Signed-off-by: Shengjiu Wang
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In SPF-29420-B2, the SCU_GPIO0_03 is used as AUD_DEC_1V8 for wm8960
codec. With this chage, the headphone plugin/plugout detection
can be enabled.Signed-off-by: Shengjiu Wang
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Move the mipi csi en/rst pinctrl configuration from gpio1 to
specific node for mipi csi.Signed-off-by: Peng Fan
Reviewed-by: Guoniu.Zhou -
Add the missing vdev-nums updates for cm41 on imx8qm
mek board.Signed-off-by: Richard Zhu
Acked-by: Jason Liu -
Support the multi-vdev on one rpmsg channel on 8qm/qxp mek boards.
Signed-off-by: Richard Zhu
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Reduce imx8qm/qxp mek board enet1 port pins drive strength by modifing
PDRV to 0x1 to pass EMI test.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
When early_power_on is present in power domain dtb node, it
will be powered on during resume regardless of whether the
related module is enabled or NOT, this will cause cm4_intmux
always power ON after first time resume when cm4_intmux is
NOT enabled.So move this early_power_on property to board level dtb, ONLY
when cm4_intmux is enabled, then this property is added.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Rename fsl-imx8qm-mek.dts to fsl-imx8qm-mek.dtsi and keep /dts-v1/ in
fsl-imx8qm-mek.dts, then let fsl-imx8qm-mek.dts include
fsl-imx8qm-mek.dtsi.This is to prepare adding /memreserve/ for mek dom0 dts.
Signed-off-by: Peng Fan
Acked-by: Anson Huang
