31 Aug, 2017

2 commits


21 May, 2017

1 commit


16 May, 2017

1 commit


15 May, 2017

2 commits


08 Mar, 2017

1 commit


19 Nov, 2016

1 commit

  • …guo/linux into next/dt64

    Freescale arm64 device tree updates for 4.10:
    - Enable Thermal Monitoring Unit (TMU) for thermal management on
    LS1043A and LS2080A.
    - Add support for LS1046A SoC, which has similar peripherals as
    LS1043A but integrates 4 A72 cores.
    - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.

    * tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
    arm64: dts: ls2080a: Add TMU device tree support for LS2080A
    arm64: dts: ls1043a: Add TMU device tree support for LS1043A
    arm64: dts: add LS1046A-QDS board support
    Documentation: DT: Add entry for QorIQ LS1046A-QDS board
    arm64: dts: add LS1046A-RDB board support
    Documentation: DT: Add entry for QorIQ LS1046A-RDB board
    arm64: dts: add QorIQ LS1046A SoC support
    dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
    dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
    dt-bindings: i2c: adds two more nxp devices
    dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
    dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings

    Signed-off-by: Olof Johansson <olof@lixom.net>

    Olof Johansson
     

15 Nov, 2016

1 commit


21 Oct, 2016

1 commit


15 Oct, 2016

1 commit

  • Pull libata updates from Tejun Heo:
    - Write same support added
    - Minor ahci MSIX irq handling updates
    - Non-critical SCSI command translation fixes
    - Controller specific changes

    * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
    ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC"
    libata: remove
    libata: remove unused definitions from
    pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
    ata: Replace BUG() with BUG_ON().
    ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc.
    libata: Some drives failing on SCT Write Same
    ahci: use pci_alloc_irq_vectors
    libata: SCT Write Same handle ATA_DFLAG_PIO
    libata: SCT Write Same / DSM Trim
    libata: Add support for SCT Write Same
    libata: Safely overwrite attached page in WRITE SAME xlat
    ahci: also use a per-port lock for the multi-MSIX case
    ARM: dts: STiH407-family: Add ports-implemented property in sata nodes
    ahci: st: Add ports-implemented property in support
    ahci: qoriq: enable snoopable sata read and write
    ahci: qoriq: adjust sata parameter
    libata-scsi: fix MODE SELECT translation for Control mode page
    libata-scsi: use u8 array to store mode page copy

    Linus Torvalds
     

15 Sep, 2016

2 commits

  • * dt/irq-fix:
    arm64: dts: Fix broken architected timer interrupt trigger

    This resolves a non-obvious conflict between a bugfix from
    v4.8 and a cleanup for the exynos7 platform.

    Arnd Bergmann
     
  • The ARM architected timer specification mandates that the interrupt
    associated with each timer is level triggered (which corresponds to
    the "counter >= comparator" condition).

    A number of DTs are being remarkably creative, declaring the interrupt
    to be edge triggered. A quick look at the TRM for the corresponding ARM
    CPUs clearly shows that this is wrong, and I've corrected those.
    For non-ARM designs (and in the absence of a publicly available TRM),
    I've made them active low as well, which can't be completely wrong
    as the GIC cannot disinguish between level low and level high.

    The respective maintainers are of course welcome to prove me wrong.

    While I was at it, I took the liberty to fix a couple of related issue,
    such as some spurious affinity bits on ThunderX, and their complete
    absence on ls1043a (both of which seem to be related to copy-pasting
    from other DTs).

    Acked-by: Duc Dang
    Acked-by: Carlo Caione
    Acked-by: Michal Simek
    Acked-by: Krzysztof Kozlowski
    Acked-by: Dinh Nguyen
    Acked-by: Masahiro Yamada
    Signed-off-by: Marc Zyngier
    Signed-off-by: Arnd Bergmann

    Marc Zyngier
     

30 Aug, 2016

1 commit


10 Aug, 2016

1 commit


02 Aug, 2016

1 commit

  • Pull 64-bit ARM DT updates from Olof Johansson:
    "Just as the 32-bit contents, the 64-bit device tree branch also
    contains a number of additions this release cycle.

    New platforms:
    - LG LG1313
    - Mediatek MT6755
    - Renesas r8a7796
    - Broadcom 2837

    Other platforms with larger updates are:
    - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
    - Mediatek MT8173 (display subsystem added)
    - Rockchip RK3399 (a lot of new peripherals)
    - ARM Juno reference implementation (SCPI power domains, coresight,
    thermal)"

    * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
    arm64: tegra: Enable HDMI on Jetson TX1
    arm64: tegra: Add sor1_src clock
    arm64: tegra: Add XUSB powergates on Tegra210
    arm64: tegra: Add DPAUX pinctrl bindings
    arm64: tegra: Add ACONNECT bus node for Tegra210
    arm64: tegra: Add audio powergate node for Tegra210
    arm64: tegra: Add regulators for Tegra210 Smaug
    arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
    arm64: tegra: Enable XUSB controller on Jetson TX1
    arm64: tegra: Enable debug serial on Jetson TX1
    arm64: tegra: Add Tegra210 XUSB controller
    arm64: tegra: Add Tegra210 XUSB pad controller
    arm64: tegra: Add DSI panel on Jetson TX1
    arm64: tegra: p2597: Add SDMMC power supplies
    arm64: tegra: Add PMIC support on Jetson TX1
    Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
    arm64: dts: hi6220: Add pl031 RTC support
    arm64: dts: r8a7796/salvator-x: Enable watchdog timer
    arm64: dts: r8a7796: Add RWDT node
    arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
    ...

    Linus Torvalds
     

21 Jun, 2016

1 commit


16 Jun, 2016

1 commit

  • The 'dma-coherent' indicates that the hardware IP block can ensure
    the coherency of the data transferred from/to the IP block. This
    can avoid the software cache flush/invalid actions, and improve
    the performance significantly.

    The PCI IP block of ls1043a has this capability, so adding this
    feature to improve the PCI performance.

    Signed-off-by: Liu Gang
    Signed-off-by: Shawn Guo

    Liu Gang
     

11 Jun, 2016

1 commit


09 Jun, 2016

1 commit


07 Jun, 2016

1 commit


18 Apr, 2016

1 commit


13 Apr, 2016

1 commit


14 Feb, 2016

1 commit


23 Dec, 2015

1 commit

  • LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are
    similar to LS1021a which also complies to Freescale Chassis 2.1 spec.

    Created LS1043a SoC DTSI file to be included by board level DTS files.

    Signed-off-by: Li Yang
    Signed-off-by: Hou Zhiqiang
    Signed-off-by: Mingkai Hu
    Signed-off-by: Wenbin Song
    Signed-off-by: Olof Johansson

    Mingkai Hu