02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
13 Jun, 2017
1 commit
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The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.Signed-off-by: Mikko Perttunen
Signed-off-by: Thierry Reding
04 Apr, 2017
1 commit
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Add the DT node for the GP10B GPU on Tegra186.
Signed-off-by: Alexandre Courbot
Signed-off-by: Thierry Reding
08 Mar, 2017
2 commits
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The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data
transfer rates.Acked-by: Jon Hunter
Signed-off-by: Thierry Reding -
The NVIDIA Tegra186 SoC has a Power Management Controller that performs
various tasks related to system power, boot as well as suspend/resume.Acked-by: Jon Hunter
Signed-off-by: Thierry Reding
27 Jan, 2017
1 commit
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Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.Signed-off-by: Thierry Reding
25 Jan, 2017
2 commits
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Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.Signed-off-by: Thierry Reding
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Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.Signed-off-by: Thierry Reding
21 Nov, 2016
6 commits
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Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.Signed-off-by: Thierry Reding
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Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).Signed-off-by: Thierry Reding
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Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).Signed-off-by: Thierry Reding
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The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.Signed-off-by: Thierry Reding
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Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.Signed-off-by: Thierry Reding
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This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.Signed-off-by: Joseph Lo
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding