12 Feb, 2019
6 commits
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perf stat -a -e ddr0/axid-read,axi_id=MMMMDDDD/ cmd
MMMM AXI_MASKING
DDDD AXI_IDSigned-off-by: Frank Li
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[ 28.061044] perf[2494]: PC Alignment exception: pc=0000000072656d69 sp=ffff800032f2bd30
[ 28.069061] Internal error: Oops - SP/PC alignment exception: 8a000000 1 PREEMPT SMP
[ 28.077066] Modules linked in:
[ 28.080128] CPU: 2 PID: 2494 Comm: perf Not tainted 4.9.11-02540-g3ebe22c #52
[ 28.087263] Hardware name: Freescale i.MX8QXP LPDDR4 ARM2 (DT)
[ 28.093093] task: ffff80002e097080 task.stack: ffff800032f28000
[ 28.099011] PC is at 0x72656d69
[ 28.102163] LR is at perf_try_init_event+0x98/0xb0
[ 28.106950] pc : [] lr : [] pstate: 60000145Signed-off-by: Frank Li
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Added support for counter overflow interrupts.
When the cycles counter overflows, update all local event data,
then reset it and let it continue counting.Signed-off-by: Tiberiu Breana
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Always enable cycles counter 0, regardless if it is explicitly
selected by the user or not. The cycles counter generates overflow
interrupts that will be used to update other counters.Signed-off-by: Tiberiu Breana
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- repurpose e2c_map array to a perf_event* array
- add ddr_perf_event_enable function
- tidy up indentingSigned-off-by: Tiberiu Breana
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perf stat -a -e ddr0/cycles/,ddr0/read-bytes/,ddr0/write-bytes/,ddr1/cycles/,d
dr1/read-bytes/,ddr1/write-bytes/ dd if=/dev/zero of=/dev/null bs=10M count=1
1+0 records in
1+0 records outPerformance counter stats for 'system wide':
7236174 ddr0/cycles/ (99.97%)
8573 ddr0/read-bytes/ (99.99%)
163628 ddr0/write-bytes/
7256543 ddr1/cycles/ (99.99%)
9308 ddr1/read-bytes/ (100.00%)
165039 ddr1/write-bytes/0.008990125 seconds time elapsed
Signed-off-by: Frank Li
Signed-off-by: Tiberiu Breana
18 Oct, 2018
1 commit
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commit ca2b497253ad01c80061a1f3ee9eb91b5d54a849 upstream.
It doesn't make sense for a perf event to be configured as a CHAIN event
in isolation, so extend the arm_pmu structure with a ->filter_match()
function to allow the backend PMU implementation to reject CHAIN events
early.Cc:
Reviewed-by: Suzuki K Poulose
Signed-off-by: Will Deacon
Signed-off-by: Greg Kroah-Hartman
24 Aug, 2018
1 commit
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[ Upstream commit a45fc268db20ecd859bb61e25045912b3194b5e6 ]
This patch fixes the below parser error of the IOB SLOW PMU.
# perf stat -a -e iob-slow0/cycle-count/ sleep 1
evenf syntax error: 'iob-slow0/cycle-count/'
\___ parser errorIt replaces the "-" character by "_" character inside the PMU name.
Signed-off-by: Hoan Tran
Signed-off-by: Will Deacon
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
22 Sep, 2017
1 commit
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Free memory region, if arm_pmu_acpi_probe is not successful.
Acked-by: Will Deacon
Signed-off-by: Arvind Yadav
Signed-off-by: Catalin Marinas
09 Aug, 2017
1 commit
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Rather than continue adding CPU-specific event maps, instead look up by
default in the PMUv3 event map and only fallback to the CPU-specific maps
if either the event isn't described by PMUv3, or it is described but
the PMCEID registers say that it is unsupported by the current CPU.Signed-off-by: Will Deacon
08 Aug, 2017
1 commit
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Managed resources in the driver should be automatically cleaned up on
driver detach. It's unnecessary to manually free/unmmap these resources.
One of the manual cleanup causes static checkers to complain.
The bug is reported by Dan Carpenter in [1][1] https://www.spinics.net/lists/arm-kernel/msg593012.html
This patch gets rid of all the unnecessary manual cleanup and properly
unregister all the registered PMU devices by the driver on driver detach.Signed-off-by: Tai Nguyen
Signed-off-by: Will Deacon
27 Jul, 2017
1 commit
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Since the PMU register interface is banked per CPU, CPU PMU interrrupts
cannot be handled by a CPU other than the one with the PMU asserting the
interrupt. This means that migrating PMU SPIs, as we do during a CPU
hotplug operation doesn't make any sense and can lead to the IRQ being
disabled entirely if we route a spurious IRQ to the new affinity target.This has been observed in practice on AMD Seattle, where CPUs on the
non-boot cluster appear to take a spurious PMU IRQ when coming online,
which is routed to CPU0 where it cannot be handled.This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their
affinity prior to requesting them, ensuring that they cannot
be migrated during hotplug events. This interacts badly with the DB8500
erratum workaround that ping-pongs the interrupt affinity from the handler,
so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags
to be overridden in the platdata.Fixes: 3cf7ee98b848 ("drivers/perf: arm_pmu: move irq request/free into probe")
Cc: Mark Rutland
Cc: Linus Walleij
Signed-off-by: Will Deacon
26 Jul, 2017
1 commit
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The check for column exclusion did not verify that the event being
checked was an L2 event, and not a software event.
Software events should not be checked for column exclusion.
This resulted in a group with both software and L2 events sometimes
incorrectly rejecting the L2 event for column exclusion and
not counting it.Add a check for PMU type before applying column exclusion logic.
Fixes: 21bdbb7102edeaeb ("perf: add qcom l2 cache perf events driver")
Acked-by: Mark Rutland
Signed-off-by: Neil Leeder
Signed-off-by: Will Deacon
20 Jul, 2017
1 commit
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Signed-off-by: Rob Herring
Cc: Will Deacon
Cc: Mark Rutland
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Will Deacon
26 Jun, 2017
1 commit
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Merge in arm64 ACPI RAS support (APEI/GHES) from Tyler Baicar.
23 Jun, 2017
3 commits
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This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
Unit version 3.It can support up to
- 2 IOB PMU instances
- 8 L3C PMU instances
- 2 MCB PMU instances
- 8 MCU PMU instances
and these PMUs support 64 bit counterSigned-off-by: Hoan Tran
[Mark: stop counters in _xgene_pmu_isr()]
Signed-off-by: Mark Rutland
[will: make xgene_pmu_v3_ops static]
Signed-off-by: Will Deacon -
This patch moves PMU leaf functions into a function pointer structure.
It helps code maintain and expasion easier.Signed-off-by: Hoan Tran
[Mark: remove redundant cast]
Signed-off-by: Mark Rutland
[will: make xgene_pmu_ops static]
Signed-off-by: Will Deacon -
This patch parses PMU Subnode from a match table.
Signed-off-by: Hoan Tran
Signed-off-by: Mark Rutland
Signed-off-by: Will Deacon
15 Jun, 2017
1 commit
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All PMU drivers are going to depend on PERF_EVENTS, so let's make this
dependency common and simplify the individual Kconfig entries.Signed-off-by: Mark Rutland
Cc: Will Deacon
Signed-off-by: Will Deacon
30 May, 2017
1 commit
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We saw perf IRQ init failures when running Linux kernel in an ACPI
guest without PMU (i.e. pmu=off). This is because perf IRQ is not
present when pmu=off, but arm_pmu_acpi still tries to register
or unregister GSI. This patch addresses the problem by checking
gicc->performance_interrupt. If it is 0, which is the value set
by qemu when pmu=off, we skip the IRQ register/unregister process.[ 4.069470] bc00: 0000000000040b00 ffff0000089db190
[ 4.070267] [] enable_percpu_irq+0xdc/0xe4
[ 4.071192] [] arm_perf_starting_cpu+0x108/0x10c
[ 4.072200] [] cpuhp_invoke_callback+0x14c/0x4ac
[ 4.073210] [] cpuhp_thread_fun+0xd4/0x11c
[ 4.074132] [] smpboot_thread_fn+0x1b4/0x1c4
[ 4.075081] [] kthread+0x10c/0x138
[ 4.075921] [] ret_from_fork+0x10/0x50
[ 4.076947] genirq: Setting trigger mode 4 for irq 43 failed
(gic_set_type+0x0/0x74)Signed-off-by: Wei Huang
[will: add comment justifying deviation from ACPI spec, removed redundant hunk]
Signed-off-by: Will Deacon
Signed-off-by: Catalin Marinas
11 Apr, 2017
11 commits
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This patch adds framework code to handle parsing PMU data out of the
MADT, sanity checking this, and managing the association of CPUs (and
their interrupts) with appropriate logical PMUs.For the time being, we expect that only one PMU driver (PMUv3) will make
use of this, and we simply pass in a single probe function.This is based on an earlier patch from Jeremy Linton.
Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
Now that we've split the pdev and DT probing logic from the runtime
management, let's move the former into its own file. We gain a few lines
due to the copyright header and includes, but this should keep the logic
clearly separated, and paves the way for adding ACPI support in a
similar fashion.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
[will: rename nr_irqs to avoid conflict with global variable]
Signed-off-by: Will Deacon -
Currently we request (and potentially free) all IRQs for a given PMU in
cpu_pmu_init(). This works for platform/DT probing today, but it doesn't
fit ACPI well as we don't have all our affinity data up-front.In preparation for ACPI support, fold the IRQ request/free into
arm_pmu_device_probe(), which will remain specific to platform/DT
probing.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
Currently we have functions to request/free all IRQs for a given PMU.
While this works today, this won't work for ACPI, where we don't know
the full set of IRQs up front, and need to request them separately.To enable supporting ACPI, this patch splits out the cpu-local
request/free into new functions, allowing us to request/free individual
IRQs.As this makes it possible/necessary to request a PPI once per cpu, an
additional check is added to detect mismatched PPIs. This shouldn't
matter for the DT / platform case, as we check this when parsing.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
For historical reasons, portions of the arm_pmu code use a cpu_pmu_
prefix rather than an armpmu_ prefix. While a minor annoyance, this
hasn't been a problem thusfar.However, to enable ACPI support, we'll need to expose a few things in
header files, and we should aim to keep those consistently namespaced.
In preparation for exporting our IRQ request/free functions, rename
these to have an armpmu_ prefix. For consistency, the 'cpu_pmu'
parameter is also renamed to 'armpmu'.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
In armpmu_dispatch_irq() we look at arm_pmu::plat_device to acquire
platdata, so that we can defer to platform-specific IRQ handling,
required on some 32-bit parts. With the advent of ACPI we won't always
have a platform_device, and so we must avoid trying to dereference
fields from it.This patch fixes up armpmu_dispatch_irq() to avoid doing so, introducing
a new armpmu_get_platdata() helper.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
The ARM PMU framework code always uses armpmu_dispatch_irq as its common
IRQ handler. Passing this down from cpu_pmu_init() is somewhat
pointless, and gets in the way of refactoring.This patch makes cpu_pmu_request_irqs() always use armpmu_dispatch_irq
as the handler when requesting IRQs, and removes the handler parameter
from its prototype.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
Currently arm_pmu_device_probe contains probing logic specific to the
platform_device infrastructure, and some logic required to safely
register the PMU with various systems.This patch factors out the logic relating to the registration of the
PMU. This makes arm_pmu_device_probe a little easier to read, and will
make it easier to reuse the logic for an ACPI-specific probing
mechanism.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
Given we always want to initialise common fields on an allocated PMU,
this patch folds this common initialisation into armpmu_alloc(). This
will make it simpler to reuse this code for an ACPI-specific probe path.Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
We expect an ARM PMU's init function to have a particular prototype,
which we open-code in a few places. This is less than ideal, considering
that we cast a void value to this type in one location, and a mismatch
could easily be missed.Add a typedef so that we can ensure this is consistent.
Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon -
We currently disable the PMU temporarily in armpmu_add(). We may have
required this historically, but the perf core always disables an event's
PMU when calling event::pmu::add(), so this is not necessary.We don't do similarly in armpmu_del(), or elsewhere, so this is
unnecessary and inconsistent, and only serves to confuse the reader.Remove the pointless disable, simplifying armpmu_add() in the process.
Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon
04 Apr, 2017
1 commit
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This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each individual PMU is provided even though all CPUs share all
the slices. User space needs to aggregate to individual counts to provide
a global picture.The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
perf stat -a -e l3cache_0_0/read-miss/
perf stat -a -e l3cache_0_0/event=0x21/Acked-by: Mark Rutland
Signed-off-by: Agustin Vega-Frias
[will: fixed sparse issues]
Signed-off-by: Will Deacon
01 Apr, 2017
3 commits
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For historical reasons, we lazily request and free interrupts in the
arm pmu driver. This requires us to refcount use of the pmu (by way of
counting the active events) in order to request/free interrupts at the
correct times, which complicates the driver somewhat.The existing logic is flawed, as it only considers currently online CPUs
when requesting, freeing, or managing the affinity of interrupts.
Intervening hotplug events can result in erroneous IRQ affinity, online
CPUs for which interrupts have not been requested, or offline CPUs whose
interrupts are still requested.To fix this, this patch splits the requesting of interrupts from any
per-cpu management (i.e. per-cpu enable/disable, and configuration of
cpu affinity). We now request all interrupts up-front at probe time (and
never free them, since we never unregister PMUs).The management of affinity, and per-cpu enable/disable now happens in
our cpu hotplug callback, ensuring it occurs consistently. This means
that we must now invoke the CPU hotplug callback at boot time in order
to configure IRQs, and since the callback also resets the PMU hardware,
we can remove the duplicate reset in the probe path.This rework renders our event refcounting unnecessary, so this is
removed.Signed-off-by: Mark Rutland
[will: make armpmu_get_cpu_irq static]
Signed-off-by: Will Deacon -
When requesting or freeing interrupts, we use platform_get_irq() to find
relevant irqs, backing this up with additional information in an
optional irq_affinity table.This means that our irq request and free paths are tied to a
platform_device, and our request path must jump through a number of
hoops in order to determine the required affinity of each interrupt.Given that the affinity must be static, we can compute the affinity once
up-front at probe time, simplifying the irq request and free paths. By
recording interrupts in a per-cpu data structure, we simplify a few
paths, and permit a subsequent rework of the request and free paths.Signed-off-by: Mark Rutland
[will: rename local nr_irqs variable to avoid conflict with global]
Signed-off-by: Will Deacon -
For historical reasons, we allocate per-cpu data associated with a PMU
rather late, in cpu_pmu_init, after we've parsed whatever hardware
information we were provided with.In order to allow use to store some per-cpu data early in the probe
path, we need to allocate (and initialise) the per-cpu data earlier.
This patch reworks the way we allocate the pmu and associated per-cpu
data in order to make that possible.Signed-off-by: Mark Rutland
[will: make armpmu_{alloc,free} static
Signed-off-by: Will Deacon
02 Mar, 2017
1 commit
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We are going to split out of , which
will have to be picked up from other headers and .c files.Create a trivial placeholder file that just
maps to to make this patch obviously correct and
bisectable.Include the new header in the files that are going to need it.
Acked-by: Linus Torvalds
Cc: Mike Galbraith
Cc: Peter Zijlstra
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar
09 Feb, 2017
1 commit
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Adds perf events support for L2 cache PMU.
The L2 cache PMU driver is named 'l2cache_0' and can be used
with perf events to profile L2 events such as cache hits
and misses on Qualcomm Technologies processors.Reviewed-by: Mark Rutland
Signed-off-by: Neil Leeder
[will: minimise nesting in l2_cache_associate_cpu_with_cluster]
[will: use kstrtoul for unsigned long, remove redunant .owner setting]
Signed-off-by: Will Deacon
04 Feb, 2017
1 commit
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I ran into a build error when I disabled CONFIG_ACPI and tried to
compile this driver:drivers/perf/xgene_pmu.c:1242:1: warning: data definition has no type or storage class
MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
^
drivers/perf/xgene_pmu.c:1242:1: error: type defaults to 'int' in declaration of 'MODULE_DEVICE_TABLE' [-Werror=implicit-int]Include module.h for the MODULE_DEVICE_TABLE macro that's
implicitly included through ACPI.Tested-by: Tai Nguyen
Signed-off-by: Stephen Boyd
Signed-off-by: Will Deacon
25 Dec, 2016
1 commit
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When the state names got added a script was used to add the extra argument
to the calls. The script basically converted the state constant to a
string, but the cleanup to convert these strings into meaningful ones did
not happen.Replace all the useless strings with 'subsys/xxx/yyy:state' strings which
are used in all the other places already.Signed-off-by: Thomas Gleixner
Cc: Peter Zijlstra
Cc: Sebastian Siewior
Link: http://lkml.kernel.org/r/20161221192112.085444152@linutronix.de
Signed-off-by: Thomas Gleixner
