25 Nov, 2019
1 commit
11 Nov, 2019
1 commit
01 Nov, 2019
1 commit
18 Apr, 2019
1 commit
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On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
the 1st linux configure power/clock for the 2nd Linux.When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
to destroy the 2nd linux, then restart the 1st linux, we met SDHCI dump
as following, after we clear the pending interrupt and halt CQCTL, issue
gone.[ 1.334594] mmc2: Got command interrupt 0x00000001 even though no command operation was in progress.
[ 1.334595] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 1.334599] mmc2: sdhci: Sys addr: 0xa05dcc00 | Version: 0x00000002
[ 1.340819] lib80211: common routines for IEEE802.11 drivers
[ 1.345538] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000000
[ 1.345541] mmc2: sdhci: Argument: 0x00018000 | Trn mode: 0x00000033
[ 1.345543] mmc2: sdhci: Present: 0x01f88008 | Host ctl: 0x00000031
[ 1.345547] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080
[ 1.357903] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x0000003f
[ 1.357905] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00000000
[ 1.357908] mmc2: sdhci: Int enab: 0x107f100b | Sig enab: 0x107f100b
[ 1.357911] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502
[ 1.370268] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400
[ 1.370270] mmc2: sdhci: Cmd: 0x00000d1a | Max curr: 0x00ffffff
[ 1.370273] mmc2: sdhci: Resp[0]: 0x00000b00 | Resp[1]: 0xffffffff
[ 1.370276] mmc2: sdhci: Resp[2]: 0x328f5903 | Resp[3]: 0x00d00f00
[ 1.382132] mmc2: sdhci: Host ctl2: 0x00000000
[ 1.382135] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xa2040208[ 2.060932] mmc2: Unexpected interrupt 0x00004000.
[ 2.065538] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 2.071720] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
[ 2.077902] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
[ 2.084083] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000
[ 2.090264] mmc2: sdhci: Present: 0x01f88009 | Host ctl: 0x00000011
[ 2.096446] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080
[ 2.102627] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x000010ff
[ 2.108809] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00004000
[ 2.114990] mmc2: sdhci: Int enab: 0x007f1003 | Sig enab: 0x007f1003
[ 2.121171] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502
[ 2.127353] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400
[ 2.133534] mmc2: sdhci: Cmd: 0x0000371a | Max curr: 0x00ffffff
[ 2.139715] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
[ 2.145896] mmc2: sdhci: Resp[2]: 0x328f5903 | Resp[3]: 0x00d00f00
[ 2.152077] mmc2: sdhci: Host ctl2: 0x00000000
[ 2.156342] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000Signed-off-by: Peng Fan
Reviewed-by: Haibo Chen
15 Apr, 2019
1 commit
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The 'reset' pin used by this panel driver is shared with the touchscreen
driver, which is causing issues during suspend/resume process. In order
to better handle this gpio pin, release its resource during suspend and
acquire it again in resume.Signed-off-by: Robert Chiras
12 Apr, 2019
3 commits
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The overlay fb can only be enabled when the LCDIF is not in
running, otherwise overlay display may look like image shift.
So during the system resume procedure, the overlay fb should
be resumed before mxsfb unblank.Signed-off-by: Fancy Fang
(cherry picked from commit f39662a3a38a2da082d55a006e634766cc85e347) -
Do HW reset for communication port after the port is registered
if the UART controller support the feature.Do partition reset with LPUART's power on, LPUART registers will
keep the previous status, like on i.MX8QM platform, which is not
expected action, so reset the HW is required.Currently, only i.MX7ULP and i.MX8QM LPUART controllers include
global register that support HW reset.Tested-by: Robin Gong
Tested-by: Peng Fan
Reviewed-by: Robby Cai
Signed-off-by: Fugang Duan
(cherry picked from commit c2bc1f62ec28981462c9cb5ceac17134931ca19f) -
edma interrupt maybe happened during reboot or watchdog reset, meanwhile
gic never power down on i.mx8QM/QXP, thus the unexpect irq will come in
once edma driver request irq at probe phase. Unfortunately, at that time
that edma channel's power domain which power-up by customer driver such
as audio/uart driver may not be ready, so kernel panic triggered once
touch such edma registers which still not power up in interrupt handler.
Move request irq from probe to alloc dma channel so that edma channel's
power domain has already been powered, besides, clear meaningless
interrupt before request irq.Signed-off-by: Robin Gong
Acked-by: Fugang Duan
(cherry picked from commit 0a0d8f8b944094342fda18f23f3ac13b8a73871d)
11 Apr, 2019
1 commit
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Add the missing complete operations for dma_completion to fix the
problem of blocking at the wait_for_completion_interruptible()
function in some situations.Signed-off-by: Clark Wang
(cherry picked from commit a19a00c51df5c3ead4d64ea3136f5bce60b2e6af)
10 Apr, 2019
5 commits
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The variable "is_canfd" will stay true after the following sequence:
root@imx8qxpmek:~# ip link set can0 type can bitrate 1000000 dbitrate 4000000 fd on
root@imx8qxpmek:~# ip link set can0 up
root@imx8qxpmek:~# ip link set can0 down
root@imx8qxpmek:~# ip link set can0 type can bitrate 1000000It will use alloc_canfd_skb() to allocate skb for normal CAN when
"is_canfd" is true, which will affect the receive of remote frame.Signed-off-by: Joakim Zhang
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should check imx8-gpu instead of imx8x-gpu string for i.mx8 gpu sub-system
Signed-off-by: Xianzhong
(cherry picked from commit ce6483c43465651469c75b0e5093bdc749866f84) -
Disable typec irq when suspend to avoid the threaded irq to access
some resource(e.g. i2c over rpmsg) but those resource is not
available at later phrase, also use IRQ_DISABLE_UNLAZY flag to
mask the irq on irq chip level when irq happens.Suggested-by: Anson Huang
Acked-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 61869f787fb0ee2f00d0fe9443cb8b487e16e5ec) -
While system suspend, the typec event handling required service
maybe is not available(suspended), so we need freeze those event
handling by using freezable workqueue, e.g while tcpm is handling
PD message but system suspend started.Acked-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 270d4df94b7c2c773a171fe012fb8ce89196964f) -
We should assign dedicated id for every tcon instance.
This makes us be able to figure out bewteen master and
slave tcon. Only side-by-side display mode is likely
impacted. Based on tests, no functional change is
observed before or after this patch is applied.Signed-off-by: Liu Ying
(cherry picked from commit e181d9e56b096bbdc919f65b223d1bde413df1bb)
29 Mar, 2019
3 commits
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CID: 5781508
device pointer should not be used before null checkSigned-off-by: Xianzhong
(cherry picked from commit 17942905375a282ed9896c3cc778a246c321f5f0) -
Vulkan driver has problem to commit command without device mutex,
command object has race condition risk without mutex protection.move _ProcessUserCommandBufferList into command mutex region.
Signed-off-by: Xianzhong
(cherry picked from commit 10120a64fd9342c8effd21eb62bc51f88f1493cb) -
It is only used in this file, so staticize it.
Signed-off-by: Liu Ying
(cherry picked from commit e293f8671509ed54c83a51b40da53da3bdf216f5)
28 Mar, 2019
6 commits
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It isn't used out side of the file for now.
Signed-off-by: Liu Ying
(cherry picked from commit 13a0d5c3b15e42834b872b0da904f874ff717500) -
Due to TKT320590, we are asked to turn TCON into operation mode later after
the first dumb frame is generated by DPU. This makes DPR/PRG be able to
evade the frame. However, it turns out we have to set the TCON into operation
mode first and then wait for Framegen frame counter moving, otherwise, the
display pipeline cannot be setup correctly sometimes(If pixel combiner is used,
one of the two display streams is likely broken). This is a mysterious issue.
So, we've already taken a workaround for the cases where pixel combiner is used.It appears that the similar issue is likely to happen for cases where pixel
combiner is unused. That is to say, if pixel combiner is unused and prefetch
engine is used, the first atomic flush after the enablement is likely to fail -
content shadow load irq doesn't come. The sequence which the patch takes is
the same to the one taken by the previous workaround. Based on tests, it is
valid for cases with or without pixel combiner.Signed-off-by: Liu Ying
(cherry picked from commit b6126aa9697c77896d2085997eec2a6995509f4b) -
To avoid potential division by zero in ipu_init_sync_panel(),
let's check the rounded_pixel_clk rate prior to that.Detected by CoverityScan, CID#56278 ("Division or modulo by zero")
Signed-off-by: Liu Ying
(cherry picked from commit 1523150b71f1aa0610f61ea47a9f3bdbcda92522) -
To avoid potential division by zero in ipu_init_async_panel(),
let's check the di_clk rate prior to that.Detected by CoverityScan, CID#56264 ("Division or modulo by zero")
Signed-off-by: Liu Ying
(cherry picked from commit d7777247e6ba4ca9fcc313bef6672060859fed19) -
To avoid potential out of bounds array access on tbl->used[][],
let's check the tsk->ipu_id prior to that. Based on the context,
this is what we can do to make the coverity happy.Detected by CoverityScan, CID#17689 ("Derefernece before null check")
Signed-off-by: Liu Ying
(cherry picked from commit f5dcf709c54da8e64eb84f1dd7a4452ad8d942cf) -
The check on !sp_tsk0 is unnecessary in ipu_task_thread(), because the
beforehand "list_del(&sp_tsk0->node);" within the context implies sp_tsk0
is not null, otherwise, we'll dereference a null pointer earlier.Detected by CoverityScan, CID#17842 ("Logically dead code")
Signed-off-by: Liu Ying
(cherry picked from commit 9ad5edd076d61bc8bb3a558e523cc7b31f2c3043)
27 Mar, 2019
7 commits
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Double check that the DTG IRQ STATUS register bit is set when handling
the vblank and CTXLD kick interrupts to make sure we avoid spurious
interrupts and kick the CTXLD in a bad moment.Signed-off-by: Laurentiu Palcu
Reviewed-by: Robert Chiras
(cherry picked from commit cc56e4e07f623d0b831e0f8347f2f3198697ee20) -
Using one completion variable is not feasible as we can hit corner cases like
enabling and then quickly disabling DCSS where we end up signaling that DTG was
correctly disabled when, in fact, a VBLANK interrupt was received.Signed-off-by: Laurentiu Palcu
Reviewed-by: Robert Chiras
(cherry picked from commit 8073e87dce34548bea758c34d3b3557819c75551) -
Currently, we set the colorimetry to BT.2020 even if the color-depth is
8 bit. This is not according to HDMI specification.This patch makes sure we follow the specs.
Signed-off-by: Laurentiu Palcu
CC: Sandor Yu
Reviewed-by: Sandor Yu
Reviewed-by: Robert Chiras
(cherry picked from commit cdacfaadd5dccfdca5dd68640d8f08506f6a9114) -
A fixed PLL PMS setting for attached panel is obviously not
enough for any other mipi panel which needs a different PLL
output clock frequency, and besides, for the CEA-861 standard
display modes, the 'pll_pms' table also can not cover all the
modes requirements. So a general way is created to solve this
problem which can provide an optimum solution to output a PLL
bit clock to match the request frequency in a maximum degree
and also satisfy the input clock and intermediate clocks limit
according to the PLL specification.Signed-off-by: Fancy Fang
(cherry picked from commit a73fdd5e48fe0df47685cfc197fe66edc1e28405) -
Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.Signed-off-by: Fancy Fang
(cherry picked from commit a9fafe8108505f8a1580af898ff5fa9c26d03680) -
When there is no existing horizontal blanking word counts in
'dsim_hblank_par' tables, these data requires to be computed
according to the 'hfp', 'hbp' and 'hsa' timings which are in
pixel unit. So the pixel unit data requires to be converted
to word count unit data correctly to match the PLL output clk
frequency.Signed-off-by: Fancy Fang
(cherry picked from commit af9ab0d4362d9298978e2ac62033f65ea1cc09ed) -
Change the 'bit_clk' and 'pix_clk' fields of struct sec_mipi_dsim
and the 'bit_clk' field of struct dsim_pll_pms from 'uint64_t' type
to 'uint32_t' type, since first, these two fields are in KHz unit,
and so 32 bit unsigned integer is enough to hold the data values,
and second, use 32 bit integer can simplify related clocks compute.Signed-off-by: Fancy Fang
(cherry picked from commit 3e62c748a531ca5eacbf6a616d3a979be5222b9c)
25 Mar, 2019
1 commit
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Since, the partition reset irq would be triggered anytime.
Do not read the status of the MU if master side is in suspend mode.Signed-off-by: Richard Zhu
(cherry picked from commit 117dbcb1ce258587f8d162c0b3219f32d6de6fbc)
24 Mar, 2019
7 commits
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Coverity reported potential arithmetic overflow of a 32-bit
multiply operation. Adding a cast to promote the mulitply opertion to use
64 bits.Signed-off-by: Oliver Brown
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Coverity reported a potential divide by zero. Adding a check to prevent
a divide by zero.Signed-off-by: Oliver Brown
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Fixed a dead code error reported by Coverity.
CID 1826265: Logically dead codeSigned-off-by: Oliver Brown
(cherry picked from commit 4b25b038a2278b0782e144ec3e3907fbcbc138c1) -
Fixed two issues resported by Coverity:
CID 343354: Uninitialized scalar variable
CID 343355: Uninitialized scalar variableSigned-off-by: Oliver Brown
(cherry picked from commit abc359e835dca5942d9dc101bfdc55f243e01d65) -
Fixed CID 3411368, Unsigned compared against 0. Removed comparison with
no effect.Signed-off-by: Oliver Brown
(cherry picked from commit 7a90cb82d00109cdd00eea67fbf9d75b6efe6172) -
Fixed CID 17375, Unsigned compared against 0. Removed code with no effect.
Signed-off-by: Oliver Brown
(cherry picked from commit b86debc52acd4131515f62130f52c2d0f48cdbfe) -
Fix Covertity CID 18110 Uninitialized scalar variable
Signed-off-by: Oliver Brown
(cherry picked from commit 0f2a05c5cef95dabdbdd1e78531cd42aec24876a)
23 Mar, 2019
1 commit
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Some rpmsg user may require rpmsg resume before the user start
handle its irq, e.g the typec controller use a GPIO as irq and
use rpmsg to get event status, so move imx rpmsg power management
ops to noirq phrase.Reviewed-by: Richard Zhu
Tested-by: Clark Wang
Signed-off-by: Anson Huang
Signed-off-by: Li Jun
22 Mar, 2019
1 commit
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Changing error message "Link rate is too high - forcing link to lower rate"
to a debug message "Lowering DP link rate from to ".Signed-off-by: Oliver Brown