23 May, 2018
1 commit
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commit efc4a13724b852ddaa3358402a8dec024ffbcb17 upstream.
Currently the 32-bit device address only is supported for DMA. However,
starting from Intel Sunrisepoint PCH the DMA address of the device FIFO
can be 64-bit.Change the respective variable to be compatible with DMA engine
expectations, i.e. to phys_addr_t.Fixes: 34cadd9c1bcb ("spi: pxa2xx: Add support for Intel Sunrisepoint")
Signed-off-by: Andy Shevchenko
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman
04 Aug, 2017
1 commit
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We still need to request/free GPIOs passed via the legacy path of
pxa2xx_spi_chip::gpio_cs, but we can use the gpiod API otherwise.Consistently use the descriptor API instead of the legacy one.
Signed-off-by: Jan Kiszka
Acked-by: Mika Westerberg
Signed-off-by: Mark Brown
14 Nov, 2016
1 commit
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IS_DMA_ALIGNED() became unused by the commit 6356437e65c2
("spi: spi-pxa2xx: remove legacy PXA DMA bits").Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
27 Sep, 2016
1 commit
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The driver uses custom chip_info coming from platform data for chip selects
implemented as GPIOs. If the system lacks board files setting up the
platform data, it is not possible to use GPIOs as chip selects.This adds support for GPIO descriptors so that regardless of the underlying
firmware interface (DT, ACPI or platform data) the driver can request GPIOs
used as chip selects and configure them accordingly.The custom chip_info GPIO support is still left there to make sure the
existing systems keep working as expected.Signed-off-by: Mika Westerberg
Signed-off-by: Mark Brown
13 Sep, 2016
2 commits
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Transfer state machine in this driver does not need to set/unset pointer
to chip data between queueing and finalizing message as it is not
actually used as a state info itself but just pointer passing.Since this per SPI device specific chip data is already carried in
ctldata use that and remove pointer to chip data from driver data.While at it, group initialized variables before uninitialized variables
in pump_transfers().Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown -
There is no need to carry pointer to current SPI message in driver data
because cur_msg in struct spi_master holds it already when driver is using
the message queueing infrastructure from the SPI core.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
22 Jun, 2016
1 commit
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SPI core provides DMA mapping with scatterlists. Start using it instead
of own implementation in spi-pxa2xx. Major difference in addition to
bunch of removed boilerplate code is that SPI core does
mapping/unmapping for all transfers in a message before and after the
message sending where spi-pxa2xx did mapping/unmapping for each
transfers separately.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
28 Mar, 2016
2 commits
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Dummy buffer is used for half duplex transfers that don't have TX or RX
buffer set. Instead of own dummy buffer management here let the SPI core to
handle it by setting the SPI_MASTER_MUST_RX and SPI_MASTER_MUST_TX flags.
Then core makes sure both transfer buffers are set.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown -
spi-pxa2xx-dma.c DMA engine implementation stopped using PIO for
unaligned trailing bytes in the commit 111e0a9dc71e ("spi/pxa2xx: Prevent
DMA from transferring too many bytes"). This means there is no need to
update tx/rx transfer buffer pointers after DMA completion. These buffer
pointers will be set to new buffers when handling the next transfer.Because this buffer pointer update was only remaining use for rx_map_len
and tx_map_len members in struct driver_data after removing the legacy PXA
DMA implementation they can be removed now.Signed-off-by: Jarkko Nikula
Acked-by: Robert Jarzmik
Signed-off-by: Mark Brown
21 Feb, 2016
1 commit
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Only legacy PXA DMA implementation was using these rx_dma and tx_dma DMA
addresses so they are not needed after commit 6356437e65c2
("spi: spi-pxa2xx: remove legacy PXA DMA bits").Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
16 Jan, 2016
1 commit
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After removal of legacy PXA DMA code by the commit 6356437e65c2
("spi: spi-pxa2xx: remove legacy PXA DMA bits") the
CONFIG_SPI_PXA2XX_DMA follows the CONFIG_SPI_PXA2XX and cannot be disabled
alone. Therefore remove this config symbol and dead definitions from the
spi-pxa2xx.h.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
04 Nov, 2015
1 commit
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…pi/topic/owner', 'spi/topic/pxa' and 'spi/topic/pxa2xx' into spi-next
03 Oct, 2015
1 commit
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It is not used since commit 8d94cc50aa4f ("[PATCH] spi: stabilize PIO mode
transfers on PXA2xx systems").Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
02 Oct, 2015
1 commit
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This was leftover from the legacy pxa2xx DMA implementation and not needed
anymore so remove it.Signed-off-by: Mika Westerberg
Signed-off-by: Mark Brown
26 Sep, 2015
1 commit
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Carry input clock of the controller in max_speed_hz of struct spi_master
instead of in own driver data. They mean the same thing and more over now
the max_speed_hz is not even set here.As an added bonus this allows SPI core to validate that transfer speed is
not beyond the maximum input clock. This is not a problem in spi-pxa2xx as
the driver doesn't use transfer speed parameter directly but via input
clock divider calculation which will top at divide by one. However it's
better to validate speed before passing it here.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
18 Sep, 2015
2 commits
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There hasn't been need to carry chip->cr0 after SPI core started to
validate speed_hz and bits_per_word transfer parameters. That effectively
caused that pump_transfers() always recalculated it and practically
chip->cr0 is used locally in setup() for debug prints only.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown -
There is no need to carry spi->max_speed_hz and spi->bits_per_word from
setup() in "struct chip_data" since pump_transfers() will anyway take the
transfer parameters from "struct spi_transfer". This is since SPI core
validates both bits_per_word and speed_hz transfer parameters and defaults
to spi->bits_per_word and spi->max_speed_hz in case these per transfer
parameters are not set.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
05 Aug, 2015
1 commit
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Remove null_dma_buf variable and extra allocation for it. It is not needed
since commit 6356437e65c2 ("spi: spi-pxa2xx: remove legacy PXA DMA bits").Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
04 Aug, 2015
1 commit
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These became unused by the commit 6356437e65c2
("spi: spi-pxa2xx: remove legacy PXA DMA bits").Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
09 Jun, 2015
1 commit
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Generic DMA support was already implemented by commit cd7bed003404
("spi/pxa2xx: break out the private DMA API usage into a separate file")
which moved all the legacy PXA DMA implementation code into its own
file.With generic DMA available for PXA, we can now just trash this file.
Signed-off-by: Daniel Mack
Acked-by: Mark Brown
[respin after pxa dmaengine support upstream]
Signed-off-by: Robert Jarzmik
Acked-by: Mika Westerberg
Signed-off-by: Mark Brown
23 Dec, 2014
1 commit
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Currently SSP registers are accessed by having an own read and write macros
for each register. For instance read_SSSR(iobase) and write_SSSR(iobase).In my opinion this hurts readability and requires new macros to be defined
for each new added register. Let's define and use instead common
pxa2xx_spi_read() and pxa2xx_spi_write() accessors.Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
27 Nov, 2014
1 commit
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There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable the SPI for
Intel Quark X1000.This piece of work is derived from Dan O'Donovan's initial work for Intel Quark
X1000 SPI enabling.Reviewed-by: Andy Shevchenko
Acked-by: Mika Westerberg
Signed-off-by: Weike Chen
Signed-off-by: Mark Brown
08 Feb, 2013
3 commits
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Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it
has few additional features over the original:o FIFO depth is 256 entries
o RX FIFO has one watermark
o TX FIFO has two watermarks, low and high
o chip select can be controlled by writing to a registerThe new FIFO registers follow immediately the PXA27xx registers but then there
are some additional LPSS private registers at offset 1k or 2k from the base
address. For these private registers we add new accessors that take advantage
of drv_data->lpss_base once it is resolved.We add a new type LPSS_SSP that can be used to distinguish the LPSS devices
from others.Signed-off-by: Mika Westerberg
Tested-by: Lu Cao
Signed-off-by: Mark Brown -
To be able to use DMA with this driver on non-PXA platforms we implement
support for the generic DMA engine API. This lets user to use different DMA
engines with little or no modification to the driver.Request lines and channel numbers can be passed to the driver from the
platform specific data.The DMA engine implementation will be selected by default even on PXA
platform. User can select the legacy DMA API by enabling Kconfig option
CONFIG_SPI_PXA2XX_PXADMA.Signed-off-by: Mika Westerberg
Acked-by: Linus Walleij
Tested-by: Lu Cao
Signed-off-by: Mark Brown -
The PXA SPI driver uses PXA platform specific private DMA implementation
which does not work on non-PXA platforms. In order to use this driver on
other platforms we break out the private DMA implementation into a separate
file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA
functions are stubbed out if there is no DMA implementation selected (i.e
we are building on non-PXA platform).While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they
are not needed anymore for CE4100.Once this is done we can add the generic DMA engine support to the driver
that allows usage of any DMA controller that implements DMA engine API.Signed-off-by: Mika Westerberg
Acked-by: Linus Walleij
Tested-by: Lu Cao
Signed-off-by: Mark Brown