11 Jan, 2012
1 commit
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…ium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next
08 Dec, 2011
4 commits
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Add new processor ID to asm/cpu.h and kernel/cpu-probe.c.
Update to new CPU frequency detection code which works on XLP 3XX
and 8XX.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2971/
Signed-off-by: Ralf Baechle -
Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.hSigned-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2966/
Signed-off-by: Ralf Baechle -
Use r4k_wait as the CPU wait function for XLR/XLS processors.
Signed-off-by: Jayachandran C
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2728/
Signed-off-by: Ralf Baechle -
Add basic support for the Au1300 variant(s):
- New GPIO/Interrupt controller
- DBDMA ids
- USB setup
- MMC support
- enable various PSC drivers
- detection code.Signed-off-by: Manuel Lauss
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2866/
Signed-off-by: Ralf Baechle
07 Nov, 2011
1 commit
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* 'modsplit-Oct31_2011' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: (230 commits)
Revert "tracing: Include module.h in define_trace.h"
irq: don't put module.h into irq.h for tracking irqgen modules.
bluetooth: macroize two small inlines to avoid module.h
ip_vs.h: fix implicit use of module_get/module_put from module.h
nf_conntrack.h: fix up fallout from implicit moduleparam.h presence
include: replace linux/module.h with "struct module" wherever possible
include: convert various register fcns to macros to avoid include chaining
crypto.h: remove unused crypto_tfm_alg_modname() inline
uwb.h: fix implicit use of asm/page.h for PAGE_SIZE
pm_runtime.h: explicitly requires notifier.h
linux/dmaengine.h: fix implicit use of bitmap.h and asm/page.h
miscdevice.h: fix up implicit use of lists and types
stop_machine.h: fix implicit use of smp.h for smp_processor_id
of: fix implicit use of errno.h in include/linux/of.h
of_platform.h: delete needless include
acpi: remove module.h include from platform/aclinux.h
miscdevice.h: delete unnecessary inclusion of module.h
device_cgroup.h: delete needless include
net: sch_generic remove redundant use of
net: inet_timewait_sock doesnt need
...Fix up trivial conflicts (other header files, and removal of the ab3550 mfd driver) in
- drivers/media/dvb/frontends/dibx000_common.c
- drivers/media/video/{mt9m111.c,ov6650.c}
- drivers/mfd/ab3550-core.c
- include/linux/dmaengine.h
01 Nov, 2011
2 commits
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These files are not modules, but were including module.h only for
EXPORT_SYMBOL and/or THIS_MODULE. Now that we have the lightweight
export.h, use it in these kinds of cases.Signed-off-by: Paul Gortmaker
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We are relying on asm/elf.h being present implicitly. Once we clean
up the root cause of that, we'll see this, so fix it in advance.arch/mips/kernel/cpu-probe.c: In function 'set_elf_platform':
arch/mips/kernel/cpu-probe.c:298: error: '__elf_platform' undeclared (first use in this function)Signed-off-by: Paul Gortmaker
25 Oct, 2011
1 commit
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Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium().
Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2777/
Signed-off-by: Ralf Baechle
26 Jul, 2011
1 commit
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Signed-off-by: Ralf Baechle
To: Sergei Shtylyov
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2391/
Signed-off-by: Ralf Baechle
19 May, 2011
4 commits
-
Signed-off-by: Robert Millan
Acked-by: David Daney
Signed-off-by: Kevin Cernekee
Cc: David Daney
Cc: wu zhangjin
Cc: Aurelien Jarno
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2302/
Signed-off-by: Ralf Baechle -
Signed-off-by: Kevin Cernekee
Cc: Robert Millan
Cc: David Daney
Cc: wu zhangjin
Cc: Aurelien Jarno
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2300/
Signed-off-by: Ralf Baechle -
Replace these sequences:
if (cpu == 0)
__elf_platform = "foo";with a trivial inline function.
Signed-off-by: Robert Millan
Signed-off-by: Kevin Cernekee
Signed-off-by: David Daney
Cc: wu zhangjin
Cc: Aurelien Jarno
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2304/
Patchwork: https://patchwork.linux-mips.org/patch/2374/
Signed-off-by: Ralf Baechle -
Add Netlogic Microsystems company ID and processor IDs for XLR
and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2367/
Signed-off-by: Ralf Baechle
19 Jan, 2011
1 commit
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Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo.
Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1877/
Signed-off-by: Ralf Baechle
17 Dec, 2010
1 commit
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BCM4710 uses the BMIPS32 core (like BCM6345), not the MIPS 4Kc core as
was previously believed.Signed-off-by: Kevin Cernekee
Tested-by: Alexandros C. Couloumbis
Patchwork: https://patchwork.linux-mips.org/patch/1837/
Signed-off-by: Ralf Baechle
30 Oct, 2010
3 commits
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The TASK_SIZE macro should reflect the size of a user process virtual
address space. Previously for 64-bit kernels, this was not the case.
The immediate cause of pain was in
hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes
trying to mmap a huge page would be served a page with an address
outside of the 32-bit address range. But there are other uses of
TASK_SIZE in the kernel as well that would like an accurate value.The new definition is nice because it now makes TASK_SIZE and
TASK_SIZE_OF() yield the same value for any given process.For 32-bit kernels there should be no change, although I did factor
out some code in asm/processor.h that became identical for the 32-bit and
64-bit cases.__UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels.
This should eliminate the possibility of getting a
AddressErrorException in the kernel for addresses that pass the
access_ok() test.With the patch applied, I can still run o32, n32 and n64 processes,
and have an o32 shell fork/exec both n32 and n64 processes.Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1701/ -
BMIPS processor cores are used in 50+ different chipsets spread across
5+ product lines. In many cases the chipsets do not share the same
peripheral register layouts, the same register blocks, the same
interrupt controllers, the same memory maps, or much of anything else.But, across radically different SoCs that share nothing more than the
same BMIPS CPU, a few things are still mostly constant:SMP operations
Access to performance counters
DMA cache coherency quirks
Cache and memory bus configurationSo, it makes sense to treat each BMIPS processor type as a generic
"building block," rather than tying it to a specific SoC. This makes it
easier to support a large number of BMIPS-based chipsets without
unnecessary duplication of code, and provides the infrastructure needed
to support BMIPS-proprietary features.Signed-off-by: Kevin Cernekee
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli
Patchwork: https://patchwork.linux-mips.org/patch/1706/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org -
The OCTEON II ISA extends the original OCTEON ISA, so give it its own
__elf_platform string so optimized libraries can be selected in
userspace.Signed-off-by: David Daney
Patchwork: http://patchwork.linux-mips.org/patch/1665/
Signed-off-by: Ralf Baechle
05 Aug, 2010
2 commits
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The struct cpuinfo_mips.core field should be populated with the
physical core number. For R2 CPUs, this is carried in the low 10 bits
of Ebase.Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1505/
Signed-off-by: Ralf Baechle -
Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.Signed-off-by: Lars-Peter Clausen
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/
Signed-off-by: Ralf Baechle
22 May, 2010
1 commit
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The "nofpu" and "nodsp" kernel command line options currently do not
affect CPUs that are brought online later in the boot process or
hotplugged at runtime. It is desirable to apply the nofpu/nodsp options
to all CPUs in the system, so that surprising results are not seen when
a process migrates from one CPU to another.[Ralf: Moved definitions of mips_fpu_disabled, fpu_disable,
mips_dsp_disabled and dsp_disable from setup.c to cpu-probe.c to allow
making mips_fpu_disabled and mips_dsp_disabled static.]Signed-off-by: Kevin Cernekee
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1169/
Signed-off-by: Ralf Baechle
27 Feb, 2010
5 commits
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This allows us to treat them differently at runtime.
Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle -
Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/892/
Signed-off-by: Ralf Baechle -
The userspace runtime linker uses the elf_platform to find the libraries
optimized for the current CPU archecture variant. First we need to allow it
to be set to something other than NULL. Follow-on patches will set some
values for specific CPUs.GLIBC already does the right thing. The kernel just needs to supply good
data.Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/891/
Signed-off-by: Ralf Baechle -
Signed-off-by: Roel Kluin
To: linux-mips@linux-mips.org
To: Andrew Morton
To: LKML
Patchwork: http://patchwork.linux-mips.org/patch/860/
Signed-off-by: Ralf Baechle -
For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/866/
Signed-off-by: Ralf Baechle
11 Feb, 2010
1 commit
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The patch that adds cpu_probe_vmbits is erroneously writing to reserved
bit 12. Since we are really only probing high bits, don't write this bit
with a one.Signed-off-by: David Daney
To: linux-mips@linux-mips.org
Cc: Guenter Roeck
Patchwork: http://patchwork.linux-mips.org/patch/949/
Acked-by: Guenter Roeck
Signed-off-by: Ralf Baechle
03 Feb, 2010
1 commit
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Linux kernel 2.6.32 and later allocate address space from the top of the
kernel virtual memory address space.This patch implements virtual memory size detection for 64 bit MIPS CPUs
to avoid resulting crashes.Signed-off-by: Guenter Roeck
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/935/
Reviewed-by: David Daney
Signed-off-by: Ralf Baechle
17 Dec, 2009
1 commit
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Loongson 2F supports CPU clock scaling. When put it into wait mode by
setting the frequency as ZERO it will stay in this mode until an external
interrupt wakes the CPU again.To enable clock scaling support, an external timer of a known stable rate
is required.Signed-off-by: Wu Zhangjin
Cc: linux-mips@linux-mips.org
Cc: cpufreq@vger.kernel.org,
Cc: Dave Jones ,
Cc: Dominik Brodowski ,
Cc: yanh@lemote.com
Cc: huhb@lemote.com,
Patchwork: http://patchwork.linux-mips.org/patch/660/
Patchwork: http://patchwork.linux-mips.org/patch/751/
Signed-off-by: Ralf Baechle
02 Nov, 2009
1 commit
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Signed-off-by: Chris Dearman
Signed-off-by: Ralf Baechle
18 Sep, 2009
3 commits
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Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway.
Signed-off-by: Maxime Bizon
Signed-off-by: Ralf Baechle -
Signed-off-by: Ralf Baechle
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Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the
Alchemy-specific wait code before timer initialization; if the C0
timer must be used for timekeeping the wait function is set to NULL
which means no wait implementation is available.As a sideeffect, the 'wait instruction available' output in
/proc/cpuinfo now correctly indicates whether 'wait' is usable.Run-tested on DB1200.
Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle
25 Jun, 2009
1 commit
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Some of the were relying into smp.h being dragged in by another header
which of course is fragile. uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.Signed-off-by: Ralf Baechle
30 Mar, 2009
1 commit
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This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization. The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle
12 Mar, 2009
1 commit
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Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.Here're some VR5500A spec notes:
* All execution hazards are handled in hardware.
* Once VR5500A stops the operation of the pipeline by WAIT instruction,
it could return from the standby mode only when either a reset, NMI
request, or all enabled interrupts is/are detected. In other words,
if interrupts are disabled by Status.IE=0, it keeps in standby mode
even when interrupts are internally asserted.Notes on WAIT: The operation of the processor is undefined if WAIT
insn is in the branch delay slot. The operation is also undefined
if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.* VR5500A core only implements the Load prefetch.
With these changes, it boots fine.
Signed-off-by: Shinya Kuribayashi
Signed-off-by: Ralf Baechle
11 Jan, 2009
2 commits
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Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device. As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.Signed-off-by: Manuel Lauss
Signed-off-by: Ralf Baechle -
Add OCTEON constants to asm/cpu.h and asm/module.h.
Add probe function for Cavium OCTEON CPUs and hook it up.
Signed-off-by: Tomaso Paoletti
Signed-off-by: David Daney
Signed-off-by: Ralf Baechle
30 Oct, 2008
1 commit
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As noticed by David Daney , the old long switch
statement did not comply with the Linux C coding style. It was also yet
another place of code to be changed when adding a new processor type
leading to annoying bugs for example in /proc/cpuinfo.Fixed by moving the setting of the CPU type string into the core of the
probing code and a few BUG_ON() test to ensure the CPU probing code indeed
did its job and removing multiple now redundant tests.Signed-off-by: Ralf Baechle