06 Aug, 2019
1 commit
-
Add quirk for cyw4356 to disable D3 mode because current firmware
still doesn't support D3 mode.After stress test, cyw4356 D3 mode still has timeout issue, so
cherry pick back the commit.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit 22212c60d7fb067e28a2fed16914515e3d6d3950)
23 Jul, 2019
1 commit
-
drivers/pci/controller/dwc/pci-imx6.c:2826:2: error: implicit
declaration of function ‘pci_imx_set_msi_en’
[-Werror=implicit-function-declaration]
pci_imx_set_msi_en(&pci->pp);
^
drivers/pci/controller/dwc/pci-imx6.c: At top level:
drivers/pci/controller/dwc/pci-imx6.c:2857:10: error:
‘pci_imx_pm_ops’ undeclared here (not in a function)
.pm = &pci_imx_pm_ops,
^
cc1: some warnings being treated as errorsSigned-off-by: Richard Zhu
24 May, 2019
2 commits
-
The MSI Enable bit controls delivery of MSI interrupts from components
below the Root Port.
This bit would be lost during the suspend, should be re-configured
during resume.Signed-off-by: Richard Zhu
-
iMX8M PCIe doesn't need to touch GPC, since they are contained in the
power domain operations already.Signed-off-by: Richard Zhu
Acked-by: Fugang Duan
22 May, 2019
1 commit
-
Setup PCI its own HSIO regmap to fix the kernel dump, when the HSIO
regmap is set as system syscon.
/sys/kernel/debug/regmap# cat dummy-hsio@5f080000/registerNOTE: devm_ioremap is used to get the virtual address, because that the
devm_ioremap_resource would return -EBUSY when there is a resource
overlap between different HSIO consumers.Signed-off-by: Richard Zhu
07 May, 2019
1 commit
-
There is redundant attrs registration in ep's probe.
Maybe introduced by the merge conflication.
Remove them to fix the probe failure.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
02 May, 2019
3 commits
-
Remove the quirk for disable cyw4356 D3 mode since current FW
already support it.
This revert the commit 28db0ac248b3("MLK-20716 PCI: add quirk for
cyw4356 to disable D3 mode")Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit d0e2c4b0b66e46b2f33633efdea19af6241f95ef) -
Add quirk for cyw4356 to disable D3 mode because current firmware
still doesn't support D3 mode.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit 22212c60d7fb067e28a2fed16914515e3d6d3950) -
This reverts commit 2a031cab71cd9909fa659c96b6221d1fe33ad87f.
Signed-off-by: Shrikant Bobade
(cherry picked from commit 91d66f481121b2eab56f5d829a0002f6bb47953e)
18 Apr, 2019
31 commits
-
MSI is broken on CYW4356/4359 chips. This causes CYW4356 1CX not
work on i.MX8x platforms with bandwidth test. It is known issue
that i.MX8x PCIe host driver MSI interrupt lost.Disable MSI completely for this chipset to let wifi can stable work
until PCIe RC driver fix the issue.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
(cherry picked from commit d99766187fb99d4a6655a1e0fdf5dc9451a8e4a0) -
Turn on the power on gpio once is enough and this pin shouldn't be
re-configured in resume procedure again and again.
Thus, move the turn on operation of the power_on_gpio to the proper
place.Signed-off-by: Richard Zhu
Acked-by: Fugang Duan -
Upstream rejected ARCH_MXC_ARM64 in favor of defining ARCH_MXC for
arm64.Simplify PCI_IMX6 "depends on" to just "ARCH_MXC || COMPILE_TEST" and
make it actually build on imx8.Fixes: 2c3ecbe0d6a4 ("MLK-15064-4 PCI: imx: enable pcie support on imx8")
Signed-off-by: Leonard Crestez
-
Use the external osc as the pcie refclk on 8mm evk board.
- Do not turn off the over ride of rc's clkreq#, when
L1SS is not enabled.
NOTE: L1SS_EN would be set at both RC and EP by
pcie_config_aspm_link when the L1SS is supported
by the link.Signed-off-by: Richard Zhu
-
- replace the sleep by the udelay, since it would be used
in the no_irq_suspend/resume callbacks.
- aligned the retries to the PHY_PLL_LOCK_WAIT_MAX_RETRIESSigned-off-by: Richard Zhu
(Vipul: apply manually while rebase on v4.19)
Signed-off-by: Vipul Kumar -
Make sure that the sysfile api of the pcie ep is add properly.
Signed-off-by: Richard Zhu
Acked-by: Fugang Duan
(Vipul: apply manually whilre rebase on v4.19)
Signed-off-by: Vipul Kumar -
In the EP RC validation system, EP wouldn't set RC's
CLK_REQ# to low, like one real inserted EP device to do.
Let RC to set the over ride low and enabled, make sure that
REF_CLK of RC side is turned on.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
(cherry picked from commit 9dbd35f429a8383b13ca758fd14c6dad926e16e6)
rebase on v4.19
Signed-off-by: Vipul Kumar -
- Do not de-assert the clkreq# when compliance tests mode
is enabled, make sure that the ref_clk is turned on.
- Correct the PLL lock bit check point.
- Adjust the TRSV PHY registers to pass the compliance tests.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Enable the L1.1 ASPM support on iMX8MM, and
verified the EVK board.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
- Enable the L1.1 ASPM support on iMX8MQ, and verified
on the both PCIe ports of the EVK board.
- Fix the L1 exit latency larger than 64us issue
Otherwise, the L1/L1.1 ASPM would be disabled in the
initialization.
- Add the internal PLL of the PCIe REF_CLK support, and
verify the L1.1 ASPM on port0 of 8MQ EVK boardSigned-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
- warning: ‘retries’ may be used uninitialized in this function
- WARNING: vmlinux.o(.data+0x5d2d8): Section mismatch in reference from the
variable imx_pcie_driver to the function .init.text:imx_pcie_probe()The variable imx_pcie_driver references the function __init
imx_pcie_probe().
If the reference is valid then annotate the variable with
__init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_consoleSigned-off-by: Jason Liu
Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Fix the crash when pcie request the reserved memory region
after the -EPROBE_DEFER in the probe.
The pointer of the resource parameter would be invalided
in the second probe. Use one structure varible to replace
it.
Put node after done with it, after call of_parse_phandle.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
PCIe ep rc validation is one remote processors communications.
Remove the hard-coded ep rc ddr test region on imx8 platforms.
Get the reserved region for ep rc ddr test region.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
iThe perst signal shouldn't be asserted during imx6q/dl
pcie suspend.
Otherwise, the link would be down during resume,
and system would be hang.
Fix it by one return in imx6q switch case.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
enable imx8mm pcie support.
BTW, the power management is not supported yet.
Disable pcie module, if you test power management
on the imx8mm platforms.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
- They should be bitwise logic, not the boolean logic.
- Correct the error return values.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Replace the specific name imx6_xxx by imx_xxx.
Since all imx6/7/8 PCIe use the same driver.Signed-off-by: Richard Zhu
During 4.14 rebase remade this manually
Signed-off-by: Leonard Crestez
rebase on v4.19
Signed-off-by: Vipul Kumar -
Enable the imx pcie ep dma in the pcie ep rc
validation system.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Failed to verify the MSI in the EP RC system.
Root cause: the MSI address is not fetched corretly.
The second port of iMX8MQ EVK board should be used
as EP port, not the first one.Signed-off-by: Richard Zhu
Reviewed-by: Frank Li
rebase on v4.19
Signed-off-by: Vipul Kumar -
Enable the PCIE EP RC for iMX8
RC access memory of EP:
- EP:
write the to the bar0 of ep.
- RC:
access the , and this address
would be mapped to the of ep.
Note:
ddr_region_address mem_base_addr bar0_addr
imx8mq 0xb820_0000 0x2000_0000 0x33c0_0010
imx8qxp 0xb820_0000 0x6000_0000 0x5f00_0010
imx8qm 0xb820_0000 0x7000_0000 0x5f01_0010MSI verification:
- EP:
write 0 to the , for example ./memtool -32 =0
- RC:
check the msi is triggered or not.
cat /proc/interrupts | grep msi
Note:
The msi_addr can be get by the following command after RC platform
is boot up.
For example
root@imx8_all:~# dmesg | grep msi_addr
[ 2.670247] pci_msi_addr = 0x7ff80000, cpu_base 0x80000000msi_addr
imx8mq 0x27f8_0000
imx8qxp 0x6ff8_0000
imx8qm 0x7ff8_0000iMX8QM:
BuildInfo:
- SCFW daabd5d3, IMX-MKIMAGE 0ad6069a, ATF 93dd1cc
- U-Boot 2017.03-imx_v2017.03+gc662e0a
iMX8QXP:
BuildInfo:
- SCFW daabd5d3, IMX-MKIMAGE 0ad6069a, ATF 93dd1cc
- U-Boot 2017.03-imx_v2017.03+gc662e0aSigned-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
To support the bus freq power saving mode, add the
sysfile interface.
request bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freq
release bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freqSigned-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Return the error when the pll is not locked.
Signed-off-by: Richard Zhu
Reviewed-by: Frank Li
rebase on v4.19
Signed-off-by: Vipul Kumar -
Enable the pcie pm on imx8qm/qxp
Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Enable the PCIE PM on mScale.
- Refine the codes.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Driver should do defer probing if .of_get_named_gpio() returns
-EPROBE_DEFER. And moving epdev_on regulator to be common for all
platforms.(BuildInfo: SCFW 3e70523d, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Fugang Duan
Reviewed-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Add the epdev_on regulator to power up the WiFi module
on the iMX8QM board.
This regulator needs to be powered up before the pcie
link, in order for the WiFi module to work.Signed-off-by: Fugang Duan
Signed-off-by: Tiberiu Breanarebase on v4.19
Signed-off-by: Vipul Kumar -
Description:
Initial VCO oscillation may fail under corner conditions such as
cold temperature. It causes PCIe PLL fail to lock in
initialization phase.Project Impact:
iMX7D PCIe PLL fails to lock and PCIe doesn.t work.workarounds:
To disable Duty-cycle Corrector(DCC) calibration after G_RST
signal is de-asserted by following the sequences:
1. De-assert the G_RST signal by clearing
SRC_PCIEPHY_RCR[PCIEPHY_G_RST].
2. de-assert DCC_FB_EN in Reg4 by writing data '0x29' to the register
address 0x306d0014.
3. assert RX_EQS, RX_EQ_SEL in Reg24 by writing data '0x48' to the
register address 0x306d0090.
4.assert ATT_MODE in Reg26 by writing data '0xbc' to the register
address 0x306d0098.
5.De-assert the CMN_RST signal by clearing register bit
SRC_PCIEPHY_RCR[PCIEPHY_BTN].Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
- correct the msi address
- only do shutdown reset for imx6q pcie, since only
imx6qdl pcie doesn't have the reset mechanism.
- don't limit the max link speed of imx pcie to gen2Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
In order to make sure that get the regulator correctly.
Check the return value of devm_regulator_get().
Return value directly if it is '-EPROBE_DEFER'Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
Root cause:
Poewr domain of the PCIEs are turned off, and
not turned on properly in previous ATF.The PDs of PCIE1/2 have the dependency.
Both of the PDs should be operated at same time.
This issue is gone after update the PDs operations
in ATF.
In order to make sure that the PDs are turned on,
Turn power domain for imx8mq pcie explicitly in
driver.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar -
On iMX8QM, functions of PCIEB relied on PCIEA.
But PCIEB used on iMX8QXP can work standalone.
Specify the iMX8QXP PCIE in driver.
Up to now, only iMX6QP PCIE may use the EXT OSC,
specify the EXT/EXT_SRC clocks for iMX6QP only.Signed-off-by: Richard Zhu
rebase on v4.19
Signed-off-by: Vipul Kumar
