27 Mar, 2019

1 commit

  • Add a new property 'pref-rate' support which can be used to
    assign a different clock frequency for the DPHY PLL reference
    clock in the dtb file. And if this property does not exist,
    the default clock frequency for the reference clock will be
    used. And according to the spec, the DPHY PLL reference clk
    frequency should be in [6MHz, 300MHz] range.

    Signed-off-by: Fancy Fang
    (cherry picked from commit a9fafe8108505f8a1580af898ff5fa9c26d03680)

    Fancy Fang
     

22 Feb, 2019

1 commit

  • Add virtual i2c driver to send SRTM i2c messages to M4.
    Each virtual I2C bus has a specal bus id, which is abstracted by M4.
    Each SRTM message include a bus id for the bus which the device is on.

    Virtual i2c rpmsg bus will bind rpbus nodes with compatible string
    "fsl,i2c-rpbus". And "rpmsg-i2c-channel" will probe only one rpmsg
    channel for all rpbuses.

    This virtual i2c driver depends on CONFIG_I2C and CONFIG_RPMSG.

    Signed-off-by: Clark Wang

    Clark Wang
     

12 Feb, 2019

38 commits