06 Jul, 2015

1 commit


18 Apr, 2015

1 commit


22 Dec, 2014

1 commit


06 Dec, 2014

1 commit


22 May, 2014

1 commit


21 May, 2014

1 commit


17 Mar, 2014

1 commit

  • As discussed in [1] the tasklet_disable is not a proper function for teardown.
    We need to ensure irq is disabled, followed by ensuring that don't schedule any
    more tasklets and then its safe to use tasklet_kill().

    Here in pch dma driver we need to use free_irq() before tasklet_kill(). So move
    up the free_irq() which will ensure that the irq is disabled and also wait till
    all scheduled interrupts are executed by invoking synchronize_irq().

    [1]: http://lwn.net/Articles/588457/

    Reported-by: Thomas Gleixner
    Signed-off-by: Vinod Koul

    Vinod Koul
     

02 Sep, 2013

1 commit


05 Aug, 2013

1 commit


22 Jul, 2013

1 commit


15 Apr, 2013

1 commit


27 Feb, 2013

1 commit

  • Pull slave-dmaengine updates from Vinod Koul:
    "This is fairly big pull by my standards as I had missed last merge
    window. So we have the support for device tree for slave-dmaengine,
    large updates to dw_dmac driver from Andy for reusing on different
    architectures. Along with this we have fixes on bunch of the drivers"

    Fix up trivial conflicts, usually due to #include line movement next to
    each other.

    * 'next' of git://git.infradead.org/users/vkoul/slave-dma: (111 commits)
    Revert "ARM: SPEAr13xx: Pass DW DMAC platform data from DT"
    ARM: dts: pl330: Add #dma-cells for generic dma binding support
    DMA: PL330: Register the DMA controller with the generic DMA helpers
    DMA: PL330: Add xlate function
    DMA: PL330: Add new pl330 filter for DT case.
    dma: tegra20-apb-dma: remove unnecessary assignment
    edma: do not waste memory for dma_mask
    dma: coh901318: set residue only if dma is in progress
    dma: coh901318: avoid unbalanced locking
    dmaengine.h: remove redundant else keyword
    dma: of-dma: protect list write operation by spin_lock
    dmaengine: ste_dma40: do not remove descriptors for cyclic transfers
    dma: of-dma.c: fix memory leakage
    dw_dmac: apply default dma_mask if needed
    dmaengine: ioat - fix spare sparse complain
    dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c
    ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDING
    dw_dmac: add support for Lynxpoint DMA controllers
    dw_dmac: return proper residue value
    dw_dmac: fill individual length of descriptor
    ...

    Linus Torvalds
     

07 Jan, 2013

1 commit


04 Jan, 2013

1 commit

  • CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
    markings need to be removed.

    This change removes the use of __devinit, __devexit_p, __devinitconst,
    and __devexit from these drivers.

    Based on patches originally written by Bill Pemberton, but redone by me
    in order to handle some of the coding style issues better, by hand.

    Cc: Bill Pemberton
    Cc: Viresh Kumar
    Cc: Dan Williams
    Cc: Vinod Koul
    Cc: Barry Song
    Cc: Jeff Kirsher
    Cc: Alexander Duyck
    Cc: Russell King
    Cc: Linus Walleij
    Cc: Jassi Brar
    Cc: Dave Jiang
    Cc: Bill Pemberton
    Cc: Guennadi Liakhovetski
    Signed-off-by: Greg Kroah-Hartman

    Greg Kroah-Hartman
     

29 Nov, 2012

2 commits


11 May, 2012

1 commit

  • dmaengine drivers should always use sg_dma_address instead of sg_phys to get the
    addresses for the transfer from a sg element.

    To quote Russel King:
    sg_phys(sg) of course has nothing to do with DMA addresses. It's the
    physical address _to the CPU_ of the memory associated with the scatterlist
    entry. That may, or may not have the same value for the DMA engine,
    particularly if IOMMUs are involved.

    And if these drivers are used on ARM, they must be fixed, sooner rather
    than later. There's patches in the works which will mean we will end up
    with IOMMU support in the DMA mapping later, which means everything I've
    said above will become reality.

    The patch has been generated using the following coccinelle patch:

    @@
    struct scatterlist *sg;
    @@
    -sg_phys(sg)
    +sg_dma_address(sg)

    Signed-off-by: Lars-Peter Clausen
    Acked-by: Linus Walleij
    Signed-off-by: Vinod Koul

    Lars-Peter Clausen
     

21 Mar, 2012

1 commit


13 Mar, 2012

5 commits

  • Provide a common function to initialize a channels cookie values.

    Signed-off-by: Russell King
    Tested-by: Linus Walleij
    Reviewed-by: Linus Walleij
    Acked-by: Jassi Brar
    [imx-sdma.c & mxs-dma.c]
    Tested-by: Shawn Guo
    Signed-off-by: Vinod Koul

    Russell King - ARM Linux
     
  • Now that we have the completed cookie in the dma_chan structure, we
    can consolidate the tx_status functions by providing a function to set
    the txstate structure and returning the DMA status. We also provide
    a separate helper to set the residue for cookies which are still in
    progress.

    Signed-off-by: Russell King
    Tested-by: Linus Walleij
    Reviewed-by: Linus Walleij
    Acked-by: Jassi Brar
    [imx-sdma.c & mxs-dma.c]
    Tested-by: Shawn Guo
    Signed-off-by: Vinod Koul

    Russell King - ARM Linux
     
  • Everyone deals with assigning DMA cookies in the same way (it's part of
    the API so they should be), so lets consolidate the common code into a
    helper function to avoid this duplication.

    Signed-off-by: Russell King
    Tested-by: Linus Walleij
    Reviewed-by: Linus Walleij
    Acked-by: Jassi Brar
    [imx-sdma.c & mxs-dma.c]
    Tested-by: Shawn Guo
    Signed-off-by: Vinod Koul

    Russell King - ARM Linux
     
  • Add a local private header file to contain definitions and declarations
    which should only be used by DMA engine drivers.

    We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
    multiple inclusion.

    Signed-off-by: Russell King
    Tested-by: Linus Walleij
    Reviewed-by: Linus Walleij
    Acked-by: Jassi Brar
    [imx-sdma.c & mxs-dma.c]
    Tested-by: Shawn Guo
    Signed-off-by: Vinod Koul

    Russell King - ARM Linux
     
  • Every DMA engine implementation declares a last completed dma cookie
    in their private dma channel structures. This is pointless, and
    forces driver specific code. Move this out into the common dma_chan
    structure.

    Signed-off-by: Russell King
    Tested-by: Linus Walleij
    Reviewed-by: Linus Walleij
    Acked-by: Jassi Brar
    [imx-sdma.c & mxs-dma.c]
    Tested-by: Shawn Guo
    Signed-off-by: Vinod Koul

    Russell King - ARM Linux
     

17 Nov, 2011

3 commits


27 Oct, 2011

1 commit

  • fixup usage of dma direction by introducing dma_transfer_direction,
    this patch moves dma/drivers/* to use new enum

    Cc: Jassi Brar
    Cc: Russell King
    Cc: Viresh Kumar
    Cc: Linus Walleij
    Cc: Nicolas Ferre
    Cc: Mika Westerberg
    Cc: H Hartley Sweeten
    Cc: Li Yang
    Cc: Zhang Wei
    Cc: Sascha Hauer
    Cc: Guennadi Liakhovetski
    Cc: Shawn Guo
    Cc: Yong Wang
    Cc: Tomoya MORINAGA
    Cc: Boojin Kim
    Cc: Barry Song
    Acked-by: Mika Westerberg
    Acked-by: Linus Walleij
    Acked-by: Viresh Kumar
    Acked-by: Nicolas Ferre
    Signed-off-by: Vinod Koul

    Vinod Koul
     

12 Oct, 2011

2 commits

  • nr_channels is defined in "struct pch_dma".
    and struct pch_dma_chan is defined in "struct pch_dma".
    So, "sizeof(struct pch_dma_chan) * nr_channels" is unnecessary.

    Signed-off-by: Tomoya MORINAGA
    Signed-off-by: Vinod Koul

    Tomoya MORINAGA
     
  • Currently, executing suspend/hibernation,
    memory access violation occurs.

    In pch_dma_save_regs() called by suspend(),
    you can see the following code.

    static void pch_dma_save_regs(struct pch_dma *pd)
    {
    snip...
    list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
    pd_chan = to_pd_chan(chan);

    pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
    pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
    pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
    pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);

    i++;
    }
    }

    Max loop count is 12 defined at pci_table.
    So, this caused memory access violation.

    This patch fixes the issue
    - Modify array size (MAX_CHAN_NR)

    Signed-off-by: Tomoya MORINAGA
    Signed-off-by: Vinod Koul

    Tomoya MORINAGA
     

20 Sep, 2011

1 commit


25 Jul, 2011

1 commit

  • Currently, Mode-Control register is accessed by read-modify-write.

    According to DMA hardware specifications datasheet, prohibits this method.
    Because this register resets to 0 by DMA HW after DMA transfer completes.
    Thus, current read-modify-write processing can cause unexpected behavior.

    The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
    e.g. Set DMA0=01b DMA11=10b
    CTL0=33333331h
    CTL2=00002333h

    NOTE:
    CTL0 includes DMA0~7 Mode-Control register.
    CTL2 includes DMA8~11 Mode-Control register.

    This patch modifies the issue.

    Signed-off-by: Tomoya MORINAGA
    Signed-off-by: Vinod Koul

    Tomoya MORINAGA
     

14 Jul, 2011

1 commit

  • Fix for the following INFO message

    =================================
    [ INFO: inconsistent lock state ]
    2.6.39+ #89
    ---------------------------------
    inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage.
    rs232/822 [HC1[1]:SC0[0]:HE0:SE1] takes:
    (&(&pd_chan->lock)->rlock){?.....}, at: [] pdc_desc_get+0x16/0xab
    {HARDIRQ-ON-W} state was registered at:
    [] mark_irqflags+0xbd/0x11a
    [] __lock_acquire+0x501/0x6bb
    [] lock_acquire+0x63/0x7b
    [] _raw_spin_lock_bh+0x43/0x51
    [] pd_alloc_chan_resources+0x92/0x11e
    [] dma_chan_get+0x9b/0x107
    [] __dma_request_channel+0x61/0xdc
    [] pch_request_dma+0x61/0x19e
    [] pch_uart_startup+0x16a/0x1a2
    [] uart_startup+0x87/0x147
    [] uart_open+0x117/0x13e
    [] tty_open+0x23c/0x34c
    [] chrdev_open+0x140/0x15f
    [] __dentry_open.clone.14+0x14a/0x22b
    [] nameidata_to_filp+0x36/0x40
    [] do_last+0x513/0x635
    [] path_openat+0x9c/0x2aa
    [] do_filp_open+0x27/0x69
    [] do_sys_open+0xfd/0x184
    [] sys_open+0x24/0x2a
    [] sysenter_do_call+0x12/0x32
    irq event stamp: 2522
    hardirqs last enabled at (2521): [] _raw_spin_unlock_irqrestore+0x36/0x52
    hardirqs last disabled at (2522): [] common_interrupt+0x27/0x34
    softirqs last enabled at (2354): [] __do_softirq+0x10a/0x11a
    softirqs last disabled at (2299): [] do_softirq+0x57/0xa4

    other info that might help us debug this:
    2 locks held by rs232/822:
    #0: (&tty->atomic_write_lock){+.+.+.}, at: [] tty_write_lock+0x14/0x3c
    #1: (&port_lock_key){-.....}, at: [] pch_uart_interrupt+0x17/0x1e9

    stack backtrace:
    Pid: 822, comm: rs232 Not tainted 2.6.39+ #89
    Call Trace:
    [] ? printk+0x19/0x1b
    [] print_usage_bug+0x184/0x18f
    [] ? print_irq_inversion_bug+0x10e/0x10e
    [] mark_lock_irq+0xa5/0x1f6
    [] mark_lock+0x208/0x2d7
    [] mark_irqflags+0x55/0x11a
    [] __lock_acquire+0x501/0x6bb
    [] ? dump_trace+0x92/0xb6
    [] lock_acquire+0x63/0x7b
    [] ? pdc_desc_get+0x16/0xab
    [] _raw_spin_lock+0x3e/0x4c
    [] ? pdc_desc_get+0x16/0xab
    [] pdc_desc_get+0x16/0xab
    [] ? __lock_acquire+0x653/0x6bb
    [] pd_prep_slave_sg+0x7c/0x1cb
    [] ? nommu_map_sg+0x6e/0x81
    [] dma_handle_tx+0x2cf/0x344
    [] ? pch_uart_interrupt+0x17/0x1e9
    [] pch_uart_interrupt+0x160/0x1e9
    [] handle_irq_event_percpu+0x25/0x127
    [] handle_irq_event+0x2c/0x43
    [] ? handle_fasteoi_irq+0x84/0x84
    [] handle_edge_irq+0xac/0xce
    [] ? do_IRQ+0x38/0x9d
    [] ? common_interrupt+0x2e/0x34
    [] ? __lock_acquire+0x1f6/0x6bb
    [] ? _raw_spin_unlock_irqrestore+0x38/0x52
    [] ? uart_start+0x2d/0x32
    [] ? uart_flush_chars+0x8/0xa
    [] ? n_tty_write+0x12c/0x1c6
    [] ? try_to_wake_up+0x251/0x251
    [] ? tty_write+0x169/0x1dc
    [] ? n_tty_ioctl+0xb7/0xb7
    [] ? vfs_write+0x91/0x10d
    [] ? tty_write_lock+0x3c/0x3c
    [] ? sys_write+0x3e/0x63
    [] ? sysenter_do_call+0x12/0x32

    Signed-off-by: Alexander Stein
    Tested-by: Tomoya MORINAGA
    Signed-off-by: Vinod Koul

    Alexander Stein
     

01 Jun, 2011

1 commit

  • ISSUE: In case PCH_DMA with I2S communications with ch8~ch11, sometimes I2S data
    is not send correctly.
    CAUSE: The following patch I submitted before was not enough modification for
    supporting DMA ch8~ch11. The modification for status register of ch8~11 was not
    enough.

    pch_dma: Support I2S for ML7213 IOH
    author Tomoya MORINAGA
    Mon, 9 May 2011 07:09:38 +0000 (16:09 +0900)
    committer Vinod Koul
    Mon, 9 May 2011 11:42:23 +0000 (16:42 +0530)
    commit 194f5f2706c7472f9c6bb2d17fa788993606581f
    tree c9d4903ea02b18939a4f390956a48be1a3734517
    parent 60092d0bde4c8741198da4a69b693d3709385bf1

    This patch fixes the issue.
    We can confirm PCH_DMA with I2S communications with ch8~ch11 works well.

    Signed-off-by: Tomoya MORINAGA
    Signed-off-by: Vinod Koul

    Tomoya MORINAGA
     

09 May, 2011

6 commits


06 Apr, 2011

1 commit