28 Jan, 2021
1 commit
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The ls-extirq driver doesn't implement the irq_set_wake()
callback, while being wake-up capable. This results in
ugly behaviours across suspend/resume cycles.Advertise this by adding IRQCHIP_SKIP_SET_WAKE to
the irqchip flagsSigned-off-by: Biwen Li
04 Jan, 2021
1 commit
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This is the 5.10.4 stable release
* tag 'v5.10.4': (717 commits)
Linux 5.10.4
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
drm/edid: fix objtool warning in drm_cvt_modes()
...Signed-off-by: Jason Liu
Conflicts:
drivers/gpu/drm/imx/dcss/dcss-plane.c
drivers/media/i2c/ov5640.c
30 Dec, 2020
4 commits
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[ Upstream commit 2f5fbc4305d07725bfebaedb09e57271315691ef ]
We have a problem if we use gpio-keys and configure wakeups such that
we only want one edge to wake us up. AKA:
wakeup-event-action = ;
wakeup-source;Specifically we end up with a phantom interrupt that blocks suspend if
the line was already high and we want wakeups on rising edges (AKA we
want the GPIO to go low and then high again before we wake up). The
opposite is also problematic.Specifically, here's what's happening today:
1. Normally, gpio-keys configures to look for both edges. Due to the
current workaround introduced in commit c3c0c2e18d94 ("pinctrl:
qcom: Handle broken/missing PDC dual edge IRQs on sc7180"), if the
line was high we'd configure for falling edges.
2. At suspend time, we change to look for rising edges.
3. After qcom_pdc_gic_set_type() runs, we get a phantom interrupt.We can solve this by just clearing the phantom interrupt.
NOTE: it is possible that this could cause problems for a client with
very specific needs, but there's not much we can do with this
hardware. As an example, let's say the interrupt signal is currently
high and the client is looking for falling edges. The client now
changes to look for rising edges. The client could possibly expect
that if the line has a short pulse low (and back high) that it would
always be detected. Specifically no matter when the pulse happened,
it should either have tripped the (old) falling edge trigger or the
(new) rising edge trigger. We will simply not trip it. We could
narrow down the race a bit by polling our parent before changing
types, but no matter what we do there will still be a period of time
where we can't tell the difference between a real transition (or more
than one transition) and the phantom.Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
Signed-off-by: Douglas Anderson
Signed-off-by: Marc Zyngier
Tested-by: Maulik Shah
Reviewed-by: Maulik Shah
Reviewed-by: Stephen Boyd
Link: https://lore.kernel.org/r/20201211141514.v4.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid
Signed-off-by: Sasha Levin -
[ Upstream commit fc6c7cd3878641fd43189f15697e7ad0871f5c1a ]
ti_sci_intr_irq_domain_free() assumes that out_irq of intr is stored in
data->chip_data and uses it for calling ti_sci irq_free() and then
mark the out_irq as available resource. But ti_sci_intr_irq_domain_alloc()
is storing p_hwirq(parent's hardware irq) which is translated from out_irq.
This is causing resource leakage and eventually out_irq resources might
be exhausted. Fix ti_sci_intr_irq_domain_alloc() by storing the out_irq
in data->chip_data.Fixes: a5b659bd4bc7 ("irqchip/ti-sci-intr: Add support for INTR being a parent to INTR")
Signed-off-by: Lokesh Vutla
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201102120631.11165-1-lokeshvutla@ti.com
Signed-off-by: Sasha Levin -
[ Upstream commit b10d5fd489b0c67f59cbdd28d95f4bd9f76a62f2 ]
On a successful probe, the driver tries to print a success message with
INTA device id. It uses pdev->id for printing the id but id is stored in
inta->ti_sci_id. Fix it by correcting the dev_info parameter.Fixes: 5c4b585d2910 ("irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC")
Signed-off-by: Lokesh Vutla
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201102120614.11109-1-lokeshvutla@ti.com
Signed-off-by: Sasha Levin -
[ Upstream commit 3841245e8498a789c65dedd7ffa8fb2fee2c0684 ]
The alpine-msi driver has an interesting allocation error handling,
where it frees the same interrupts repeatedly. Hilarity follows.This code is probably never executed, but let's fix it nonetheless.
Fixes: e6b78f2c3e14 ("irqchip: Add the Alpine MSIX interrupt controller")
Signed-off-by: Marc Zyngier
Reviewed-by: Antoine Tenart
Cc: Tsahee Zidenberg
Cc: Antoine Tenart
Link: https://lore.kernel.org/r/20201129135525.396671-1-maz@kernel.org
Signed-off-by: Sasha Levin
14 Dec, 2020
19 commits
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Allows imx irqsteer driver to be loaded as module.
Signed-off-by: Jindong
Reviewed-by: Fugang Duan -
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xASigned-off-by: Hou Zhiqiang
Signed-off-by: Biwen Li -
This reverts commit 3d65a3518149d33e289b5417d7a4a175b4ef0737.
The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.Signed-off-by: Jacky Bai
Tested-by: Jian Li -
…rq numbers for imx8mp"
This reverts commit 2d0e3291c68c3229a7e4d45dede51ebcbac7dea2.
The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Jian Li <jian.li@nxp.com> -
Since commit 5cebfd2d47c214 "arm64: Kill __smp_cross_call and co",
the workaround for ERR11171 for i.MX8MQ needs a different approach.
Remove all the smp_cross_call references and make sure the workaround
is happening only on 8MQ and if the TF-A supports it.Signed-off-by: Abel Vesa
-
Add runtime pm to manage irqsteer clock and its power domain in system
idle and suspend status to save power.Signed-off-by: Fugang Duan
Signed-off-by: Frank Li
Tested-by: Guoniu.Zhou
Reviewed-by: Frank Li
Signed-off-by: Arulpandiyan Vadivel
(cherry picked and merged from commit 6c861656225d3b2407b5e7630106a7fd7fab119d) -
For multi power domain, if DL_FLAG_RPM_ACTIVE flag is set when device link
binding, power domain will keep active after probe, but driver need to let
device into lp status when there is no camera streaming. So remove the flag
in driver.Signed-off-by: Andy Duan
Signed-off-by: Guoniu.zhou -
Fix issue reported by coverity, CID is 5575278
Signed-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
For i.MX8MP, the max irq numbers is 160, so correct the max irq number
in GPCv2 driver to Fix the IRQ number get failure issue if requested
irq number > 128.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 2d0e3291c68c3229a7e4d45dede51ebcbac7dea2) -
Add the wait mode workaround on i.MX8MP. it is just
a provisional patch for Alpha release. it will be
dropped in the future. As all the changes in this
patch need to be revered for that time, just including
all the changes of dts & driver in one patch to make
it more easier to track all the changes.Coresight probe has some conlict with the IPI workaround.
it is meaningless to put effort on resolve such conflict,
and Coresight is not an must feature for Alpha release,
disable the Coresight support directly.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 3d65a3518149d33e289b5417d7a4a175b4ef0737) -
Add reset function for imx-irqsteer.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai -
Fix below build error when CONFIG_SMP is NOT selected:
drivers/irqchip/irq-imx-gpcv2.c: In function "imx_gpcv2_wake_request_fixup":
drivers/irqchip/irq-imx-gpcv2.c:123:2: error: implicit declaration of function
"set_smp_cross_call" [-Werror=implicit-function-declaration]
123 | set_smp_cross_call(imx_gpcv2_raise_softirq);
| ^~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[3]: *** [drivers/irqchip/irq-imx-gpcv2.o] Error 1Signed-off-by: Anson Huang
Reviewed-by: Robin Gong -
As of now, if somebody masks/unmasks any irq while the set_wake goes
to TF-A, the masking/unmasking might be overwritten. So add new irq_chip ops
that implement the masking, unmasking, set_wake and set_affinity and each
calls into TF-A internally. Also add the ERR11171 knob that allows
initializing the core wake-up workaround by registering our own
smp_cross_call funtion and call the old one from within. The ERR11171 knob
gets enabled by default if the machine is i.MX8MQ.Signed-off-by: Abel Vesa
Reviewed-by: Jacky Bai -
Fix below build warning when built with imx_v6_v7_defconfig:
drivers/irqchip/irq-imx-gpcv2.c: In function 'imx_gpcv2_irq_set_wake':
drivers/irqchip/irq-imx-gpcv2.c:129:23: warning: unused variable 'res' [-Wunused-variable]
struct arm_smccc_res res;
^Signed-off-by: Anson Huang
-
The wakeup irq info need to be provided to ATF side, then
ATF side can config the correct wakeup IRQ when entering
suspend.Signed-off-by: Jacky Bai
-
Fix below build error when built with imx_v6_v7_defconfig:
drivers/irqchip/irq-imx-gpcv2.c: In function 'imx_gpcv2_wake_request_fixup':
drivers/irqchip/irq-imx-gpcv2.c:112:28: error: '__smp_cross_call' undeclared (first use in this function); did you mean 'set_smp_cross_call'?
__gic_v3_smp_cross_call = __smp_cross_call;
^~~~~~~~~~~~~~~~
set_smp_cross_call
drivers/irqchip/irq-imx-gpcv2.c:112:28: note: each undeclared identifier is reported only once for each function it appears inSigned-off-by: Anson Huang
-
Not all EL3 have the FSL_SIP_CONFIG_GPC_CORE_WAKE, therefore disable
the cpuidle to avoid all the cores going to sleep ending up with a
hang. This allows all the EL3 implementations to work with i.MX8MQ
even if they do not support core wake-up through GPC as a workaround.Signed-off-by: Abel Vesa
-
i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
breaks cpuidle support due to inability to wake target cores on IPIs.Here is the link to the errata (see e11171):
https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0N14W.pdf
Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
setting 12th bit in IOMUX_GPR1 register. In order to control the target cores
only, that is, not waking up all the cores every time, we can unmask/mask the
IRQ 32 in the first GPC IMR register. So basically we can leave the IOMUX_GPR1
12th bit always set and just play with the masking and unmasking the IRO 32 for
each independent core.Since EL3 is the one that deals with powering down/up the cores, and since the
cores wake up in EL3, EL3 should be the one to control the IMRs in this case.
This implies we need to get into EL3 on every IPI to do the unmasking, leaving
the masking to be done on the power-up sequence by the core itself.In order to be able to get into EL3 on each IPI, we 'hijack' the registered smp
cross call handler, in this case the gic_raise_softirq which is registered by
the irq-gic-v3 driver and register our own handler instead. This new handler is
basically a wrapper over the hijacked handler plus the call into EL3.To get into EL3, we use a custom vendor SIP id added just for this purpose.
All of this is conditional for i.MX8MQ only.
Signed-off-by: Abel Vesa
-
In some subsystem of IMX8, irqsteer is under multi power domains
and they need to be actived when irqsteer work.irqsteer of imx8qxp image subsystem need CSI and ISI power domains
to be actived, so add multi-pd support as an optional feature for
irqsteer driverThe power-domains on imx8qxp are meant to look like this:
power-domains = , ;
power-domain-names = "pd_csi", "pd_isi_ch0";Signed-off-by: Guoniu.zhou
25 Nov, 2020
1 commit
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…t/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
- Fix Exiu driver trigger type when using ACPI
- Fix GICv3 ITS suspend/resume to use the in-kernel path
at all times, sidestepping braindead firmware supportLink: https://lore.kernel.org/r/20201122184752.553990-1-maz@kernel.org
22 Nov, 2020
2 commits
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On systems without HW-based collections (i.e. anything except GIC-500),
we rely on firmware to perform the ITS save/restore. This doesn't
really work, as although FW can properly save everything, it cannot
fully restore the state of the command queue (the read-side is reset
to the head of the queue). This results in the ITS consuming previously
processed commands, potentially corrupting the state.Instead, let's always save the ITS state on suspend, disabling it in the
process, and restore the full state on resume. This saves us from broken
FW as long as it doesn't enable the ITS by itself (for which we can't do
anything).This amounts to simply dropping the ITS_FLAGS_SAVE_SUSPEND_STATE.
Signed-off-by: Xu Qiang
[maz: added warning on resume, rewrote commit message]
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201107104226.14282-1-xuqiang36@huawei.com -
Since fwspec->param_count of ACPI node is two, the index of IRQ type
in fwspec->param[] should be 1 rather than 2.Fixes: 3d090a36c8c8 ("irqchip/exiu: Implement ACPI support")
Signed-off-by: Chen Baozi
Signed-off-by: Marc Zyngier
Acked-by: Ard Biesheuvel
Link: https://lore.kernel.org/r/20201117032015.11805-1-cbz@baozis.org
Cc: stable@vger.kernel.org
09 Nov, 2020
1 commit
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Pull irq fixes from Thomas Gleixner:
"A set of fixes for interrupt chip drivers:- Fix the fallout of the IPI as interrupt conversion in Kconfig and
the BCM2836 interrupt chip driver- Fixes for interrupt affinity setting and the handling of
hierarchical irq domains in the SiFive PLIC driver- Make the unmapped event handling in the TI SCI driver work
correctly- A few minor fixes and cleanups in various chip drivers and Kconfig"
* tag 'irq-urgent-2020-11-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
dt-bindings: irqchip: ti, sci-inta: Fix diagram indentation for unmapped events
irqchip/ti-sci-inta: Add support for unmapped event handling
dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling
irqchip/renesas-intc-irqpin: Merge irlm_bit and needs_irlm
irqchip/sifive-plic: Fix chip_data access within a hierarchy
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
irqchip/stm32-exti: Add all LP timer exti direct events support
irqchip/bcm2836: Fix missing __init annotation
irqchip/mips: Drop selection of IRQ_DOMAIN_HIERARCHY
irqchip/mst: Make mst_intc_of_init static
irqchip/mst: MST_IRQ should depend on ARCH_MEDIATEK or ARCH_MSTARV7
genirq: Let GENERIC_IRQ_IPI select IRQ_DOMAIN_HIERARCHY
01 Nov, 2020
3 commits
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The DMA (BCDMA/PKTDMA and their rings/flows) events are under the INTA's
supervision as unmapped events in AM64.In order to keep the current SW stack working, the INTA driver must replace
the dev_id with it's own when a request comes for BCDMA or PKTDMA
resources.Implement parsing of the optional "ti,unmapped-event-sources" phandle array
to get the sci-dev-ids of the devices where the unmapped events originate.Signed-off-by: Peter Ujfalusi
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201020073243.19255-3-peter.ujfalusi@ti.com -
Get rid of the separate flag to indicate if the IRLM bit is present in
the INTC/Interrupt Control Register 0, by considering -1 an invalid
irlm_bit value.Signed-off-by: Geert Uytterhoeven
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201028153955.1736767-1-geert+renesas@glider.be -
The plic driver crashes in plic_irq_unmask() when the interrupt is within a
hierarchy, as it picks the top-level chip_data instead of its local one.Using irq_data_get_irq_chip_data() instead of irq_get_chip_data() solves
the issue for good.Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
Signed-off-by: Greentime Hu
[maz: rewrote commit message]
Signed-off-by: Marc Zyngier
Reviewed-by: Anup Patel
Reviewed-by: Atish Patra
Link: https://lore.kernel.org/r/20201029023738.127472-1-greentime.hu@sifive.com
26 Oct, 2020
1 commit
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Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.Conversion done using the script at:
https://lore.kernel.org/lkml/75393e5ddc272dc7403de74d645e6c6e0f4e70eb.camel@perches.com/2-convert_section.pl
Signed-off-by: Joe Perches
Reviewed-by: Nick Desaulniers
Reviewed-by: Miguel Ojeda
Signed-off-by: Linus Torvalds
25 Oct, 2020
4 commits
-
An interrupt submitted to an affinity change will always be left enabled
after plic_set_affinity() has been called, while the expectation is that
it should stay in whatever state it was before the call.Preserving the configuration fixes a PWM hang issue on the Unleashed
board.[ 919.015783] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 919.020922] rcu: 0-...0: (0 ticks this GP)
idle=7d2/1/0x4000000000000002 softirq=1424/1424 fqs=105807
[ 919.030295] (detected by 1, t=225825 jiffies, g=1561, q=3496)
[ 919.036109] Task dump for CPU 0:
[ 919.039321] kworker/0:1 R running task 0 30 2 0x00000008
[ 919.046359] Workqueue: events set_brightness_delayed
[ 919.051302] Call Trace:
[ 919.053738] [] __schedule+0x194/0x4de
[ 982.035783] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 982.040923] rcu: 0-...0: (0 ticks this GP)
idle=7d2/1/0x4000000000000002 softirq=1424/1424 fqs=113325
[ 982.050294] (detected by 1, t=241580 jiffies, g=1561, q=3509)
[ 982.056108] Task dump for CPU 0:
[ 982.059321] kworker/0:1 R running task 0 30 2 0x00000008
[ 982.066359] Workqueue: events set_brightness_delayed
[ 982.071302] Call Trace:
[ 982.073739] [] __schedule+0x194/0x4de
[..]Fixes: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow")
Signed-off-by: Greentime Hu
[maz: tidy-up commit message]
Signed-off-by: Marc Zyngier
Reviewed-by: Anup Patel
Link: https://lore.kernel.org/r/20201020081532.2377-1-greentime.hu@sifive.com -
Add all remaining LP timer exti direct events, e.g. for LP Timer 2 to 5.
LP timer 1 is already listed (e.g. exti 47).Signed-off-by: Fabrice Gasnier
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/1602859219-15684-2-git-send-email-fabrice.gasnier@st.com -
bcm2836_arm_irqchip_smp_init() calls set_smp_ipi_range(), which has
an __init annotation. Make sure the caller has the same annotation.Reported-by: kernel test robot
Signed-off-by: Marc Zyngier -
Pull ARM SoC platform updates from Olof Johansson:
"SoC changes, a substantial part of this is cleanup of some of the
older platforms that used to have a bunch of board files.In particular:
- Remove non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.- A bunch of cleanup and removal of platform data for TI/OMAP
platforms, moving over to genpd for power/reset control (yay!)- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).There are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones are:- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
ARM: mstar: Select MStar intc
ARM: stm32: Replace HTTP links with HTTPS ones
ARM: debug: add UART early console support for SD5203
ARM: hisi: add support for SD5203 SoC
ARM: omap3: enable off mode automatically
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx27: Remove mx27_clocks_init()
ARM: imx: Remove unused definitions
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: s3c64xx: bring back notes from removed debug-macro.S
ARM: s3c24xx: fix Wunused-variable warning on !MMU
ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
MAINTAINERS: mark linux-samsung-soc list non-moderated
ARM: imx: Remove remnant board file support pieces
...
16 Oct, 2020
3 commits
-
Now that GENERIC_IRQ_IPI selects IRQ_DOMAIN_HIERARCHY, there is no
need to have this conditional select for IRQ_MIPS_CPU. Similarily,
MIPS_GIC only needs selecting GENERIC_IRQ_IPI.Suggested-by: Thomas Gleixner
Signed-off-by: Marc Zyngier -
mst_intc_of_init has no external caller, so let's make it static.
Reported-by: kernel test robot
Signed-off-by: Marc Zyngier -
The MStar interrupt controller is only found on MStar, SigmaStar, and
Mediatek SoCs. Hence add dependencies on ARCH_MEDIATEK and
ARCH_MSTARV7, to prevent asking the user about the MStar interrupt
controller driver when configuring a kernel without support for MStar,
SigmaStar, and Mediatek SoCs.Fixes: ad4c938c92af9130 ("irqchip/irq-mst: Add MStar interrupt controller support")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Marc Zyngier
Acked-by: Daniel Palmer
Link: https://lore.kernel.org/r/20201014131703.18021-1-geert+renesas@glider.be