12 Jan, 2021
1 commit
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Refer to commit 075af61c19cd ("PCI: imx6: Limit DBI register length"),
i.MX6QP PCIe has the similar issue.
Define the length of the DBI registers and limit config space to its
length for i.MX6QP PCIe too.Signed-off-by: Richard Zhu
Reviewed-by: Peter Chen
04 Jan, 2021
1 commit
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This is the 5.10.4 stable release
* tag 'v5.10.4': (717 commits)
Linux 5.10.4
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
drm/edid: fix objtool warning in drm_cvt_modes()
...Signed-off-by: Jason Liu
Conflicts:
drivers/gpu/drm/imx/dcss/dcss-plane.c
drivers/media/i2c/ov5640.c
30 Dec, 2020
8 commits
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commit 4684709bf81a2d98152ed6b610e3d5c403f9bced upstream.
If kobject_init_and_add() fails, pci_slot_release() is called to delete
slot->list from parent->slots. But slot->list hasn't been initialized
yet, so we dereference a NULL pointer:Unable to handle kernel NULL pointer dereference at virtual address
00000000
...
CPU: 10 PID: 1 Comm: swapper/0 Not tainted 4.4.240 #197
task: ffffeb398a45ef10 task.stack: ffffeb398a470000
PC is at __list_del_entry_valid+0x5c/0xb0
LR is at pci_slot_release+0x84/0xe4
...
__list_del_entry_valid+0x5c/0xb0
pci_slot_release+0x84/0xe4
kobject_put+0x184/0x1c4
pci_create_slot+0x17c/0x1b4
__pci_hp_initialize+0x68/0xa4
pciehp_probe+0x1a4/0x2fc
pcie_port_probe_service+0x58/0x84
driver_probe_device+0x320/0x470Initialize slot->list before calling kobject_init_and_add() to avoid this.
Fixes: 8a94644b440e ("PCI: Fix pci_create_slot() reference count leak")
Link: https://lore.kernel.org/r/1606876422-117457-1-git-send-email-zhongjubin@huawei.com
Signed-off-by: Jubin Zhong
Signed-off-by: Bjorn Helgaas
Cc: stable@vger.kernel.org # v5.9+
Signed-off-by: Greg Kroah-Hartman -
commit 7482c5cb90e5a7f9e9e12dd154d405e0219656e3 upstream.
The idea behind acpi_pm_set_bridge_wakeup() was to allow bridges to
be reference counted for wakeup enabling, because they may be enabled
to signal wakeup on behalf of their subordinate devices and that
may happen for multiple times in a row, whereas for the other devices
it only makes sense to enable wakeup signaling once.However, this becomes problematic if the bridge itself is suspended,
because it is treated as a "regular" device in that case and the
reference counting doesn't work.For instance, suppose that there are two devices below a bridge and
they both can signal wakeup. Every time one of them is suspended,
wakeup signaling is enabled for the bridge, so when they both have
been suspended, the bridge's wakeup reference counter value is 2.Say that the bridge is suspended subsequently and acpi_pci_wakeup()
is called for it. Because the bridge can signal wakeup, that
function will invoke acpi_pm_set_device_wakeup() to configure it
and __acpi_pm_set_device_wakeup() will be called with the last
argument equal to 1. This causes __acpi_device_wakeup_enable()
invoked by it to omit the reference counting, because the reference
counter of the target device (the bridge) is 2 at that time.Now say that the bridge resumes and one of the device below it
resumes too, so the bridge's reference counter becomes 0 and
wakeup signaling is disabled for it, but there is still the other
suspended device which may need the bridge to signal wakeup on its
behalf and that is not going to work.To address this scenario, use wakeup enable reference counting for
all devices, not just for bridges, so drop the last argument from
__acpi_device_wakeup_enable() and __acpi_pm_set_device_wakeup(),
which causes acpi_pm_set_device_wakeup() and
acpi_pm_set_bridge_wakeup() to become identical, so drop the latter
and use the former instead of it everywhere.Fixes: 1ba51a7c1496 ("ACPI / PCI / PM: Rework acpi_pci_propagate_wakeup()")
Signed-off-by: Rafael J. Wysocki
Reviewed-by: Mika Westerberg
Acked-by: Bjorn Helgaas
Cc: 4.14+ # 4.14+
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 89bbcaac3dff21f3567956b3416f5ec8b45f5555 ]
Second stage bootloaders prior to Linux boot may use all inbound windows
including IARR1/IMAP1. We need to ensure that all previous configuration
of inbound windows are invalidated during the initialization stage of
the Linux iProc PCIe driver so let's add a fix to define and invalidate
IARR1/IMAP1 because it is currently missing, fixing the issue.Link: https://lore.kernel.org/r/20201001060054.6616-3-srinath.mannam@broadcom.com
Fixes: 9415743e4c8a ("PCI: iproc: Invalidate PAXB address mapping")
Signed-off-by: Roman Bacik
Signed-off-by: Srinath Mannam
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi
Signed-off-by: Sasha Levin -
[ Upstream commit a3ff529f5d368a17ff35ada8009e101162ebeaf9 ]
Declare the full size array for all revisions of PAX register sets
to avoid potentially out of bound access of the register array
when they are being initialized in iproc_pcie_rev_init().Link: https://lore.kernel.org/r/20201001060054.6616-2-srinath.mannam@broadcom.com
Fixes: 06324ede76cdf ("PCI: iproc: Improve core register population")
Signed-off-by: Bharat Gooty
Signed-off-by: Lorenzo Pieralisi
Signed-off-by: Sasha Levin -
[ Upstream commit cc73eb321d246776e5a9f7723d15708809aa3699 ]
The shift of 1 by align_order is evaluated using 32 bit arithmetic and the
result is assigned to a resource_size_t type variable that is a 64 bit
unsigned integer on 64 bit platforms. Fix an overflow before widening issue
by making the 1 a ULL.Addresses-Coverity: ("Unintentional integer overflow")
Fixes: 32a9a682bef2 ("PCI: allow assignment of memory resources with a specified alignment")
Signed-off-by: Colin Ian King
Signed-off-by: Bjorn Helgaas
Reviewed-by: Logan Gunthorpe
Signed-off-by: Sasha Levin -
[ Upstream commit 6534aac198b58309ff2337981d3f893e0be1d19d ]
32-bit BARs are limited to 2GB size (2^31). By extension, I assume 64-bit
BARs are limited to 2^63 bytes. Limit the alignment requested by the
"pci=resource_alignment=" command-line parameter to 2^63.Link: https://lore.kernel.org/r/20201007123045.GS4282@kadam
Reported-by: Dan Carpenter
Signed-off-by: Bjorn Helgaas
Signed-off-by: Sasha Levin -
[ Upstream commit ddaff0af653136ee1e0b49116ecf2988c2fc64ca ]
The variable 'tmp' is used multiple times in the brcm_pcie_setup()
function. One such usage did not initialize 'tmp' to the current value
of the target register. By luck the mistake does not currently affect
behavior; regardless 'tmp' is now initialized properly.Suggested-by: Rafał Miłecki
Link: https://lore.kernel.org/r/20201102205712.23332-1-james.quinlan@broadcom.com
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
Signed-off-by: Jim Quinlan
Signed-off-by: Lorenzo Pieralisi
Acked-by: Nicolas Saenz Julienne
Acked-by: Florian Fainelli
Signed-off-by: Sasha Levin -
[ Upstream commit f83c37941e881224885f2e694e0626bea358e96b ]
Pericom PCIe-USB adapter advertises MSI, but documentation says "The MSI
Function is not implemented on this device" in chapters 7.3.27,
7.3.29-7.3.31, and Alberto found that MSI in fact does not work.Disable MSI for these devices.
Datasheet: https://www.diodes.com/assets/Datasheets/PI7C9X440SL.pdf
Fixes: 306c54d0edb6 ("usb: hcd: Try MSI interrupts on PCI devices")
Link: https://lore.kernel.org/linux-usb/20201030134826.GP4077@smile.fi.intel.com/
Link: https://lore.kernel.org/r/20201106100526.17726-1-andriy.shevchenko@linux.intel.com
Reported-by: alberto.vignani@fastwebnet.it
Signed-off-by: Andy Shevchenko
Signed-off-by: Bjorn Helgaas
Signed-off-by: Sasha Levin
18 Dec, 2020
2 commits
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* origin/pcie/mobiveil: (10 commits)
PCI: mobiveil: Complete initialization of host even if no PCIe link
PCI: mobiveil: Add link up condition check
PCI: mobiveil: Add workaround for unsupported request error
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
... -
* origin/pcie/dwc: (64 commits)
LF-2681-1 PCI: imx: fix ep dump in ep rc system
LF-2680-2 PCI: imx: msi addr should be re-init in resume
LF-2680-1 PCI: dwc: Revert "PCI: dwc: Use interrupt disabling instead of masking"
MA-17597-5 pci: controller: dwc: support module build
PCI: layerscape: Add EP mode support for LX2160A rev2
...
14 Dec, 2020
28 commits
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Sometimes there is not a PCIe Endpoint stalled in the slot,
do not exit when the PCIe link is not up, such that the root
port can be registered.
And degrade the print level of no link info.Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa -
Avoid to issue CFG transactions to link partner when the PCIe
link is not up.Signed-off-by: Hou Zhiqiang
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Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang -
This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
mode if select this config opteration.Signed-off-by: Xiaowei Bao
[Zhiqiang: Correct the Copyright]
Signed-off-by: Hou Zhiqiang -
Add the EP driver support for Mobiveil base on endpoint framework.
Signed-off-by: Xiaowei Bao
[Zhiqiang: Correct the Copyright]
Signed-off-by: Hou Zhiqiang -
Clearing the Bus Master Enable bit in Command register blocks all
outbound transactions to be sent out in RC modeDescription:
According to PCI Express base specification, the Command register’s
Bus Master Enable bit of a PCI Express RC controller can only
control the forwarding of memory requests received at its root port
in the upstream direction. In other words, clearing the Bus Master
Enable bit must not block all outbound transactions to be sent out
toward RC’s downstream devices. Due to this erratum, when the
Command register’s Bus Master Enable bit is cleared, all the outbound
transactions from the device’s internal bus masters, including but
not limited to configuration read and write transactions, are
terminated with the slave error (SLVERR) response status on the PCI
Express RC controller’s internal AXI bus interface.Workaround:
Software must program the PCI Express RC controller's Command
register [Bus Master Enable] bit to 1b before issuing any
outbound transaction, including but not limited to configuration
read and write transactions.Signed-off-by: Hou Zhiqiang
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When LX2 PCIe controller is sending multiple split completions and
ACK latency expires indicating that ACK should be send at priority.
But because of large number of split completions and FC update DLLP,
the controller does not give priority to ACK transmission. This
results into ACK latency timer timeout error at the link partner and
the pending TLPs are replayed by the link partner again.Workaround:
1. Reduce the ACK latency timeout value to a very small value.
2. Restrict the number of completions from the LX2 PCIe controller
to 1, by changing the Max Read Request Size (MRRS) of link partner
to the same value as Max Packet size (MPS).This patch implemented part 1, the part 2 can be set by kernel parameter
'pci=pcie_bus_perf'This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.Signed-off-by: Hou Zhiqiang
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PCIe configuration access to non-existent function triggered
SERROR interrupt exception.Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.Signed-off-by: Hou Zhiqiang
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On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.Signed-off-by: Po Liu
Signed-off-by: Hou Zhiqiang -
Refine the codes, and only get the source entry when RC mode is enabled.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
The MSI ADDR should be re-initialized in the resume, otherwise MSI
might be broken after suspend/resume on 5.10 kernel.Signed-off-by: Richard Zhu
Reviewed-by: Peter Chen -
This reverts commit b45cf0dd49e75e324276bf99ca1e62e65f76d9ee.
The commit "b45cf0dd49e75e324276bf99ca1e62e65f76d9ee" breaks PCIe MSI
functions, and is not required anymore on 5.10 kernel.Signed-off-by: Richard Zhu
Reviewed-by: Andy Duan -
Support build PCI_IMX6 as module.
Also export the dw_pcie_link_up() function to be used
by other module.Signed-off-by: Jindong Yue
Reviewed-by: Richard Zhu -
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2
PCIe controller is integrated with different stride between PFs'
register address.Signed-off-by: Hou Zhiqiang
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pci imx set the dbi_wr_en when re-configure the link gen
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
EP has it's own memory window alignment, use it to refine
the EP/RC validation codes.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
These codes had been moved to probe func. Remove the
duplicated ones.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
To support the bus freq power saving mode, add the sysfile interface.
Request bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freq
Release bus high: echo 0 > /sys/devices/platform/xxxxxxxx.pcie/bus_freqSigned-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
- Verify the both internal PLL_SYS and external OSC reference clock
modes on iMX8MP EVK board, and pass the PCIe compliance tests.
- Remove the no-needed bypass setting.
- PHY configuration should be completed before CMN_RSTN is set to 1b1
- To manually initiate the speed change to make sure GEN2 is linked up:
- Write to LINK_CONTROL2_LINK_STATUS2_REG.PCIE_CAP_TARGET_LINK_SPEED
in the local device
- De-assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device
- Assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local deviceSigned-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Remove one dev_info message
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Configure the L1 latency of iMX8M's RC to less than 64us, otherwise,
the L1/L1SS wouldn't be enabled by ASPM.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX6Q/DL/QP PCIe EP supports, and verify on sabresd board.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX7D PCIe EP mode support and verify on SDB board.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX6SX PCIe EP support and verify on SDB board.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX8MQ/MM/MP PCIe EP support
Set the align to 64K since it is required by iMX8M PCIe inbound/outbound
Remove the redundant codes of the CLKREQ_OVERRIDE setting, since these
codes are duplicated.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX8QM PCIe EP mode support, and verify on iMX8QM MEK board.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the PCIe EP mode on iMX8QXP, and verify EP mode on iMX8QXP MEK board
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add the iMX8MP PCIe support.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
