29 Nov, 2011
1 commit
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Support for specific hardware belongs under drivers/net/ not net/.
Signed-off-by: Ben Hutchings
Acked-by: Lennert Buytenhek
Signed-off-by: David S. Miller
27 Nov, 2011
3 commits
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Change the kconfig types to tristate and adjust the condition for
declaring net_device::dsa_ptr to allow for this.Adjust the makefile so that if NET_DSA_MV88E6123_61_65=y and
NET_DSA_MV88E6131=m or vice versa then both drivers are built-in. We
could leave these options as bool and make NET_DSA_MV88E6XXX a
user-selected option, but that would break existing configurations.Signed-off-by: Ben Hutchings
Signed-off-by: David S. Miller -
These drivers share a lot of code, so if we make them modular they
should be built into the same module. Therefore, link them together
and merge their respective module init and exit functions.Signed-off-by: Ben Hutchings
Signed-off-by: David S. Miller -
These files have circular dependencies, so if we make DSA modular then
they must be built into the same module. Therefore, link them
together and merge their respective module init and exit functions.Signed-off-by: Ben Hutchings
Signed-off-by: David S. Miller
09 Oct, 2008
5 commits
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Add support for the Marvell 88E6060 switch chip. This chip only
supports the Header and Trailer tagging formats, and we use it in
Trailer mode since that mode is slightly easier to handle than
Header mode.Signed-off-by: Lennert Buytenhek
Tested-by: Byron Bradley
Tested-by: Tim Ellis
Signed-off-by: David S. Miller -
This adds support for the Trailer switch tagging format. This is
another tagging that doesn't explicitly mark tagged packets with a
distinct ethertype, so that we need to add a similar hack in the
receive path as for the Original DSA tagging format.Signed-off-by: Lennert Buytenhek
Tested-by: Byron Bradley
Tested-by: Tim Ellis
Signed-off-by: David S. Miller -
Add support for the Marvell 88E6131 switch chip. This chip only
supports the original (ethertype-less) DSA tagging format.On the 88E6131, there is a PHY Polling Unit (PPU) which has exclusive
access to each of the PHYs's MII management registers. If we want to
talk to the PHYs from software, we have to disable the PPU and wait
for it to complete its current transaction before we can do so, and we
need to re-enable the PPU afterwards to make sure that the switch will
notice changes in link state and speed on the individual ports as they
occur.Since disabling the PPU is rather slow, and since MII management
accesses are typically done in bursts, this patch keeps the PPU disabled
for 10ms after a software access completes. This makes handling the
PPU slightly more complex, but speeds up something like running ethtool
on one of the switch slave interfaces from ~300ms to ~30ms on typical
hardware.Signed-off-by: Lennert Buytenhek
Tested-by: Nicolas Pitre
Tested-by: Peter van Valderen
Tested-by: Dirk Teurlings
Signed-off-by: David S. Miller -
Most of the DSA switches currently in the field do not support the
Ethertype DSA tagging format that one of the previous patches added
support for, but only the original DSA tagging format.The original DSA tagging format carries the same information as the
Ethertype DSA tagging format, but with the difference that it does not
have an ethertype field. In other words, when receiving a packet that
is tagged with an original DSA tag, there is no way of telling in
eth_type_trans() that this packet is in fact a DSA-tagged packet.This patch adds a hook into eth_type_trans() which is only compiled in
if support for a switch chip that doesn't support Ethertype DSA is
selected, and which checks whether there is a DSA switch driver
instance attached to this network device which uses the old tag format.
If so, it sets the protocol field to ETH_P_DSA without looking at the
packet, so that the packet ends up in the right place.Signed-off-by: Lennert Buytenhek
Tested-by: Nicolas Pitre
Tested-by: Peter van Valderen
Tested-by: Dirk Teurlings
Signed-off-by: David S. Miller -
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)Signed-off-by: Lennert Buytenhek
Tested-by: Nicolas Pitre
Tested-by: Byron Bradley
Tested-by: Tim Ellis
Tested-by: Peter van Valderen
Tested-by: Dirk Teurlings
Signed-off-by: David S. Miller
