Eric Lee / smarc-fsl-linux-kernel

12 Mar, 2020

3 commits

  • c9e28c25a   clk: tegra: Remove CLK_M_DIV fixed clocks ... Browse Code »

    Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has
    OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible
    parents of PMC clocks for Tegra30 through Tegra210.

    Tegra PMC clock parents are changed to use OSC_DIV clocks.

    So, this patch removes CLK_M_DIV fixed clocks

    Tested-by: Dmitry Osipenko
    Reviewed-by: Dmitry Osipenko
    Signed-off-by: Sowjanya Komatineni
    Signed-off-by: Thierry Reding

    Sowjanya Komatineni
     
  • 2b50e49b0   clk: tegra: Add Tegra OSC to clock lookup ... Browse Code »

    OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2,
    and clk_out_3.

    This patch adds Tegra OSC to clock lookup.

    Tested-by: Dmitry Osipenko
    Reviewed-by: Dmitry Osipenko
    Signed-off-by: Sowjanya Komatineni
    Signed-off-by: Thierry Reding

    Sowjanya Komatineni
     
  • 9a85eb4d6   clk: tegra: Add support for OSC_DIV fixed clocks ... Browse Code »

    Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
    from the OSC pads.

    This patch adds support for these clocks.

    Tested-by: Dmitry Osipenko
    Reviewed-by: Dmitry Osipenko
    Signed-off-by: Sowjanya Komatineni
    Signed-off-by: Thierry Reding

    Sowjanya Komatineni
     

11 Nov, 2019

1 commit

  • 50d4da9b1   clk: tegra: Support for OSC context save and restore ... Browse Code »

    This patch adds support for saving OSC clock frequency and the
    drive-strength during OSC clock init and creates an API to restore
    OSC control register value from the saved context.

    This API is invoked by Tegra210 clock driver during system resume
    to restore the OSC clock settings.

    Acked-by: Thierry Reding
    Signed-off-by: Sowjanya Komatineni
    Signed-off-by: Thierry Reding

    Sowjanya Komatineni
     

31 May, 2019

1 commit

  • 9952f6918   treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 ... Browse Code »

    Based on 1 normalized pattern(s):

    this program is free software you can redistribute it and or modify
    it under the terms and conditions of the gnu general public license
    version 2 as published by the free software foundation this program
    is distributed in the hope it will be useful but without any
    warranty without even the implied warranty of merchantability or
    fitness for a particular purpose see the gnu general public license
    for more details you should have received a copy of the gnu general
    public license along with this program if not see http www gnu org
    licenses

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

    has been chosen to replace the boilerplate/reference in 228 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Allison Randal
    Reviewed-by: Steve Winslow
    Reviewed-by: Richard Fontana
    Reviewed-by: Alexios Zavras
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

28 Apr, 2016

1 commit

03 Mar, 2016

1 commit

21 Jul, 2015

1 commit

  • 584ac4e93   clk: tegra: Properly include clk.h ... Browse Code »

    Clock provider drivers generally shouldn't include clk.h because
    it's the consumer API. Only include clk.h in files that are using
    it. Also add in a clkdev.h include that was missing in a file
    using clkdev APIs.

    Cc: Peter De Schrijver
    Cc: Thierry Reding
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

10 Apr, 2015

1 commit

  • 63cc5a4da   clk: tegra: Model oscillator as clock ... Browse Code »

    Currently the Tegra clock driver simplifies the clock tree somewhat by
    taking advantage of the fact that clk_m runs at the same frequency as
    the oscillator. While that's true on all currently supported SoCs, it
    does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
    divided down from the oscillator frequency. To support that setup, add
    a separate clock for the oscillator that both clk_m and pll_ref derive
    from.

    Modify the tegra_osc_clk_init() function to take an additional divider
    parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
    will read the divider from a register in the clock & reset controller.

    Signed-off-by: Thierry Reding

    Thierry Reding
     

27 Nov, 2013

1 commit