10 Apr, 2020

1 commit


09 Apr, 2020

2 commits

  • Analogix_dp driver acquires all its resources in the ->bind() callback,
    what is a bit against the component driver based approach, where the
    driver initialization is split into a probe(), where all resources are
    gathered, and a bind(), where all objects are created and a compound
    driver is initialized.

    Extract all the resource related operations to analogix_dp_probe() and
    analogix_dp_remove(), then call them before/after registration of the
    device components from the main Exynos DP and Rockchip DP drivers. Also
    move the plat_data initialization to the probe() to make it available for
    the analogix_dp_probe() function.

    This fixes the multiple calls to the bind() of the DRM compound driver
    when the DP PHY driver is not yet loaded/probed:

    [drm] Exynos DRM: using 14400000.fimd device for DMA mapping operations
    exynos-drm exynos-drm: bound 14400000.fimd (ops fimd_component_ops [exynosdrm])
    exynos-drm exynos-drm: bound 14450000.mixer (ops mixer_component_ops [exynosdrm])
    exynos-dp 145b0000.dp-controller: no DP phy configured
    exynos-drm exynos-drm: failed to bind 145b0000.dp-controller (ops exynos_dp_ops [exynosdrm]): -517
    exynos-drm exynos-drm: master bind failed: -517
    ...
    [drm] Exynos DRM: using 14400000.fimd device for DMA mapping operations
    exynos-drm exynos-drm: bound 14400000.fimd (ops hdmi_enable [exynosdrm])
    exynos-drm exynos-drm: bound 14450000.mixer (ops hdmi_enable [exynosdrm])
    exynos-drm exynos-drm: bound 145b0000.dp-controller (ops hdmi_enable [exynosdrm])
    exynos-drm exynos-drm: bound 14530000.hdmi (ops hdmi_enable [exynosdrm])
    [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
    Console: switching to colour frame buffer device 170x48
    exynos-drm exynos-drm: fb0: exynosdrmfb frame buffer device
    [drm] Initialized exynos 1.1.0 20180330 for exynos-drm on minor 1
    ...

    Signed-off-by: Marek Szyprowski
    Acked-by: Andy Yan
    Reviewed-by: Andrzej Hajda
    Signed-off-by: Andrzej Hajda
    Link: https://patchwork.freedesktop.org/patch/msgid/20200310103427.26048-1-m.szyprowski@samsung.com
    (cherry picked from commit 83a196773b8bc6702f49df1eddc848180e350340)
    Signed-off-by: Maxime Ripard

    Marek Szyprowski
     
  • drm_local_map.offset is not only used for resource_size_t but also
    dma_addr_t which may be of different sizes.

    Reported-by: Nathan Chancellor
    Fixes: 8e4ff9b56957 ("drm: Remove the dma_alloc_coherent wrapper for internal usage")
    Tested-by: Nathan Chancellor # build
    Signed-off-by: Chris Wilson
    Cc: Dave Airlie
    Cc: Nathan Chancellor
    Cc: Linus Torvalds
    Signed-off-by: Daniel Vetter
    Link: https://patchwork.freedesktop.org/patch/msgid/20200402215926.30714-1-chris@chris-wilson.co.uk

    Chris Wilson
     

08 Apr, 2020

4 commits


07 Apr, 2020

10 commits


06 Apr, 2020

1 commit

  • After commit f651c8b05542 ("drm/virtio: factor out the sg_table from
    virtio_gpu_object"), virtio_gpu_create_object allocates too small space
    to fit everything in. It is because it allocates struct
    virtio_gpu_object, but should allocate a newly added struct
    virtio_gpu_object_shmem which has 2 more members.

    So fix that by using correct type in virtio_gpu_create_object.

    Signed-off-by: Jiri Slaby
    Link: http://patchwork.freedesktop.org/patch/msgid/20200319100421.16267-1-jslaby@suse.cz
    Fixes: f651c8b05542 ("drm/virtio: factor out the sg_table from virtio_gpu_object")
    Cc: Gurchetan Singh
    Cc: Gerd Hoffmann
    Signed-off-by: Gerd Hoffmann
    (cherry picked from commit 0666a8d7f6a4530440e59f2d22ed4091f4d3818c)

    Jiri Slaby
     

05 Apr, 2020

1 commit

  • Scatterlist elements contains both pages and DMA addresses, but one
    should not assume 1:1 relation between them. The sg->length is the size
    of the physical memory chunk described by the sg->page, while
    sg_dma_len(sg) is the size of the DMA (IO virtual) chunk described by
    the sg_dma_address(sg).

    The proper way of extracting both: pages and DMA addresses of the whole
    buffer described by a scatterlist it to iterate independently over the
    sg->pages/sg->length and sg_dma_address(sg)/sg_dma_len(sg) entries.

    Fixes: 42e67b479eab ("drm/prime: use dma length macro when mapping sg")
    Signed-off-by: Marek Szyprowski
    Reviewed-by: Alex Deucher
    Signed-off-by: Alex Deucher
    Link: https://patchwork.freedesktop.org/patch/msgid/20200327162126.29705-1-m.szyprowski@samsung.com
    Cc: stable@vger.kernel.org

    Marek Szyprowski
     

04 Apr, 2020

1 commit


03 Apr, 2020

1 commit


02 Apr, 2020

1 commit


01 Apr, 2020

16 commits

  • [Why]
    Some displays have an issue where the hdcp chips are initialized after the
    display has already lit up. This means we can sometimes authentication too early
    and cause authentication failures.

    This happens when HDCP is enabled and the display is power cycled. Normally we
    will authenticate 2 seconds after the display is lit, but some displays need a
    bit more time.

    [How]
    Increase delay to 3 second before we start authentication.

    Signed-off-by: Bhawanpreet Lakha
    Reviewed-by: Nicholas Kazlauskas
    Signed-off-by: Alex Deucher

    Bhawanpreet Lakha
     
  • [Why]
    -We need to cancel future callbacks/watchdogs events when a callback/watchdog event happens

    [How]
    -fix typo in event_callback()
    -cancel callback, not watchdog
    -cancel watchdog events in event_watchdog_timer().

    Signed-off-by: Bhawanpreet Lakha
    Reviewed-by: Nicholas Kazlauskas
    Signed-off-by: Alex Deucher

    Bhawanpreet Lakha
     
  • [Why]
    When content type property is set to 1. We should enable hdcp2.2 and if we cant
    then stop. Currently the way it works in DC is that if we fail hdcp2, we will
    try hdcp1 after.

    [How]
    Use link config to force disable hdcp1.4 when type1 is set.

    Signed-off-by: Bhawanpreet Lakha
    Reviewed-by: Nicholas Kazlauskas
    Signed-off-by: Alex Deucher

    Bhawanpreet Lakha
     
  • This is ASIC specific and should be placed in _ppt.c of each ASIC.

    Signed-off-by: Evan Quan
    Reviewed-by: Alex Deucher
    Signed-off-by: Alex Deucher

    Evan Quan
     
  • This is already done in soc15.c. And this is really ASIC specific
    and should not be placed here.

    Signed-off-by: Evan Quan
    Reviewed-by: Alex Deucher
    Signed-off-by: Alex Deucher

    Evan Quan
     
  • [Why]
    DML expects num_states to exclude the duplicate state.

    [How]
    Set num_states to correct value to prevent array off-by-one error. Also
    refactor max clock level code for diags.

    Signed-off-by: Dmytro Laktyushkin
    Signed-off-by: George Shen
    Reviewed-by: Dmytro Laktyushkin
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Dmytro Laktyushkin
     
  • [Why]
    BT2020 is not supported in COLOR_ENCODING property of planes. Only
    BT601 and BT709 was available.

    [How]
    Allow BT2020 as legit value in setting COLOR_ENCODING property.

    Signed-off-by: Stylon Wang
    Reviewed-by: Nicholas Kazlauskas
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Stylon Wang
     
  • [Why]
    Nominal pixel clock and EDID information differ in precision so although
    monitor reports maximum refresh is 2x minimum, LFC was not being
    enabled.

    [How]
    Use minimum refresh rate as nominal/2 when EDID dictates that min
    refresh = max refresh/2.

    v2: squash in 64 bit divide fix

    Signed-off-by: Aric Cyr
    Reviewed-by: Nicholas Kazlauskas
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Aric Cyr
     
  • [Why]
    CTM was only supported at CRTC level and we need color space conversion
    in linear space at plane level.

    [How]
    - Add plane-level CTM to dc interface
    - Program plane-level CTM in DCN

    Signed-off-by: Stylon Wang
    Reviewed-by: Nicholas Kazlauskas
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Stylon Wang
     
  • [Why]
    Change is causing a regression where the OPC app no longer functions
    properly.

    [How]
    Revert the changelist causing the issue.

    Signed-off-by: Isabel Zhang
    Reviewed-by: Yongqiang Sun
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Isabel Zhang
     
  • [Why]
    In some scenario like 1366x768 VSR enabled connected with a 4K monitor
    and playing 4K video in clone mode, underflow will be observed due to
    decrease dppclk when previouse surface scan isn't finished

    [How]
    In this use case, surface flip is switching between 4K and 1366x768,
    1366x768 needs smaller dppclk, and when decrease the clk and previous
    surface scan is for 4K and scan isn't done, underflow will happen. Not
    doing optimize bandwidth in case of flip pending.

    Signed-off-by: Yongqiang Sun
    Reviewed-by: Tony Cheng
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Yongqiang Sun
     
  • [Why]
    For some monitors extreme flickering can occur while using LFC for if
    we're not doing the DRR timing update for V_TOTAL_MIN / V_TOTAL_MAX at
    the DP start of frame.

    Hardware can default to any time in the frame which isn't the behavior
    we want.

    [How]
    Add a new function for setting the double buffering mode for DRR timing.

    Default to DP start of frame double buffering on timing generator init.

    Signed-off-by: Nicholas Kazlauskas
    Reviewed-by: Aric Cyr
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Nicholas Kazlauskas
     
  • [Why]
    P010 pixel format is not declared as supported in DRM and DM.

    [How]
    Add P010 format to the support list presented to DRM and checked in DM

    Signed-off-by: Stylon Wang
    Reviewed-by: Nicholas Kazlauskas
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Stylon Wang
     
  • [Why]
    Diagnostics scaling test failing to set required number of vertical taps
    in 4:2:0 surface case

    [How]
    In dpp3_get_optimal_number_of_taps() need to use LB_MEMORY_CONFIG_3 for
    4:2:0 surface case. In resource_build_scaling_params() make sure to also
    set plane res alpha enable based on updated surface state

    Signed-off-by: Eric Bernstein
    Reviewed-by: Dmytro Laktyushkin
    Acked-by: Rodrigo Siqueira
    Signed-off-by: Alex Deucher

    Eric Bernstein
     
  • the HPD bo size calculation error.
    the "mem.size" can't present actual BO size all time.

    Signed-off-by: Kevin Wang
    Reviewed-by: Alex Deucher
    Acked-by: Christian König
    Signed-off-by: Alex Deucher

    Kevin Wang
     
  • … drm-intel-next-fixes

    gvt-next-fixes-2020-03-31

    - Fix non-privilege access warning (Tina)
    - Fix display port type (Tina)
    - BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan)
    - Bypass length check of LRI (Yan)
    - Fix one klocwork warning (Tina)

    Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    From: Zhenyu Wang <zhenyuw@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200331070025.GB16629@zhen-hp.sh.intel.com

    Rodrigo Vivi
     

31 Mar, 2020

2 commits

  • This reverts commit 7be1b9b8e9d1e9ef0342d2e001f44eec4030aa4d.

    The drm_mm is supposed to work in atomic context, so calling schedule()
    or in this case cond_resched() is illegal.

    Signed-off-by: Christian König
    Acked-by: Daniel Vetter
    Link: https://patchwork.freedesktop.org/patch/359278/

    Christian König
     
  • Fix a static code checker warning:
    drivers/gpu/drm/xen/xen_drm_front.c:404 xen_drm_drv_dumb_create()
    warn: passing zero to 'PTR_ERR'

    Signed-off-by: Ding Xiang
    Reviewed-by: Oleksandr Andrushchenko
    Signed-off-by: Daniel Vetter
    Link: https://patchwork.freedesktop.org/patch/msgid/1585562347-30214-1-git-send-email-dingxiang@cmss.chinamobile.com

    Ding Xiang