07 Mar, 2020
1 commit
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Pull spi fixes from Mark Brown:
"A selection of small fixes, mostly for drivers, that have arrived
since the merge window. None of them are earth shattering in
themselves but all useful for affected systems"* tag 'spi-fix-v5.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi_register_controller(): free bus id on error paths
spi: bcm63xx-hsspi: Really keep pll clk enabled
spi: atmel-quadspi: fix possible MMIO window size overrun
spi/zynqmp: remove entry that causes a cs glitch
spi: pxa2xx: Add CS control clock quirk
spi: spidev: Fix CS polarity if GPIO descriptors are used
spi: qup: call spi_qup_pm_resume_runtime before suspending
spi: spi-omap2-mcspi: Support probe deferral for DMA channels
spi: spi-omap2-mcspi: Handle DMA size restriction on AM65x
04 Mar, 2020
1 commit
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Some error paths leave the bus id allocated. As a result the IDR
allocation will fail after a deferred probe. Fix by freeing the bus id
always on error.Signed-off-by: Aaro Koskinen
Message-Id:
Signed-off-by: Mark Brown
02 Mar, 2020
1 commit
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The purpose of commit 0fd85869c2a9 ("spi/bcm63xx-hsspi: keep pll clk enabled")
was to keep the pll clk enabled through the lifetime of the device.In order to do that, some 'clk_prepare_enable()'/'clk_disable_unprepare()'
calls have been added in the error handling path of the probe function, in
the remove function and in the suspend and resume functions.However, a 'clk_disable_unprepare()' call has been unfortunately left in
the probe function. So the commit seems to be more or less a no-op.Axe it now, so that the pll clk is left enabled through the lifetime of
the device, as described in the commit.Fixes: 0fd85869c2a9 ("spi/bcm63xx-hsspi: keep pll clk enabled")
Signed-off-by: Christophe JAILLET
Acked-by: Jonas Gorski
Link: https://lore.kernel.org/r/20200228213838.7124-1-christophe.jaillet@wanadoo.fr
Signed-off-by: Mark Brown
29 Feb, 2020
1 commit
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The QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.Fixes: 0e6aae08e9ae ("spi: Add QuadSPI driver for Atmel SAMA5D2")
Signed-off-by: Tudor Ambarus
Link: https://lore.kernel.org/r/20200228155437.1558219-1-tudor.ambarus@microchip.com
Signed-off-by: Mark Brown
27 Feb, 2020
2 commits
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In the public interface for chipselect, there is always an entry
commented as "Dummy generic FIFO entry" pushed down to the fifo right
after the activate/deactivate command. The dummy entry is 0x0,
irregardless if the intention was to activate or deactive the cs. This
causes the cs line to glitch rather than beeing activated in the case
when there was an activate command.This has been observed on oscilloscope, and have caused problems for at
least one specific flash device type connected to the qspi port. After
the change the glitch is gone and cs goes active when intended.The reason why this worked before (except for the glitch) was because
when sending the actual data, the CS bits are once again set. Since
most flashes uses mode 0, there is always a half clk period anyway for
cs to clk active setup time. If someone would rely on timing from a
chip_select call to a transfer_one, it would fail though.It is unknown why the dummy entry was there in the first place, git log
seems to be of no help in this case. The reference manual gives no
indication of the necessity of this. In fact the lower 8 bits are a
setup (or hold in case of deactivate) time expressed in cycles. So this
should not be needed to fulfill any setup/hold timings.Signed-off-by: Thommy Jakobsson
Reviewed-by: Naga Sureshkumar Relli
Link: https://lore.kernel.org/r/20200224162643.29102-1-thommyj@gmail.com
Signed-off-by: Mark Brown -
In some circumstances on Intel LPSS controllers, toggling the LPSS
CS control register doesn't actually cause the CS line to toggle.
This seems to be failure of dynamic clock gating that occurs after
going through a suspend/resume transition, where the controller
is sent through a reset transition. This ruins SPI transactions
that either rely on delay_usecs, or toggle the CS line without
sending data.Whenever CS is toggled, momentarily set the clock gating register
to "Force On" to poke the controller into acting on CS.Signed-off-by: Rajat Jain
Signed-off-by: Evan Green
Link: https://lore.kernel.org/r/20200211223700.110252-1-rajatja@google.com
Signed-off-by: Mark Brown
21 Feb, 2020
2 commits
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Commit f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs")
amended of_spi_parse_dt() to always set SPI_CS_HIGH for SPI slaves whose
Chip Select is defined by a "cs-gpios" devicetree property.This change broke userspace applications which issue an SPI_IOC_WR_MODE
ioctl() to an spidev: Chip Select polarity will be incorrect unless the
application is changed to set SPI_CS_HIGH. And once changed, it will be
incompatible with kernels not containing the commit.Fix by setting SPI_CS_HIGH in spidev_ioctl() (under the same conditions
as in of_spi_parse_dt()).Fixes: f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs")
Reported-by: Simon Han
Signed-off-by: Lukas Wunner
Reviewed-by: Linus Walleij
Link: https://lore.kernel.org/r/fca3ba7cdc930cd36854666ceac4fbcf01b89028.1582027457.git.lukas@wunner.de
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org # v5.1+ -
spi_qup_suspend() will cause synchronous external abort when
runtime suspend is enabled and applied, as it tries to
access SPI controller register while clock is already disabled
in spi_qup_pm_suspend_runtime().Signed-off-by: Yuji sasaki
Signed-off-by: Vinod Koul
Link: https://lore.kernel.org/r/20200214074340.2286170-1-vkoul@kernel.org
Signed-off-by: Mark Brown
06 Feb, 2020
2 commits
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dma_request_channel() can return -EPROBE_DEFER, if DMA driver is not
ready. Currently driver just falls back to PIO mode on probe deferral.
Fix this by requesting all required channels during probe and
propagating EPROBE_DEFER error code.Signed-off-by: Vignesh Raghavendra
Link: https://lore.kernel.org/r/20200204124816.16735-3-vigneshr@ti.com
Signed-off-by: Mark Brown -
On AM654, McSPI can only support 4K - 1 bytes per transfer when DMA is
enabled. Therefore populate master->max_transfer_size callback to
inform client drivers of this restriction when DMA channels are
available.Signed-off-by: Vignesh Raghavendra
Link: https://lore.kernel.org/r/20200204124816.16735-2-vigneshr@ti.com
Signed-off-by: Mark Brown
04 Feb, 2020
1 commit
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'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p).
Hence, IS_ERR(p) is unneeded.The semantic patch that generates this commit is as follows:
//
@@
expression ptr;
constant error_code;
@@
-IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code)
+PTR_ERR(ptr) == - error_code
//Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.org
Signed-off-by: Masahiro Yamada
Cc: Julia Lawall
Acked-by: Stephen Boyd [drivers/clk/clk.c]
Acked-by: Bartosz Golaszewski [GPIO]
Acked-by: Wolfram Sang [drivers/i2c]
Acked-by: Rafael J. Wysocki [acpi/scan.c]
Acked-by: Rob Herring
Cc: Eric Biggers
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
28 Jan, 2020
1 commit
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Pull ioremap updates from Christoph Hellwig:
"Remove the ioremap_nocache API (plus wrappers) that are always
identical to ioremap"* tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap:
remove ioremap_nocache and devm_ioremap_nocache
MIPS: define ioremap_nocache to ioremap
23 Jan, 2020
2 commits
22 Jan, 2020
2 commits
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A read from a Winbond W25Q32FV SPI NOR memory chip on my MMP2 returns
wrong data.It seems like SSE doesn't do the right thing on MMP2 at all. After
enabling the SPI port back again, the FIFO reads return garbage. Things
can be brought back to order by telling the PMU to reset the block.Here's a good transaction with said chip:
# busybox devmem 0xd4035000 32 0x00001987 # SSCR0
# echo 0 >/sys/class/gpio/gpio46/value # (assert CS)
# busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command)
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ef # Correct response
# busybox devmem 0xd4035010 # SSDR
0x00000040
# busybox devmem 0xd4035010 # SSDR
0x00000016
# busybox devmem 0xd4035010 # SSDR
0x00000000
# busybox devmem 0xd4035010 # SSDR
0x00000000
# busybox devmem 0xd4035010 # SSDR
0x00000000
# echo 1 >/sys/class/gpio/gpio46/value # (deassert CS)
#Flipping off an on SSE, then running another transaction:
# busybox devmem 0xd4035000 32 0x00001907 # SSCR0, SSE off
# busybox devmem 0xd4035000 32 0x00001987 # SSCR0, SSE on
# echo 0 >/sys/class/gpio/gpio46/value # (assert CS)
# busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command)
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 32 0x00000000 # SSDR
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff # Garbage!
# busybox devmem 0xd4035010 # SSDR
0x000000ff # Oh no
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# busybox devmem 0xd4035010 # SSDR
0x000000ff
# echo 1 >/sys/class/gpio/gpio46/value # (deassert CS)
#Sometimes the response is not just ones, but something that looks like
bits of a response from a previous transaction.I can't see a fix other than not touching the SSE altogether after the
device is first brought up.Signed-off-by: Lubomir Rintel
Link: https://lore.kernel.org/r/20200118094031.327373-1-lkundrak@v3.sk
Signed-off-by: Mark Brown -
Make use of a core helper to ensure the desired width is respected
when calling spi-mem operators.Otherwise only the SPI controller will be matched with the flash chip,
which might lead to wrong widths. Also consider the width specified by
the user in the device tree.Fixes: 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Michael Walle
Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc
Signed-off-by: Mark Brown
17 Jan, 2020
5 commits
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Modify NPCM perphiral SPI reset support from
direct register access to reset controller support.Signed-off-by: Tomer Maimon
Link: https://lore.kernel.org/r/20200115162301.235926-5-tmaimon77@gmail.com
Signed-off-by: Mark Brown -
Improving spi 8 bit per word mode transfer performance
by using 16 bit per word transfer and receive when the data
length is even and larger than one.Signed-off-by: Tomer Maimon
Link: https://lore.kernel.org/r/20200115162301.235926-3-tmaimon77@gmail.com
Signed-off-by: Mark Brown -
drivers/spi/spi-ti-qspi.c: In function ‘ti_qspi_start_transfer_one’:
drivers/spi/spi-ti-qspi.c:392:8: warning: ‘rx_wlen’ may be used uninitialized in this function [-Wmaybe-uninitialized]
392 | if (rx_wlen >= 32)
| ^
drivers/spi/spi-ti-qspi.c:318:12: note: ‘rx_wlen’ was declared here
318 | u8 rxlen, rx_wlen;
| ^~~~~~~The warning is a false positive; it is not thrown by all compiler versions, e.g.
Red Hat Cross 9.2.1-1 but not Linaro GCC 7.5-2019.12.Signed-off-by: Jean Pihet
Link: https://lore.kernel.org/r/20200115100700.3357-1-jean.pihet@newoldbits.com
Signed-off-by: Mark Brown -
Fixing NPCM BMC Peripheral SPI controller 16 bit
send and receive support by writing and reading
the SPI data in the right order.Signed-off-by: Tomer Maimon
Link: https://lore.kernel.org/r/20200115162301.235926-2-tmaimon77@gmail.com
Signed-off-by: Mark Brown -
Add support for Intel Comet Lake PCH-V which has the same LPSS than on
Intel Kaby lake unlike other Intel Comet Lake PCH variants that are based
on Intel Cannon Lake PCH LPSS.Signed-off-by: Jarkko Nikula
Link: https://lore.kernel.org/r/20200116091035.575175-1-jarkko.nikula@linux.intel.com
Signed-off-by: Mark Brown
15 Jan, 2020
2 commits
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No need to 'goto err;' for just doing a return.
return directly from where the error happens.Signed-off-by: Christophe Leroy
Link: https://lore.kernel.org/r/2a4a7e11b37cfa0558d68f0d35e90d6da858b059.1579017697.git.christophe.leroy@c-s.fr
Signed-off-by: Mark Brown -
Why it does not work at the moment:
- num_chipselect sets the number of cs-gpios that are in the DT.
This comes from drivers/spi/spi.c
- num_chipselect gets set with devm_spi_register_controller, that is
called in drivers/spi/spi.c
- devm_spi_register_controller got called after num_chipselect has
been used.How this commit fixes the issue:
- devm_spi_register_controller gets called before num_chipselect is
being used.Fixes: c7a402599504 ("spi: lpspi: use the core way to implement cs-gpio function")
Signed-off-by: Philippe Schenker
Link: https://lore.kernel.org/r/20191204141312.1411251-1-philippe.schenker@toradex.com
Signed-off-by: Mark Brown
14 Jan, 2020
2 commits
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Optimize the 8-bit based transfers, as used by the SPI flash
devices, by reading the data registers by 32 and 128 bits when
possible and copy the contents to the receive buffer.The speed improvement is 4.9x using quad read.
Signed-off-by: Jean Pihet
Cc: Ryan Barnett
Cc: Conrad Ratschan
Cc: Arnout Vandecappelle
Link: https://lore.kernel.org/r/20200114124125.361429-3-jean.pihet@newoldbits.com
Signed-off-by: Mark Brown -
The TI QSPI IP has limitations:
- the MMIO region is 64MB in size
- in non-MMIO mode, the transfer can handle 4096 words max.Add support for bigger devices.
Use MMIO and DMA transfers below the 64MB boundary, use
software generated transfers above.Signed-off-by: Jean Pihet
Cc: Ryan Barnett
Cc: Conrad Ratschan
Cc: Arnout Vandecappelle
Link: https://lore.kernel.org/r/20200114124125.361429-2-jean.pihet@newoldbits.com
Signed-off-by: Mark Brown
13 Jan, 2020
1 commit
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Currrently the memory for the clk_bulk_data of the QSPI controller
is allocated with spi_alloc_master(). The bulk data pointer is passed
to devm_clk_bulk_get() which saves it in clk_bulk_devres->clks. When
the device is removed later devm_clk_bulk_release() is called and
uses the bulk data referenced by the pointer to release the clocks.
For this driver this results in accessing memory that has already
been freed, since the memory allocated with spi_alloc_master() is
released by spi_controller_release(), which is called before the
managed resources are released.Use device managed memory for the clock bulk data to fix the issue
described above.Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Link: https://lore.kernel.org/r/20200108133948.1.I35ceb4db3ad8cfab78f7cd51494aeff4891339f5@changeid
Signed-off-by: Mark Brown
10 Jan, 2020
2 commits
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Add the driver for the HiSilicon v3xx SPI NOR flash controller, commonly
found in hi16xx chipsets.This is a different controller than that in drivers/mtd/spi-nor/hisi-sfc.c;
indeed, the naming for that driver is poor, since it is really known as
FMC, and can support other memory technologies.The driver module name is "hisi-sfc-v3xx", as recommended by HW designer,
being an attempt to provide a distinct name - v3xx being the unique
controller versioning.Only ACPI firmware is supported.
DMA is not supported, and we just use polling mode for operation
completion notification.The driver uses the SPI MEM OPs.
Signed-off-by: John Garry
Link: https://lore.kernel.org/r/1575900490-74467-3-git-send-email-john.garry@huawei.com
Signed-off-by: Mark Brown -
The "RevPi Connect Flat" PLC offered by KUNBUS has 4 slaves attached
to the BCM2835 SPI master. Raise the maximum number of slaves in the
driver accordingly.Signed-off-by: Lukas Wunner
Reviewed-by: Nicolas Saenz Julienne
Link: https://lore.kernel.org/r/01453fd062de2d49bd74a847e13a0781cbf8143d.1578572268.git.lukas@wunner.de
Signed-off-by: Mark Brown
09 Jan, 2020
1 commit
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STR is a well-known stringify macro so it should be avoided in drivers
to avoid warnings like this (MIPS architecture while compile testing):drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined
#define STR 0x40 /* Status Register */
arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition
#define STR(x) __STR(x)To maintain consistency between all register names add a SI prefix to
all of them. This also matches register names in datasheet.Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Geert Uytterhoeven
Tested-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200108194319.3171-1-krzk@kernel.org
Signed-off-by: Mark Brown
08 Jan, 2020
7 commits
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Add support for GPIO chip selects using GPIO descriptors. As the RSPI
controller always drives a native chip select when performing a
transfer, at least one native chip select must be left unused.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-7-geert+renesas@glider.be
Signed-off-by: Mark Brown -
RSPI variants on some SuperH or R-Mobile SoCs support multiple native
chip selects. Add support for this by configuring the SSL Assert Signal
Setting.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-6-geert+renesas@glider.be
Signed-off-by: Mark Brown -
The set_config_register() macro is used in a single place.
Make the code easier to read by just removing it.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-5-geert+renesas@glider.be
Signed-off-by: Mark Brown -
Use the helper introduced by commit e135303bd5bebcd2 ("device: Add
dev__once variants") instead of open-coding the same operation.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-4-geert+renesas@glider.be
Signed-off-by: Mark Brown -
Currently the MSIOF SPI driver uses custom code to handle the unused
native chip select with GPIO chip selects.
Convert the driver to use the new generic handling in the SPI core.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-3-geert+renesas@glider.be
Signed-off-by: Mark Brown -
Some SPI master controllers always drive a native chip select when
performing a transfer. Hence when using both native and GPIO chip
selects, at least one native chip select must be left unused, to be
driven when performing transfers with slave devices using GPIO chip
selects.Currently, to find an unused native chip select, SPI controller drivers
need to parse and process cs-gpios theirselves. This is not only
duplicated in each driver that needs it, but also duplicates part of the
work done later at SPI controller registration time. Note that this
cannot be done after spi_register_controller() returns, as at that time,
slave devices may have been probed already.Hence add generic support to the SPI subsystem for finding an unused
native chip select. Optionally, this unused native chip select, and all
other in-use native chip selects, can be validated against the maximum
number of native chip selects available on the controller hardware.Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20200102133822.29346-2-geert+renesas@glider.be
Signed-off-by: Mark Brown -
Use platform_get_irq_byname_optional() instead of platform_get_irq_byname()
to avoid below error message during probe:[3.265115] bcm_iproc 68c70200.spi: IRQ spi_lr_fullness_reached not found
[3.272121] bcm_iproc 68c70200.spi: IRQ spi_lr_session_aborted not found
[3.284965] bcm_iproc 68c70200.spi: IRQ spi_lr_impatient not found
[3.291344] bcm_iproc 68c70200.spi: IRQ spi_lr_session_done not found
[3.297992] bcm_iproc 68c70200.spi: IRQ mspi_done not found
[3.303742] bcm_iproc 68c70200.spi: IRQ mspi_halted not foundSigned-off-by: Rayagonda Kokatanur
Link: https://lore.kernel.org/r/20200107040912.16426-1-rayagonda.kokatanur@broadcom.com
Signed-off-by: Mark Brown
07 Jan, 2020
2 commits
-
Because of out-of-order execution about some CPU architecture,
In this debug stage we find Completing spi interrupt enable ->
prodrucing TXEI interrupt -> running "interrupt_transfer" function
will prior to set "dw->rx and dws->rx_end" data, so this patch add
memory barrier to enable dw->rx and dw->rx_end to be visible and
solve to send SPI data error.
eg:
it will fix to this following low possibility error in testing environment
which using SPI control to connect TPM Moduleskernel: tpm tpm0: Operation Timed out
kernel: tpm tpm0: tpm_relinquish_locality: : error -1Signed-off-by: fengsheng
Signed-off-by: Xinwei Kong
Link: https://lore.kernel.org/r/1578019930-55858-1-git-send-email-kong.kongxinwei@hisilicon.com
Signed-off-by: Mark Brown -
Pull spi fixes from Mark Brown:
"A small collection of fixes here, one to make the newly added PTP
timestamping code more accurate, a few driver fixes and a fix for the
core DT binding to document the fact that we support eight wire buses"* tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: Document Octal mode as valid SPI bus width
spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent calls
spi: spi-fsl-dspi: Fix 16-bit word order in 32-bit XSPI mode
spi: Don't look at TX buffer for PTP system timestamping
spi: uniphier: Fix FIFO threshold
06 Jan, 2020
1 commit
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ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.Signed-off-by: Christoph Hellwig
Acked-by: Arnd Bergmann
03 Jan, 2020
1 commit
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dw_spi_irq() and dw_spi_transfer_one concurrent calls.
I find a panic in dw_writer(): txw = *(u8 *)(dws->tx), when dw->tx==null,
dw->len==4, and dw->tx_end==1.When tpm driver's message overtime dw_spi_irq() and dw_spi_transfer_one
may concurrent visit dw_spi, so I think dw_spi structure lack of protection.Otherwise dw_spi_transfer_one set dw rx/tx buffer and then open irq,
store dw rx/tx instructions and other cores handle irq load dw rx/tx
instructions may out of order.[ 1025.321302] Call trace:
...
[ 1025.321319] __crash_kexec+0x98/0x148
[ 1025.321323] panic+0x17c/0x314
[ 1025.321329] die+0x29c/0x2e8
[ 1025.321334] die_kernel_fault+0x68/0x78
[ 1025.321337] __do_kernel_fault+0x90/0xb0
[ 1025.321346] do_page_fault+0x88/0x500
[ 1025.321347] do_translation_fault+0xa8/0xb8
[ 1025.321349] do_mem_abort+0x68/0x118
[ 1025.321351] el1_da+0x20/0x8c
[ 1025.321362] dw_writer+0xc8/0xd0
[ 1025.321364] interrupt_transfer+0x60/0x110
[ 1025.321365] dw_spi_irq+0x48/0x70
...Signed-off-by: wuxu.wu
Link: https://lore.kernel.org/r/1577849981-31489-1-git-send-email-wuxu.wu@huawei.com
Signed-off-by: Mark Brown
