15 Sep, 2016
1 commit
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The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).Acked-by: Duc Dang
Acked-by: Carlo Caione
Acked-by: Michal Simek
Acked-by: Krzysztof Kozlowski
Acked-by: Dinh Nguyen
Acked-by: Masahiro Yamada
Signed-off-by: Marc Zyngier
Signed-off-by: Arnd Bergmann
19 Feb, 2016
1 commit
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Add a compatible string for the Cavium ThunderX PMU.
Signed-off-by: Jan Glauber
Signed-off-by: Will Deacon
09 Jul, 2015
1 commit
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The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.Signed-off-by: Tirumalesh Chalamarla
Acked-by: Marc Zyngier
Signed-off-by: Kevin Hilman
22 Oct, 2014
1 commit
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Moving dts files to vendor subdirs.
Acked-by: Rob Herring
Acked-by: Catalin Marinas
Signed-off-by: Robert Richter
